CN1207667C - Mass high-speed digital signal source based on microcomputer PCI bus - Google Patents

Abstract

A massive high-speed digital signal system based on the PCI bus of a microcomputer, including: a PCI bus controller, used for the PCI bus interface work between the signal system and the microcomputer; data; the local bus controller is used to control the internal coordination of the signal system; the high-speed output port is used to provide a corresponding interface with the debugging system to ensure that the data flow during transmission is stable and error-free output; the digital signal system passes through the PCI bus It is connected with the microcomputer to work together, and outputs various waveform signals stored in the hard disk of the microcomputer according to a certain format and timing. The invention utilizes the friendly man-machine interface characteristics of the Windows operating system to develop corresponding application programs to control the data transmission of the board cards of the signal system, so that the operation of the signal system is simple and intuitive. The design method makes full use of various software and hardware resources in the microcomputer, has low cost, good compatibility, and is convenient and easy to use.

Description

Mass High Speed Digital Signal System Based on Microcomputer PCI Bus

technical field

The invention relates to a digital signal system, in particular to a massive high-speed digital signal system based on a microcomputer PCI bus.

Background technique

With the development of microelectronics technology and large-scale integrated circuits, more and more large-scale digital signal processing systems have been put into operation, such as video-on-demand system VOD (Video-On-Demand), high-definition television HDTV (High-Definition TV), wireless communication system, and synthetic aperture radar SAR (Synthetic Aperture Radar) real-time imaging processing system, etc. These systems require massive high-speed digital signal systems in the process of development, debugging, and integration to replace complex and expensive signal acquisition processes, or to simulate dangerous, unallowable test processes to generate the high-speed digital signals required by the actual system. Input to In the system, various functions and performances of the system are tested and verified. Since the input signals required by these systems are a large number of high-speed digital signals, taking SAR as an example, when the pulse repetition frequency PRF is 2000Hz, 8192 points are sampled at 66.6MHz for each echo, and I and Q are used for each point. When each channel is 8bits, the average data volume per second is about 32MB, and the peak frequency output by burst mode is 66.6MHz. Ordinary signal systems are obviously difficult to meet the requirements, so it is necessary to develop a general signal system suitable for such systems. This signal system is not only an ordinary arbitrary waveform digital signal generator, but also can generate output suitable for various debugging systems. actual signal.

Contents of the invention

The purpose of the present invention is to provide a mass high-speed digital signal system based on a general-purpose microcomputer.

To achieve the above goals, the massive high-speed digital signal system based on the microcomputer PCI bus includes:

PCI bus controller, used for the PCI bus interface work between the signal system and the microcomputer;

The signal storage device is used to temporarily buffer the data transmitted from the hard disk via the PCI bus;

Local bus controller, used to control the coordination work within the signaling system;

The high-speed output port is used to provide the corresponding interface with the debugging system to ensure the smooth and error-free output of the data flow during transmission;

The digital signal system is connected with the microcomputer through the PCI bus to work together, and outputs various waveform signals stored in the hard disk of the microcomputer according to a certain format and time sequence.

The present invention utilizes the processor configured in the microcomputer to generate various waveform signals of the signal system and store them in the hard disk in the microcomputer, or directly store the actual signal to be transmitted in the hard disk. In SDRAM and other memory on the system board, the signal is sent out through the output port of the system board. Utilizing the friendly man-machine interface features of the Windows operating system, the corresponding application program can be developed to control the data transmission of the signal system board, making the operation of the signal system simple and intuitive. The design method makes full use of various software and hardware resources in the microcomputer, has low cost, good compatibility, and is convenient and easy to use.

Description of drawings

Figure 1 is a system block diagram of a high-speed digital signal system;

Figure 2 is a timing diagram of radar echo data.

Detailed ways

As shown in Figure 1, in order to make the signal system have better compatibility and scalability, the interface between the signal system board and the microcomputer must be carefully selected. The PCI (Peripheral Component Expansion Interface) bus is a local bus that provides a high-performance data bus for the main CPU and peripherals. It has the advantages of high performance, low cost, high reliability, and flexible use, and gradually occupies a dominant position in microcomputer systems. Considering these superior performances of the PCI bus, the PCI bus is used as the interface between the digital signal system and the microcomputer system. The board reads the massive data stored in the hard disk of the microcomputer, transmits it to the memory on the board through the PCI bus of the microcomputer at high speed, and then outputs it according to the required frequency and format. Since the peak rate of the PCI bus is 132MB/s, as long as the read and write speed of the hard disk is fast enough, the output rate of the signal system can theoretically approach the peak rate of the PCI bus to 132MB/s, which can fully meet the requirements of SAR and HDTV (the average rate does not exceed 20MB/s) and other massive data processing system performance requirements. At the same time, the data format can be flexibly controlled by programming software on the computer.

The high-speed digital signal system system is mainly composed of four parts, and the functions of each part are as follows:

1. PCI bus controller: It mainly completes the PCI bus interface between the signal system and the microcomputer, so that the microcomputer can identify the signal system board, and transfer the data stored in the hard disk to the signal system board through programming under Windows On the signal storage device, the transmission of the signal is started to realize the control of the signal system.

2. Signal storage device: It is mainly used to temporarily buffer the data transmitted from the hard disk via the PCI bus to ensure the stability of the data flow output by the signal system board, usually using SDRAM. When the required data flow rate is lower than the read/write rate of the hard disk, it is not necessary to add a large-capacity signal storage device on the board, and only need to use a small amount of cache at the high-speed output port and perform corresponding control. When the required output rate is higher than the PCI bus transmission rate, the use of signal storage devices can not be limited by the PCI bus transmission speed, and the data in the SDRAM is output periodically, leaving room for the expansion of the signal system performance.

3. Local bus controller: control the internal coordination of the signal system board, work together with the PCI bus controller, store the data in the hard disk into the signal memory of the board, and convert the data in the memory into the required format , to control the high-speed output port to send out according to the frequency required by the actual system.

4. High-speed output: It mainly provides the corresponding interface with the debugging system to ensure the smooth and error-free output of the data flow during transmission. Corresponding changes can be made according to the different requirements of various debugging systems. When there is no signal memory on the signal system board, it must have a certain buffer capacity to ensure the stability of the output data flow.

The PCI bus specification is very complicated. You can choose a dedicated chip to design the PCI bus interface controller of the signal system. The microcomputer reads and writes the EERPOM on the expansion board through the serial EEPROM interface to complete the configuration of the PCI device. In the PCI interface part, it supports the peak burst transfer rate of PCI2.2 version which can reach 132MB/s. The dedicated chip provides an internal bus interface to complete signal transmission. In the design of the signal system, the interface is used to complete the control of the local bus in the signal system.

The local bus controller can use a dedicated CPU chip; it can also use an EPLD chip, and use VHDL language to write codes to realize the design of hardware control logic, such as the series of ALTERA company. Programming, erasing, and modifying the configuration of the chip according to actual needs are simpler and faster than developing with a CPU. In the design of this signal system, EPLD chip is used to realize the local bus control on the signal system, and write the data into SDRAM, the storage device on the board. When outputting data, convert the corresponding data format and control the output frequency. These functions are realized through VHDL language programming.

The storage device on the signal system board can choose SDRAM with a certain capacity according to actual needs. When applied to HDTV system debugging, 64MB SDRAM can be selected to store several image data to facilitate rolling output test. If the data rate is lower than the read rate of the hard disk, SDRAM can also be omitted to simplify the design.

The selection of high-speed output ports depends entirely on the data input requirements of the actual application system. Usually, FIFO (first-in-first-out) can be selected, and data streams of different frequencies can be obtained by controlling the clock at the output end of the FIFO, so as to realize asynchronous communication with the actual system. The definition of the output interface of FIFO is realized by programming the local bus controller EPLD chip with VHDL language, so for the test system with different interfaces, as long as the software programming of EPLD with VHDL language can realize the change of the interface protocol, there is no need to modify the interface protocol at all. The hardware circuit is modified.

The software design of the high-speed digital signal system is mainly to develop a driver program for the signal system, so that the data stored in the hard disk of the microcomputer can be output through the signal system. In order to improve the versatility of the system, a widely used Win95/98 driver is developed to control and complete various operations directly related to the signal system and hardware. Driver development can use some dedicated tool packages.

The driver program runs on the bottom layer of the system and is called by the application program, so the application program with window interface is developed for the signal system with MicrosoftVC++. In the application program, the driver program must be loaded first, and then various operations are performed on the hardware by calling the program to control the hardware, such as preparing to transfer data, starting the transfer, ending the transfer, etc., and unloading the driver program when the application program exits. Users only need to click the corresponding button on the window interface to realize the above functions.

After completing all the software and hardware design, it is necessary to generate a hardware description file My Card.INF and add it to the system so that the operating system can correctly identify the high-speed digital signal system board and allocate the required system resources during system initialization.

Example

During the development of the real-time imaging processing system, a digital signal system for simulating radar echo signals is required at the input of the imaging processor. Since the radar works in the way of transmitting pulse trains, the radar echo signal is also a pulse train, that is, the signal is in burst mode. During the duration of each pulse, 8192 points are sampled with a 66.6M clock, and each point is divided into two channels of I and Q, each with 8 bits (as shown in Figure 2), and the highest pulse transmission frequency (PRF) is 2000Hz. It can be seen from this that the amount of data output by the radar signal is large, and the peak speed is very high (up to 66.6×2MB/s). Although the average rate has dropped due to the fact that it is only sent during the burst, the average data volume per second still reaches about 32MB/s when PRF=2000, and the corresponding signal system is required to be a high-speed data source device to complete the burst high-speed data output.

The digital signal system based on the microcomputer PCI bus designed above is adopted, and the PCI 32-bit address and data multiplexing bus channel are selected. The clock frequency is 33MHz. It can complete the task of receiving radar data from the microcomputer and simulating radar data output to the real-time imaging system according to the radar working mode.

The amount of original data of SAR is very large. Generally, for an image of 8Kbytes*1Kbytes with a downsampling rate of 11:1, the amount of original data is 176Mbytes. When the azimuth lines of the image increase, the amount of data will be even larger. If the capacity of the SDRAM configured on the signal system board is too large, its management will be very complicated. In order to simplify the design, SDRAM can not be configured on the signal system board, and the memory of the microcomputer can be used directly, and high-speed FIFO can be configured at the output port. First read the data to the microcomputer memory, and then transfer it to the FIFO for output through the PCI bus.

In the work of debugging the real-time imaging processor, we first store the real radar data in the microcomputer hard disk in a certain format. When simulating the transmission process of real radar data, first transfer the data in the hard disk into the memory, and then use the control channel to transfer the data from the memory to the signal system board, and control the FIFO with a capacity of 8192*16bits to receive data. After the FIFO is full of data, it outputs the data in the FIFO with a 66.6MHz clock, and then receives the following data, and so on. If the amount of data to be transmitted is less than the memory capacity of the system, you can first establish a transmission linked list, read all the data into the memory connected to the linked list, and then output it repeatedly through the PCI bus. These are all implemented by the application program calling the driver of the signal system.

After actual testing, the test results of the signal system are shown in Table 1 below. It can be seen that the transmission of the signal system

memory occupied by data The number of transmission linked list nodes point to memory per node Signal system transmission rate 1MB 16 64KB 72MB/s 1MB 16*4 16KB 70MB/s-72MB/s 8MB 16*32 16KB 71MB/s 16MB 16*16 64KB 72MB/s 32MB 16*128 16KB 71MB/s 128MB 16*128 16KB 71MB/s 176MB 16*176 64KB 71MB/s

Table 1 Signal system transmission rate test results

The rate is not sensitive to the number of nodes transferring the linked list and the amount of transfer per node. Its average transmission speed can reach 70MB/s, fully meeting the test requirements for high-speed systems such as HDTV systems and SAR real-time imaging systems.

When the amount of data exceeds the system memory capacity, it can only read data from the hard disk while transferring data. The application program makes corresponding changes. After the transfer link list is established, the application program first reads a part of the data to fill the memory block pointed to by the transfer link list, starts the transfer, and then reads the next part of data to the same memory block after the transfer is completed. , restart the transfer, and so on. Obviously, as long as the average read rate of the hard disk can reach the required 32MB/s, the average output rate of the signal system can meet the debugging requirements of the SAR real-time imaging processing system. For IDE hard drives that cannot meet this speed requirement, you can configure a RAID (Redundant Array of Independent Disks) card with PCI-IDE interface to make it work in RAID 0 mode, that is, the data is stored in sequence on the member disks that make up the array, so that it can be simultaneously Read data on multiple hard disks to increase the data reading rate. In order to further increase the speed, two transmission linked lists can be established at the same time. When the application program reads data into one of them, the other linked list is transmitted. The two linked lists alternately write and transmit data, which can make the transmission average data rate of the signal system Maintained at 30MB/b (two IBM 60GXP 40G hard drives, 7200 RPM, IDE interface), which can basically meet the speed requirements of the SAR real-time imaging processor when the PRF is 2000.

Compared with other existing signaling systems, this signaling system has the following characteristics:

1. It is a high-speed, massive digital signal system. Its output instantaneous rate is 66.6×2MB/s, the average output rate of the static data in the memory can reach 70MB/s, and the average output rate of the flow data (read from the microcomputer hard disk) can also reach about 50MB/s (depending on HDD read rate).

2. Simple structure and low cost. Since the signal system makes full use of the commonly used microcomputer processor, memory, hard disk and Windows operating system and other software and hardware resources, the structure of the signal system is very simple, the components used are less, the development cost is low, and the cycle is short. .

3. It has good versatility. Since the signal system conforms to the microcomputer PCI bus specification, it can work normally if it is inserted into any microcomputer PCI bus slot, as long as the driver is installed correctly. This signal system is not just an ordinary arbitrary waveform digital signal generator, but also can generate and output actual signals suitable for various debugging systems, to replace complicated and expensive signal acquisition processes, or to simulate dangerous and unallowable test conditions. process. For example, it can provide test signals for various signal processing systems such as HDTV systems, wireless communication systems, and pulse Doppler radar systems.

4. It has good flexibility. As long as the actual required data is stored in the microcomputer hard disk in advance, the signal system can output various signals. For various test systems with different interfaces, only need to program EPLD with VHDL language to change the definition of FIFO output interface according to different interface protocols, without changing the hardware circuit, it can be used for various test systems Provide the required test signals.

5. It has good scalability. For different test systems, the required storage devices can be configured on the signal system board as required. Since the signal system strictly complies with the PCI standard, it can be improved with the upgrade of the PCI protocol.

6. Easy to operate. Due to the development of a window interface application program based on the Windows operating system, you only need to click the above buttons to complete the corresponding functions, without any complicated operations.

Claims (5)

1. mass high-speed digital signal system based on microcomputer PCI bus comprises:

Pci bus controller is used for the pci bus interface work between signal system and the microcomputer;

Signal storage equipment is used for the data that temporary cache transmits from hard disk via pci bus;

Local bus control is used for the co-ordination of control signal internal system;

The high-speed output end mouth is used to provide and the debug system corresponding interface, steady, the errorless output of data stream when guaranteeing transmission;

Described digital signaling system is by the pci bus collaborative work that links to each other with microcomputer, will be stored in various waveform signals in the hard disk of microcomputer by certain format, sequential output.

2. by the described signal system of claim 1, it is characterized in that described signal storage equipment is SDRAM.

3. by the described signal system of claim 1, it is characterized in that described microcomputer directly is stored in the actual signal that will transmit in the hard disk.

4. by the described signal system of claim 1, it is characterized in that described high-speed output end mouth adopts first-in first-out.

5. by the described signal system of claim 1, it is characterized in that described local bus control adopts the EPLD chip.

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