CN120730630B

CN120730630B - Board card hole development process determining method and electronic equipment

Info

Publication number: CN120730630B
Application number: CN202511196921.4A
Authority: CN
Inventors: 孟瑶
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2025-08-26
Filing date: 2025-08-26
Publication date: 2025-11-14
Anticipated expiration: 2045-08-26
Also published as: CN120730630A

Abstract

This invention provides a method for determining the via development process of a printed circuit board (PCB) and an electronic device, which can be applied to the field of printed circuit board processing technology. The method for determining the via development process includes: determining the effective area of the PCB based on its shape; determining the area occupied by the physical layout of the multiple devices and the area occupied by the wiring between the multiple devices under the via process based on the layout information of multiple devices related to the PCB, thereby obtaining the occupied area of the PCB; and determining the via development process of the PCB based on the effective area and the occupied area.

Description

Board card hole development process determining method and electronic equipment

Technical Field

The invention relates to the technical field of printed circuit board processing, in particular to a method for determining a board through hole development process and electronic equipment.

Background

With the development of computer technology, the products of a storage system, such as a high-density storage server control motherboard, a storage SSD (Solid STATE DRIVE, solid state disk) board and other board card products, are developed towards miniaturization and integration, and the characteristics of multiple pins of the products lead to the problem of insufficient space of the whole board in the process of layout and wiring.

In the related art, a process of lifting a PCB (Printed Circuit Board ) may be used to lift space utilization of a board card, but such a process generally requires additional processes, making the manufacturing cost of the PCB high.

The selection of engineers for the development process of the PCB through hole usually depends on personal experience, so that problems of reworking and over-designing of the design can occur in the development process of the PCB, and the development requirements of high efficiency, low cost and high reliability of the board card of the storage product can not be met.

Disclosure of Invention

In view of the above, the invention provides a board through hole development process determining method and electronic equipment.

According to one aspect of the invention, a board card through hole development process determining method is provided, which comprises the steps of determining the effective area of a board card to be developed based on the shape of the board card to be developed, determining the occupied area of the body layout of a plurality of devices and the occupied area of wiring among the devices in a through hole process state based on layout information of the plurality of devices related to the board card to be developed, obtaining the occupied area of the board card to be developed, and determining the through hole development process of the board card to be developed based on the effective area and the occupied area.

According to another aspect of the present invention there is provided an electronic device comprising one or more processors and a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the method.

Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

Fig. 1 shows a flowchart of a board cartoon hole development process determination method according to an embodiment of the present invention.

Fig. 2 shows a schematic structural diagram of a board to be developed according to an embodiment of the present invention.

Fig. 3A is a schematic structural diagram of a board to be developed according to another embodiment of the present invention.

Fig. 3B shows a schematic diagram of an equivalent routing area according to an embodiment of the present invention.

Fig. 4A shows a schematic diagram of a power topology of a single power module according to an embodiment of the invention.

Fig. 4B shows a schematic diagram of a power topology of a multi-power module according to an embodiment of the invention.

Fig. 5 shows a block diagram of an electronic device adapted to implement the method for determining a board card via development process according to an embodiment of the invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It may be evident, however, that one or more embodiments may be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The terms "comprises," "comprising," and/or the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be construed to have meanings consistent with the context of the present specification and should not be construed in an idealized or overly formal manner.

Where a convention analogous to "at least one of A, B and C, etc." is used, in general such a convention should be interpreted in accordance with the meaning of one of skill in the art having generally understood the convention (e.g., "a system having at least one of A, B and C" would include, but not be limited to, systems having a alone, B alone, C alone, a and B together, a and C together, B and C together, and/or A, B, C together, etc.).

In a storage product system, a card product such as a high-density storage server control main board, a storage SSD card and the like often has the characteristic of more total PIN (PIN) numbers of the card due to complex functional requirements. Meanwhile, the size of such boards is generally small, limited by the development trend of miniaturization and integration of products. This "multiple PIN count, small size" feature directly results in a severe challenge of the overall board facing space starvation during place and route.

When the layout and wiring space is insufficient, if a conventional through hole board process is adopted, the design requirement is often difficult to meet, so that the board design scheme is not feasible. To solve this problem, a method for improving the PCB process is generally adopted in the industry, for example, a POFV (Plating overlay FILLED VIA) process is adopted. The POFV technology is characterized in that through holes are directly punched in bonding pads of devices, and then electroplating and filling processing is carried out on the through holes, so that the space utilization rate of the board card is effectively improved, and more available space is provided for layout and wiring. However, the POFV process requires additional processes compared to the conventional via process, which directly results in significantly higher manufacturing costs of the PCB.

At present, in the development process of the PCB board card, whether the layout and wiring space is enough or not is judged, whether special processes such as POFV and the like are needed or not is judged, subjective judgment is mainly carried out according to personal experience of engineers, and scientific theory support and objective quantification basis of a system are lacked. This manner of experience-dependent decision-making poses a series of problems due to individual experience differences, technical habits and risk preferences of different engineers. For example, some engineers worry that the space is insufficient when the layout and wiring is performed to the middle and late stages, and if the POFV process is needed to be changed, a great amount of design rework is caused, and serious project delay and development cost are caused, so that the conventional process is not feasible in the early stage of the project, the POFV process is adopted too early, and a large design margin is reserved. For example, some engineers judge that the conventional through hole process is enough to meet the requirement by means of personal feel, consider that the risk is controllable, but actually find that the layout and wiring space is insufficient when the development process advances to the later stage, at the moment, the space problem has to be solved by reworking to adjust the design and adding special processes such as POFV, and the like, which also causes a great deal of reworking workload, seriously affects the development progress of the project, and causes the development cost to rise and the resource waste.

In summary, the current method for judging the development process of the cartoon holes of the PCB by only personal experience and subjective feeling has obvious defects, and cannot meet the development requirements of high efficiency, low cost and high reliability of the board card of the storage product. Therefore, how to accurately and objectively determine the process to be adopted in the early stage of the development of the PCB board card by utilizing intelligent means such as an algorithm and the like based on scientific theory and objective practical data becomes a technical problem to be solved in the field.

In view of this, the embodiment of the invention provides a method for determining a board through hole development process and electronic equipment, aiming at solving the problems of over design, increased cost, large reworking amount and the like existing in the board through hole development process determined by relying on personal experience. The method for determining the board card hole development process comprises the steps of determining the effective area of a board card to be developed based on the shape of the board card to be developed, determining the occupied area of the body layout of a plurality of devices and the occupied area of wiring among the devices in the state of a through hole process based on layout information of the plurality of devices related to the board card to be developed, obtaining the occupied area of the board card to be developed, and determining the through hole development process of the board card to be developed based on the effective area and the occupied area. The determination method for the board cartoon hole development process provided by the embodiment of the invention can realize scientific and accurate determination of the board cartoon hole development process of the PCB by systematic data processing and operation from the aspect of development feasibility on the basis of meeting the requirements of multiple fields such as structural limitation requirements, manufacturability, signal integrity and the like, and provides powerful support for high-efficiency, low-cost and high-quality development of the board card of a storage product.

As shown in FIG. 1, the method includes operations S110-S130.

In operation S110, an effective area of the board to be developed is determined based on the shape of the board to be developed.

In operation S120, based on layout information of a plurality of devices related to the board to be developed, an area occupied by body layout of the plurality of devices and an area occupied by wiring between the plurality of devices in a state of the through hole process are determined, and an occupied area of the board to be developed is obtained.

In operation S130, a through hole development process of the board to be developed is determined based on the effective area and the occupied area.

The board to be developed can be various PCB boards with the characteristics of multiple PIN numbers, small size and the like, for example, the board can be a high-density storage server control main board in a storage product system, a storage SSD board and other board products, and the board is not limited herein.

The shape of the board to be developed can be set by a developer when the board drawing of the board is performed. For example, a developer may draw a board diagram of a board using specific software, and when drawing the board diagram, may draw one or more closed curves in a specific layer of the board, where the one or more closed curves may define a shape of the board to be developed.

The effective area of the board to be developed may refer to the area of the board to be developed that may be used for the layout of components and routing between components. Optionally, one or more closed curves may be used to represent a shape profile of the board card, a shape profile of a no-wiring area in the board card, and the like, based on the one or more closed curves, a total area of the board card to be developed and an area of the no-wiring or no-wiring component area on the board card to be developed may be determined, and the effective area may be represented as a difference between the total area of the board card to be developed and the area of the no-wiring or no-wiring component area on the board card to be developed.

Or the shape of the board to be developed can be defined by the structural design parameters of the board imported through the system, and correspondingly, the effective area of the board to be developed can be calculated according to the imported structural design parameters. For example, information such as physical dimensions of the board, a structure restriction area reserved at an edge of the board, a mounting location area of a fixing device on the board which is not available for layout wiring, and the like can be imported through the system. The total area of the board card to be developed and the area of the board card to be developed, which is prohibited from wiring or is prohibited from being laid, can be calculated according to the imported information, and the difference between the total area of the board card to be developed and the area of the board card to be developed, which is prohibited from being wired or is prohibited from being laid, is calculated, so that the effective area of the board card to be developed is obtained.

Layout information for a plurality of devices associated with a board to be developed may include locations of at least some of the devices in the board to be developed. The at least some devices may include chips of a board card, connectors, and the like. After determining the frame of the board, the devices such as the chip and the connector can be arranged in the board diagram of the board so as to determine the layout information of the devices such as the chip and the connector.

In the embodiment of the invention, the occupied area of the board card to be developed can be expressed as the area occupied by the device layout and wiring calculated under the state of the layout mode based on the devices such as a chip and a connector, and the occupied area of the board card to be developed can be correspondingly changed after the layout positions of the devices such as the chip and the connector are replaced. For example, in one example, connector A1 may be disposed at a first edge of the board, connector A2 may be disposed at a second edge of the board, the first and second edges may be adjacent two edges, the length of the trace between connector A1 and connector A2 may be B1, in another example, connector A1 may be disposed at the first edge of the board, connector A2 may be disposed at a third edge of the board, the first and third edges may be opposite two edges, the length of the trace between connector A1 and connector A2 may be B2, then the values of B1 and B2 may not be equal, i.e., the area occupied by the trace between the two example connectors A1 and A2 may not be equal, such that the calculated footprints in the two examples are not equal.

The size relation between the effective area and the occupied area can be compared to determine that the board card to be developed is suitable for adopting a through hole process or a special process such as POFV. For example, when the effective area is larger than the occupied area, it can be considered that the layout of all components and signal wires thereof can be realized by adopting the through hole process, and at this time, the through hole development process of the board to be developed can be determined to be the through hole process. If the effective area is smaller than the occupied area, the through hole technology can be considered to be adopted to realize the arrangement of all components and signal wires thereof, and at the moment, the through hole development technology of the board card to be developed can be determined to be a special technology such as POFV.

According to the embodiment of the invention, the technology to be adopted for board card development is determined according to the numerical relationship between the actual effective area of the board card obtained by calculation and the actual required conventional through hole technology area value by precisely solving the effective area of the board card and carefully calculating the layout and wiring area influencing the technology selection, so that the problems of over design, cost increase, large reworking amount and the like existing in the board card hole development technology determined by relying on personal experience are effectively solved, the scientific and accurate determination of the board card hole development technology is realized, and powerful support is provided for the efficient, low-cost and high-quality development of the board card of a storage product.

The method for determining the development process of the board-card holes shown in fig. 1 will be further described with reference to the accompanying drawings in combination with specific embodiments.

The calculation of the effective area of the board card to be developed can be obtained by subtracting the area of the device and the wire forbidden in the board card to be developed from the total area of the board card to be developed.

Optionally, when the development design of the board to be developed is performed, one or more closed curves drawn by a developer in a specific layer of the board may form one or more shape elements, and the shape elements are recorded in a corresponding board structure file. By analyzing the structure file, a plurality of shape elements included in the board to be developed can be determined, and the type of each shape element, the area of the area defined by each shape element and the like can be determined. The total area of the board card to be developed and the area of the area where the devices and the wires are forbidden to be laid in the board card to be developed can be obtained respectively by screening the shape elements and calculating the areas of the shape elements, and the effective area of the board card to be developed is calculated based on the total area of the board card to be developed and the area of the area where the devices and the wires are forbidden to be laid in the board card to be developed.

The method comprises the steps of analyzing a board structure file of a board to be developed to obtain a plurality of shape elements, determining a first target shape element and at least one second target shape element from the plurality of shape elements based on the type of the shape elements and the board diagram level where the shape elements are located, and determining the effective area of the board to be developed based on the area of the first target shape element and the area of the at least one second target shape element.

The board card structure file can be input into corresponding PCB design software, and the elements are screened based on the shape attribute by consulting the command so as to obtain a plurality of shape elements.

For the plurality of shape elements obtained by preliminary screening, the type of each shape element and the level of the plate diagram are taken as keywords, corresponding target attribute information is extracted from attribute information contained in the shape element, each element can be numbered, and the target attribute information of each element, the area of each element and other key information are recorded in a data table together, as shown in table 1. In table 1, 9 shape elements may be included. The type of the shape element Item1 is a circuit board geometry, the type of the shape element Item1 is a border layer, the area is a1, the type of the shape element Item2 is a circuit board geometry, the type of the shape element Item3 is a cut-off layer, the area is a3, the type of the shape element Item4 is a wire forbidden region, the type of the shape element Item4 is a first surface layer, the area is a4, the type of the shape element Item5 is a wire forbidden region, the type of the shape element Item5 is a second surface layer, the area is a5, the type of the shape element Item6 is a layout region, the type of the shape element Item7 is a layout region, the type of the plate layer is a first surface layer, the area is a7, the element height threshold is b1, the type of the shape element Item8 is a layout region, the type of the second surface layer is a9, the element level of the element Item is a9, the element level of the element level is b9, and the element level of the element level is a 9. The first surface layer may be, for example, a TOP layer of a TOP-level board, and the second surface layer may be, for example, a BOTTOM layer of a BOTTOM-level board.

TABLE 1

As shown in fig. 2, the board to be developed may be composed of a single PCB board, and the frame of the PCB board may be represented as a first shape element 201, such as shape element Item1 or shape element Item2 in table 1.

In the PCB board card represented by the first shape element 201, a circular opening may be provided, which may be used as a mounting position of the PCB board card, through which the PCB board card may be mounted to the structural member. In manufacturing the PCB board, the board at the circular opening area needs to be cut away, i.e. the circular opening may be represented as a second shape element 202, such as shape element Item3 in table 1.

A layout inhibition area, such as a single-diagonal shadow area in fig. 2, may be provided in an edge area of the PCB board card represented by the first shape element 201, where layout of components and wires is inhibited, so as to ensure good electrical isolation of the PCB board card. The single-slashed region may be represented as a third shape element 203, such as shape element Item4 or shape element Item5 in table 1.

A limited layout area, such as the double-diagonal hatched area in fig. 2, may be provided on the PCB board represented by the shape element Item1, where the height of the components disposed thereon is different due to the limitation of the structural members and the requirement of electrical isolation between adjacent boards. The double-hatched area may be represented as a fourth shape element 204, such as shape element Item6, shape element Item7, shape element Item8, or shape element Item9 in table 1.

After the information extraction of the respective shape elements is completed, filtering may be performed based on the extracted information to determine at least one first target shape element and at least one second target shape element from the plurality of shape elements.

Specifically, for each shape element, the shape element may be determined to be a first target shape element when the type of the shape element is a circuit board geometry and the board level in which the shape element is located is a border layer, a second target shape element when the type of the shape element is a circuit board geometry and the board level in which the shape element is located is a cut-out layer, a second target shape element when the type of the shape element is a wire forbidden area and the board level in which the shape element is located is a first surface layer or a second surface layer of a board to be developed, and a first surface layer when the type of the shape element is a layout constraint area and the board level in which the shape element is located is a first surface layer and the component height of the shape element is less than a threshold value of a preset value.

For example, if the preset value is set to be smaller than b1 and larger than b2, 9 shape elements as shown in table 1 are targeted. For the shape element Item1, the type is the geometric shape of the circuit board, the board diagram layer is a frame layer, and the shape element Item1 is a first target shape element; for shape element Item2, whose type is circuit board geometry, the located board level is a border layer, then shape element Item2 is a first target shape element, for shape element Item3, whose type is circuit board geometry, the located board level is a cut-out layer, then shape element Item3 is a second target shape element, for shape element Item4, whose type is a wire exclusion region, then shape element Item4 is a second target shape element, for shape element Item5, whose type is wire exclusion region, the located board level is a second surface layer, then shape element Item5 is a second target shape element, for shape element Item6, whose type is a layout region, the located board level is a first surface layer, and whose component height threshold value b1 is greater than the preset value, thus the shape element Item6 can be removed, for shape element Item7, whose type is a layout region, the located board level is a first surface layer, the preset value is less than the first surface layer, but the shape element Item2 can be located in the second surface layer, thus the shape element Item can be removed from the first surface layer, the surface layer is a second surface layer, the shape element Item can be removed from the second surface layer, the surface layer is a surface layer 8, and the shape element Item can be removed from the surface layer, the surface layer is a surface layer 8, the surface layer is a surface layer, and the surface layer is a surface layer 8.

The sifted-out shape elements may be as shown in table 2, and among the 6 shape elements included in table 2, the first shape element may include Item1 and Item2, and the second shape element may include Item3, item4, item5, and Item7.

TABLE 2

The area of the first target shape element can be expressed as the total board card area of the board card to be developed, and the area of the second target shape element can be expressed as the area of the board card to be developed, which is forbidden to conduct device and wire arrangement.

Alternatively, the effective area of the board to be developed may be determined based on the area of the first target shape element and the area of the at least one second target shape element. Specifically, the area of the invalid region can be obtained based on the sum of the areas of at least one second target shape element, and the effective area of the board card to be developed is obtained by subtracting the area of the invalid region from the sum of the areas of at least one first target shape element.

Taking table 2 as an example, the area of at least one second target shape element may be summed to obtain an ineffective area sn=a3+a4+a5+a7, and the area of at least one first target shape element may be summed to obtain a total board area sd=a1+a2, and then the effective area of the board to be developed may be expressed as s0=sd-sn=a1+a2-a 3-a4-a5-a7.

Optionally, the plurality of devices may include a plurality of first devices, and accordingly, the occupied area of the board to be developed may include an area occupied by the body layout of the plurality of first devices and an area occupied by the routing of the wires between the plurality of first devices.

The method comprises the steps of analyzing a board layout file of a board to be developed to determine connection topology and respective layout positions of a plurality of first-type devices, determining first layout areas of the plurality of first-type devices based on the connection topology, determining wiring areas among the plurality of first-type devices based on the connection topology and the respective layout positions of the plurality of first-type devices, and obtaining occupied areas based on the first layout areas and the wiring areas.

The board layout file may be a file obtained after the layout of the plurality of first-type devices is completed. The layout file of the board can be analyzed, and the first devices such as chips, connectors and the like included on the board to be developed can be determined through keywords of packaging such as chips, connectors and the like. By inquiring the shape attribute in the board layout file, the layout position, the body area, the connection topology and other information of each first type device can be obtained, the number is respectively allocated to each first type device based on the device type, and the information and the number are filled into a data table together, so that the data table shown in the table 3 can be obtained. The connection topology may be expressed as a connection relationship between the respective first type devices. The layout position of a first type device may be expressed as coordinates of a geometric center point of the first type device.

As shown in table 3, 4 first devices, that is, a chip U1, a chip U2, a connector J1, and a connector J2, may be obtained by analyzing a board layout file of a board to be developed, where in a coordinate system using a lower left corner of the board to be developed as an origin, a layout position of the chip U1 may be (x 1, y 1), a body area c1, and a number of outgoing lines d1, a layout position of the chip U2 may be (x 2, y 2), a body area c2, a number of outgoing lines d2, a layout position of the connector J1 may be (x 3, y 3), a body area c3, a number of outgoing lines d3, a layout position of the connector J4 may be (x 4, y 4), a body area c4, and a number of outgoing lines d4.

TABLE 3 Table 3

As shown in fig. 3A, a board to be developed may be provided with a first chip 301 and a second chip 302, and a first pin 3011 of the first chip 301 may be connected to a second pin 3021 of the second chip 302 through a signal trace 303. The contact area of the signal trace 303 with the first pin 3011 may form a first wire-out area 3012 of the first pin 3011, and the contact area of the signal trace 303 with the second pin 3021 may form a second wire-out area 3022 of the second pin 3021.

The outgoing line region may be represented as a transition region between the pins of the first type of device and the high speed signal trace. The layout area of the first type device can be obtained according to the area occupied by the body of the first type device and the area occupied by the outgoing line area of the first type device. The method comprises the steps of determining the number of outgoing lines of a first type device based on connection topology, determining the area of the outgoing lines of the first type device based on the number of the outgoing lines of the first type device and the type of the outgoing lines of the first type device, and obtaining a first layout area based on the area of the outgoing lines and the area of a body of the first type device.

The area of the outgoing line area of a single pin of the first type device can be determined according to the outgoing line type of the first type device. The area of the outgoing line region corresponding to each outgoing line type may be preset, for example, if the outgoing line type of the first type device is an X1 type, the area of the outgoing line region may be set to m1, if the outgoing line type of the first type device is an X2 type, the area of the outgoing line region may be set to m2, and so on.

The first type of device has an outgoing line type of X2, which may indicate that a single pin may lead out 2 high-speed signal wires. When calculating the area of the outgoing line area, the area of the outgoing line area of the corresponding X2 wiring is required to be divided by 2, so as to obtain the area of the outgoing line area of the single high-speed signal wiring.

Taking 4 first-class devices shown in table 3 as an example, the outgoing line types of the chip U1 and the chip U2 are X2 types, the first layout area su1=c1+d1×m2/2 of the chip U1, and the first layout area su2=c2+d2×m2/2 of the chip U2. The outgoing line types of the connector J1 and the connector J2 are X1 types, and the first layout area sj1=c3+d3×m1 of the connector J1 and the first layout area sj2=c4+d4×m1 of the connector J2.

Optionally, based on the connection topology between the plurality of first-class devices obtained by analysis, the number of signal wires between the first-class devices can be determined, and under the condition that the width of each signal wire is basically consistent, the area occupied by the wires between the first-class devices can be further determined by combining the relative position relationship between the first-class devices. The method comprises the steps of determining the number of signal wires between a first device and a second device in a plurality of first devices based on connection topology between the first device and the second device, determining an equivalent wiring area based on the layout position of the first device, the layout position of the second device, the number of signal wires and a preset signal wire width, and obtaining the wiring area between the first device and the second device based on the area of the equivalent wiring area.

Taking 4 first-type devices shown in table 3 as an example, the number of signal traces between 4 first-type devices can be obtained based on the connection topology between the 4 first-type devices, as shown in table 4. In table 4, the number of signal traces between the chip U1 and the chip U2 may be e1, the number of signal traces between the chip U1 and the connector J1 may be e2, the number of signal traces between the chip U1 and the connector J2 may be e3, the number of signal traces between the chip U2 and the connector J1 may be e4, and the number of signal traces between the chip U2 and the connector J2 may be e5. The transmitting end may be denoted as a first device as described above and the receiving end may be denoted as a second device as described above.

TABLE 4 Table 4

In order to ensure impedance uniformity and signal delay uniformity, the widths of the plurality of signal traces between the transmitting end and the receiving end, the pitches between the plurality of signal traces, and the lengths of the plurality of signal traces may generally be kept uniform. Therefore, the lengths and widths of the plurality of signal wires can be equivalently obtained based on the lengths and widths of the single signal wires, so that the occupied area of the wires between the transmitting end and the receiving end is obtained, and the wire area between the corresponding first device and the second device is obtained.

Alternatively, in performing calculation of the wiring area, equivalent line widths of the plurality of signal wirings may be determined first. If the line width of the signal trace is w1 and the interval between the signal traces is w2, the equivalent line width of the plurality of signal traces between the first device and the second device may be represented as f= (w1+w2) ×e+w2, and e may be represented as the number of signal traces between the first device and the second device.

Taking 4 first-type devices as shown in table 4 as an example, the equivalent line width of the signal wiring between the chip U1 and the chip U2 may be expressed as f1= (w1+w2) xe1+w2, the equivalent line width of the signal wiring between the chip U1 and the connector J1 may be expressed as f2= (w1+w2) xe2+w2, the equivalent line width of the signal wiring between the chip U1 and the connector J2 may be expressed as f3= (w1+w2) xe3+w2, the equivalent line width of the signal wiring between the chip U2 and the connector J1 may be expressed as f4= (w1+w2) xe4+w2, and the equivalent line width of the signal wiring between the chip U2 and the connector J2 may be expressed as f5= (w1+w2) xe5+w2.

Based on the calculated equivalent line width, an equivalent wiring area can be fitted by combining the layout position of the first device and the layout position of the second device, and the area of the equivalent wiring area is calculated to obtain the wiring area between the first device and the second device.

As shown in fig. 3B, the layout position of the first device is (X1, Y1), the layout position of the second device is (X2, Y2), and the equivalent line width of the signal trace between the first device and the second device is F, so that the 4 end points of the equivalent wiring area can be determined, and the coordinates are (X1, Y1-F/2), (X1, y1+f/2), (X2, Y2-F/2), and (X2, y2+f/2), respectively. The quadrangular region defined by the 4 end points is the equivalent wiring region.

The wiring area between the first device and the second device may be obtained by calculating the area of the equivalent wiring area, which may be expressed as sx= (X2-X1) [ (y1+f/2) - (Y2-F/2) ] - (X2-X1) [ (y1+f/2) - (y2+f/2) ]/2- (X2-X1) [ (Y1-F/2) - (Y2-F/2) ]/2.

Based on the calculation formula of the wiring area and table 4, the wiring areas between the chip U1, the chip U2, the connector J1 and the connector J2 can be calculated, specifically, the wiring area between the chip U1 and the chip U2 can be su1_u2, the wiring area between the chip U1 and the connector J1 can be su1_j1, the wiring area between the chip U1 and the connector J2 can be su1_j2, the wiring area between the chip U2 and the connector J1 can be su2_j1, and the wiring area between the chip U2 and the connector J2 can be su2_j2.

Based on the calculated first layout areas and the wiring areas, in combination with tables 3 and 4, the occupation areas S1=Su1+Su of the 4 first-class devices can be obtained by adding 2+sj1+sj2+su1_u2+su1_j1 +su1_j2+su2_j1+su2_j2.

Alternatively, the plurality of devices may include at least one power module, and accordingly, the occupied area of the board to be developed may include the area occupied by the at least one power module.

Before the board to be developed is developed, the configuration information of the power module required to be configured for the board to be developed can be predetermined based on the power demand document, and the configuration information can be pre-stored to a designated position so as to be convenient for calling. Optionally, the power modules may be divided into a single power module and multiple power modules, each of which may be configured with multiple power topologies based on a combination of different electrical parameters.

Optionally, a target power topology to which the power module belongs may be determined based on the electrical parameters of the power module, and a second layout area of the power module may be obtained based on the target power topology to which the power module belongs and the electrical parameters of the power module, so as to obtain the occupied area.

When determining the through hole development process of the board to be developed, the configuration information may be called from the designated location to determine the number of terms and corresponding electrical parameters of each group of power modules, which may be as shown in table 5. In table 5, the board to be developed may include a power module 1 and a power module 2, where the input voltage of the power module 1 is 12V, the output voltage is 3.3V, the input current is 0.2A, the output current is 0.7A, the number of items is 1, the input voltage of the power module 2 is 12V, the output voltage is 0.9V, the input current is 0.9A, the output current is 12A, and the number of items is 7.

TABLE 5

The target power topology of each group of power modules may be determined based on the number of terms and corresponding electrical parameters of each group of power modules. In particular, the combination of different electrical parameters may be expressed as a combination of an input voltage and an output voltage. The target topology set may be determined based on the number of terms of the power supply module, and the target power supply topology may be determined from a plurality of power supply topologies included in the target topology set based on the input voltage and the output voltage of the power supply module.

For example, for the power supply module 1, if the number of terms is 1, it may be determined that the target topology set corresponding to the power supply module 1 is a power supply topology set of a single power supply module, and based on a combination of the input voltage 12V and the output voltage 3.3V, it may be determined that the target power supply topology 1 corresponding to the power supply module 1 is from a plurality of power supply topologies included in the power supply topology set of the single power supply module. Similarly, for the power supply module 2, if the number of terms is 7, the target topology set corresponding to the power supply module 2 may be determined to be a power supply topology set of a plurality of power supply modules, and based on a combination of the input voltage 12V and the output voltage 0.9V, the target power supply topology 2 corresponding to the power supply module 2 may be determined from a plurality of power supply topologies included in the power supply topology set of the plurality of power supply modules.

After determining the target power topology of the power supply module, the second layout area of the power supply module may be calculated based on components included in the target power topology.

As shown in fig. 4A, the power topology of the single power module may include an input current via area, an input inductance, an input capacitance, a power chip, an output inductance, an output capacitance, and an output current via area.

As shown in fig. 4B, the power topology of the multi-power module may include a plurality of branches, and an input inductor of the power topology may receive a current provided from an input current via region and provide the current to the plurality of branches, respectively. Each branch may include an input capacitance, a power chip, an output inductance, an output capacitance, and an output current via region.

As can be seen from fig. 4A and fig. 4B, the occupied area of the power supply topology can be calculated according to the length and width of each component in the power supply topology and the area occupied by the via holes of the input and output areas, so as to obtain the second layout area of the power supply module.

Optionally, the number of input vias and the number of output vias may be obtained based on the input current, the output current, and the via load value, the via area length may be obtained based on the number of input vias and the number of output vias, the equivalent length of the power module may be obtained based on the via area length and the equivalent length of the target power topology, and the second layout area of the power module may be obtained based on the equivalent length of the power module and the equivalent width of the target power topology.

Specifically, for each power topology, information of all devices of the power topology can be obtained in advance based on a schematic diagram of the power topology, and classified to record and obtain second-class device configuration information. Or after determining the target power supply topology, based on the schematic diagram of the target power supply topology, acquiring information of all devices of the target power supply topology, and classifying to record and obtain configuration information of the second type of devices. The classification method of the devices included in the power supply topology is not limited herein, and for example, the definition of PINs connected to both ends of the inductor and the definition of PINs connected to both ends of the capacitor may be searched to classify the plurality of inductors into an input inductor and an output inductor, and classify the plurality of capacitors into an input capacitor and an output capacitor, respectively.

The second type of device may refer to components constituting the power module, including capacitors, inductors, power chips, etc. constituting the power module.

For the input current and the output current included in the electrical parameter, the number of input vias to be set at the input area and the number of output vias to be set at the output area may be determined according to the value of Kong Zailiu per via.

After the number of input through holes, the number of output through holes and the configuration information of the second type of devices included in the target power topology are determined, the equivalent length and the equivalent width of the equivalent occupied area of the power module can be calculated respectively, and the area of the equivalent occupied area of the power module can be expressed as the second layout area of the power module.

When the equivalent length of the power supply module is calculated, the length of the via hole area and the equivalent length of the target power supply topology can be respectively determined, and the equivalent lengths of the via hole area and the target power supply topology are added to obtain the equivalent length of the power supply module.

Alternatively, when the vias are arranged in a single row, the length of the input via area may be obtained based on the number of input vias, and the length of the output via area may be obtained based on the number of output vias. Taking the calculation of the length of the input via region as an example, the length lin1=2×r1×n1+ (n1+2) ×w3 of the input via region, where r1 may be represented as the radius of the via, n1 may be represented as the number of input vias, and w3 may be represented as the pitch between the vias.

Alternatively, when the process is arranged in multiple rows, the length of the input via area and the length of the output via area may be obtained based on a preset number of single-row vias. Taking the calculation of the length of the input via area as an example, the length lin2=2×r1×n2+ (n2+2) ×w3 of the input via area, the n2 may be expressed as a preset number of single-row vias.

The equivalent length of the target power topology can be calculated in the process of determining the board card hole development process of the board card to be developed, or can be calculated in advance, and is not limited herein.

Optionally, no matter the power supply module is a single power supply module or a plurality of power supply modules, the equivalent length of the target power supply topology corresponding to the power supply module is not changed due to the number of items under the condition that the electrical parameters are unchanged. Therefore, the equivalent length of the target power supply topology can be obtained based on the length of the input inductor, the length of the input capacitor, the length of the power supply chip, the length of the output inductor, and the length of the output capacitor included in the target power supply topology.

For example, the equivalent length of the target power supply module may be expressed as equivalent length=input inductance length+first redundancy amount+input capacitance length+second redundancy amount+power supply chip length+third redundancy amount+length of output capacitance+fourth redundancy amount+output inductance length. The first redundancy amount, the second redundancy amount, the third redundancy amount, and the fourth redundancy amount may be expressed as a distance between devices, and the values thereof may be set according to product design experience, or may be set according to actual product requirements, which is not limited herein.

Accordingly, the equivalent length of the power module may be the sum of the length of the input via area, the length of the output via area, and the equivalent length of the target power module.

The power module includes devices that have a width that is generally greater than the width of the via area, and therefore the width of the via area may be ignored in the calculation of the equivalent width. For the multiple power supply modules and the single power supply module, the main difference is that the multiple power supply modules can include multiple branches, so that the equivalent widths of the multiple power supply modules and the single power supply module can be different under the condition of identical electrical parameters.

For example, in the case where the target power supply topology is a single power supply topology, the equivalent width of the target power supply topology may be obtained based on the maximum value of the widths of the respective second-type devices included in the target power supply topology.

Specifically, the maximum width value may be taken from the widths of the plurality of second-type devices included in the target power topology based on the widths of the plurality of second-type devices, and the maximum width value may be added to a preset safe distance value, so that an equivalent width of the target power topology may be obtained.

For another example, in the case that the target power supply topology is a multiple-term power supply topology, the equivalent width of the input capacitor may be obtained based on the number of input capacitors and the width of the input capacitors included in the target power supply topology, the equivalent width of the power supply chip may be obtained based on the number of power supply chips and the width of the power supply chips included in the target power supply topology, the equivalent width of the output inductor may be obtained based on the number of output inductors and the width of the output inductors included in the target power supply topology, the equivalent width of the output capacitor may be obtained based on the number of output capacitors and the width of the output capacitors included in the target power supply topology, and the equivalent width of the target power supply topology may be obtained based on the maximum value among the equivalent width of the input capacitors, the equivalent width of the power supply chips, the equivalent width of the output inductors, and the equivalent width of the output capacitors.

Alternatively, the equivalent width of the input capacitance may be expressed as the product of the number of input capacitances and the width of a single capacitance. Similarly, the equivalent width of the power supply chip may be expressed as a product of the number of power supply chips and the width of the single power supply chip, the equivalent width of the output inductor may be expressed as a product of the number of output inductors and the width of the single output inductor, and the equivalent width of the output capacitor may be expressed as a product of the number of output capacitors and the width of the single output capacitor.

Optionally, when calculating the equivalent width of the input capacitor, the equivalent width of the power chip, the equivalent width of the output inductor, and the equivalent width of the output capacitor, a safe distance value may be added, where the safe distance value may be determined by the number of devices and the safe intervals of the devices, and is not limited herein.

After the equivalent width of the input capacitor, the equivalent width of the power chip, the equivalent width of the output inductor and the equivalent width of the output capacitor are obtained, the 4 values can be compared, and the maximum value thereof is taken as the equivalent width of the target power topology.

The equivalent width of the target power topology can also be used as the equivalent length of the power module. After the equivalent length and the equivalent width of the power supply module are obtained, the equivalent length and the equivalent width can be multiplied to obtain the second layout area of the power supply module. The sum of the second layout areas of the at least one power module may be denoted as S2, for example.

Optionally, the plurality of devices may further include a plurality of third devices, where the third devices may refer to all devices of the plurality of devices except the first device and the second device included in the power module, including various patch devices, in-line devices, and the like, which are not limited herein.

For a patch-type device in the third type of device, the body area of the patch-type device may be taken as the third layout area of the device.

For the direct-insert type device in the third type device, the number of pins of the direct-insert type device and the body area of the direct-insert type device can be combined to obtain the third layout area of the direct-insert type device.

Specifically, the area of the via hole area of the third type device can be determined based on the pin number of the third type device, and the third layout area of the third type device is obtained based on the body area and the area of the via hole area of the third type device, so as to obtain the occupation area of the board card to be developed.

For example, pins of all third-class devices may be counted to obtain a total number n3 of pins, if a radius of a via hole of a pin is r2 and a pitch between via holes of a pin is w4, a sum of areas of all third-class devices may be represented as s3= Σ Sbody +n3×n4× (r2+2×w4) × (r2+2×w4), where S3 may represent a sum of areas of a plurality of third-class devices, Σ Sbody may represent a sum of body areas of all third-class devices, and n4 may represent a number of layer switching times of wirings.

Optionally, based on the types of devices included in the board to be developed, the occupied area of the board to be developed may be calculated based on at least one of the sum S1 of the areas of the plurality of first devices, the sum S2 of the areas of the at least one power module, and the sum S3 of the areas of the plurality of third devices. For example, the occupied area of the board to be developed may be sub=s1+s2+s3, where sub may represent the occupied area of the board to be developed.

Then, the through hole development process of the board to be developed can be determined by comparing the size relationship between the effective area S0 and the occupation area Suse of the board to be developed, which is not described herein.

Or the calculation errors and the influence of the existence of the barriers such as the support posts in the board card on the layout and the wiring layout of the device are considered, the effective area and the occupied area can be weighted respectively, and the board card to be developed is determined to be suitable for adopting a through hole process or a special process such as POFV and the like by comparing the size relation between the weighted effective area and the weighted occupied area. Alternatively, the weight corresponding to the effective area may be a value smaller than 1, so that the weighted effective area may be smaller than the effective area, and the weight corresponding to the occupied area may be a value larger than 1, so that the weighted occupied area may be larger than the occupied area, so that the influence of the obstacle in the board on the device layout and the wiring between the devices may be compensated.

According to the embodiment of the invention, the design requirements of the PCB board card are comprehensively processed through structural design, manufacturing process, signal transmission and the like in various fields, and the scattered requirements with different dimensions are converted into quantifiable and operational parameter information. And then, combining actual environment parameters of the board to be developed, such as the size of the board, the layout planning of the device, the distribution condition of pins and the like, and carrying out comprehensive operation through a preset algorithm. In the calculation process, the effective area of the area which is unavailable for layout and wiring on the board card is comprehensively considered, and the calculation of the layout and wiring area is performed on the basis of the space scale required by wiring under the conventional through hole process and covering key factors such as the occupied space of the through hole, the width of a wiring channel and the like. The calculated effective area may then be compared to the place and route area to determine a via development process for the board. By the scheme, the technology type to be adopted in the development of the PCB board card can be scientifically and reasonably determined, the key technology and cost problems of over-design, cost increase, heavy weight and the like brought by a human sense judging technology are effectively solved, and powerful support is provided for the efficient, low-cost and high-quality development of the board card of the storage product.

As shown in fig. 5, an electronic device 500 according to an embodiment of the present invention includes a processor 501 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 502 or a program loaded from a storage section 508 into a Random Access Memory (RAM) 503. The processor 501 may include, for example, a general purpose microprocessor (e.g., a CPU), an instruction set processor and/or an associated chipset and/or a special purpose microprocessor (e.g., an Application Specific Integrated Circuit (ASIC)), or the like. The processor 501 may also include on-board memory for caching purposes. The processor 501 may comprise a single processing unit or a plurality of processing units for performing different actions of the method flow according to an embodiment of the invention.

In the RAM 503, various programs and data required for the operation of the electronic apparatus 500 are stored. The processor 501, ROM 502, and RAM 503 are connected to each other by a bus 504. The processor 501 performs various operations of the method flow according to an embodiment of the present invention by executing programs in the ROM 502 and/or the RAM 503. Note that the program may be stored in one or more memories other than the ROM 502 and the RAM 503. The processor 501 may also perform various operations of the method flow according to embodiments of the present invention by executing programs stored in the one or more memories.

According to an embodiment of the invention, the electronic device 500 may further comprise an input/output (I/O) interface 505, the input/output (I/O) interface 505 also being connected to the bus 504. The electronic device 500 may also include one or more of an input portion 506 including a keyboard, a mouse, etc., an output portion 507 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc., and a speaker, etc., a storage portion 508 including a hard disk, etc., and a communication portion 509 including a network interface card such as a LAN card, a modem, etc., connected to an input/output (I/O) interface 505. The communication section 509 performs communication processing via a network such as the internet. The drive 510 is also connected to an input/output (I/O) interface 505 as needed. A removable medium 511 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 510 as needed so that a computer program read therefrom is mounted into the storage section 508 as needed.

The present invention also provides a computer-readable storage medium that may be included in the apparatus/device/system described in the above embodiments, or may exist alone without being assembled into the apparatus/device/system. The computer-readable storage medium carries one or more programs which, when executed, implement methods in accordance with embodiments of the present invention.

According to embodiments of the invention, the computer-readable storage medium may be a non-volatile computer-readable storage medium, which may include, for example, but is not limited to, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, according to embodiments of the invention, the computer-readable storage medium may include ROM 502 and/or RAM 503 and/or one or more memories other than ROM 502 and RAM 503 described above.

Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the method shown in the flowcharts. The program code means for causing a computer system to carry out the methods provided by embodiments of the present invention when the computer program product is run on the computer system.

The above-described functions defined in the system/apparatus of the embodiment of the present invention are performed when the computer program is executed by the processor 501. The systems, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the invention.

In one embodiment, the computer program may be based on a tangible storage medium such as an optical storage device, a magnetic storage device, or the like. In another embodiment, the computer program may also be transmitted, distributed, and downloaded and installed in the form of a signal on a network medium, and/or installed from a removable medium 511 via the communication portion 509. The computer program may comprise program code that is transmitted using any appropriate network medium, including but not limited to wireless, wireline, etc., or any suitable combination of the preceding.

In such an embodiment, the computer program may be downloaded and installed from a network via the communication portion 509, and/or installed from the removable media 511. The above-described functions defined in the system of the embodiment of the present invention are performed when the computer program is executed by the processor 501. The systems, devices, apparatus, modules, units, etc. described above may be implemented by computer program modules according to embodiments of the invention.

According to embodiments of the present invention, program code for carrying out computer programs provided by embodiments of the present invention may be written in any combination of one or more programming languages, and in particular, such computer programs may be implemented in high-level procedural and/or object-oriented programming languages, and/or in assembly/machine languages. Programming languages include, but are not limited to, such as Java, c++, python, "C" or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Those skilled in the art will appreciate that the features recited in the various embodiments of the invention can be combined and/or combined in a variety of ways, even if such combinations or combinations are not explicitly recited in the present invention. In particular, the features recited in the various embodiments of the invention can be combined and/or combined in various ways without departing from the spirit and teachings of the invention. All such combinations and/or combinations fall within the scope of the invention.

The embodiments of the present invention are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. The method for determining the board through hole development process is characterized by comprising the following steps of:

Determining an effective area of a board card to be developed based on the shape of the board card to be developed, wherein the effective area comprises a board card structure file of the board card to be developed, a plurality of shape elements, at least one first target shape element and at least one second target shape element from the plurality of shape elements based on the type of the shape elements and a board diagram level where the shape elements are positioned, and the effective area of the board card to be developed based on the area of the at least one first target shape element and the area of the at least one second target shape element;

determining an area occupied by body layout of a plurality of devices and an area occupied by wiring among the devices in a through hole process state based on layout information of the plurality of devices related to the board card to be developed to obtain an occupied area of the board card to be developed, and

And determining a through hole development process of the board card to be developed based on the effective area and the occupied area.

2. The method of claim 1, wherein the plurality of devices comprises a plurality of first-type devices;

The determining, based on layout information of a plurality of devices related to the board to be developed, an area occupied by body layout of the plurality of devices and an area occupied by wiring between the plurality of devices in a state of a through hole process, to obtain an occupied area of the board to be developed includes:

Analyzing the board layout file of the board to be developed to determine the connection topology and the respective layout positions of a plurality of first-class devices;

determining a first layout area of the plurality of first type devices based on the connection topology;

determining a wiring area between a plurality of devices of the first type based on the connection topology and the layout positions of the plurality of devices of the first type, and

And obtaining the occupied area based on the first layout area and the wiring area.

3. The method of claim 2, wherein the determining a first layout area of the plurality of first type devices based on the connection topology comprises:

Determining the number of outgoing lines of the first type device based on the connection topology;

determining the outgoing line area of the first type device based on the outgoing line number of the first type device and the outgoing line type of the first type device, and

And obtaining the first layout area based on the outgoing area and the body area of the first type device.

4. The method of claim 2, wherein the determining a routing area between the plurality of first-type devices based on the connection topology and the respective placement locations of the plurality of first-type devices comprises:

for a first device and a second device of the plurality of devices of the first type, determining a number of signal traces between the first device and the second device based on a connection topology between the first device and the second device;

determining an equivalent wiring area based on the layout position of the first device, the layout position of the second device, the number of signal traces and a preset signal line width, and

And obtaining the wiring area between the first device and the second device based on the area of the equivalent wiring area.

5. The method of claim 1, wherein a plurality of the devices comprise at least one power module;

determining a target power topology to which the power module belongs based on the electrical parameters of the power module, and

And obtaining a second layout area of the power supply module based on the target power supply topology to which the power supply module belongs and the electrical parameters of the power supply module, wherein the occupied area of the board card to be developed comprises the second layout area of the power supply module.

6. The method of claim 5, wherein the electrical parameters include an input voltage and an output voltage;

wherein, based on the electrical parameter of the power module, determining the target power topology to which the power module belongs includes:

determining a target topology set based on the number of terms of the power module, and

The target power topology is determined from a plurality of power topologies included in the target topology set based on the input voltage and the output voltage of the power module.

7. The method of claim 5, wherein the electrical parameters further comprise an input current and an output current;

the obtaining the second layout area of the power supply module based on the target power supply topology to which the power supply module belongs and the electrical parameters of the power supply module includes:

Obtaining the number of input through holes and the number of output through holes based on the input current, the output current and the through hole current carrying value;

obtaining the length of a via area based on the number of the input vias and the number of the output vias;

Obtaining the equivalent length of the power supply module based on the length of the via hole area and the equivalent length of the target power supply topology, and

And obtaining a second layout area of the power supply module based on the equivalent length of the power supply module and the equivalent width of the target power supply topology.

8. The method of claim 7, wherein the method further comprises:

and obtaining the equivalent length of the target power supply topology based on the length of the input inductor, the length of the input capacitor, the length of the power supply chip, the length of the output inductor and the length of the output capacitor included in the target power supply topology.

9. The method of claim 7, wherein the method further comprises:

And under the condition that the target power supply topology is a single-phase power supply topology, obtaining the equivalent width of the target power supply topology based on the maximum value of the widths of the second type devices included in the target power supply topology.

10. The method of claim 7, wherein the method further comprises:

Under the condition that the target power supply topology is a plurality of power supply topologies, obtaining the equivalent width of the input capacitor based on the number of the input capacitors included in the target power supply topology and the width of the input capacitors;

Obtaining the equivalent width of the power supply chips based on the number of the power supply chips included in the target power supply topology and the width of the power supply chips;

obtaining the equivalent width of the output inductor based on the number of the output inductors included in the target power supply topology and the width of the output inductor;

obtaining the equivalent width of the output capacitor based on the number of the output capacitors and the width of the output capacitors included in the target power supply topology, and

And obtaining the equivalent width of the target power supply topology based on the maximum value of the equivalent width of the input capacitor, the equivalent width of the power supply chip, the equivalent width of the output inductor and the equivalent width of the output capacitor.

11. The method of claim 1, wherein the plurality of devices comprises a third plurality of devices;

Determining the area of the via area of the third type device based on the pin number of the third type device, and

And obtaining a third layout area of the third type device based on the volume area of the third type device and the area of the via hole area, wherein the occupied area of the board card to be developed comprises the third layout area of the third type device.

12. The method of claim 1, wherein determining at least one first target shape element and at least one second target shape element from a plurality of the shape elements based on a type of the shape element and a level of a board graph at which the shape element is located, comprises:

Determining the shape element as the first target shape element under the condition that the type of the shape element is a circuit board geometric shape and the board diagram level where the shape element is positioned is a frame layer;

determining the shape element as the second target shape element when the type of the shape element is a circuit board geometry and the board layer level at which the shape element is located is a cut-away layer;

in the case that the type of the shape element is a wire-forbidden area and the board diagram level where the shape element is located is the first surface layer or the second surface layer of the board to be developed, determining the shape element as the second target shape element, and

And determining the shape element as the second target shape element under the condition that the type of the shape element is a limited layout area, the board diagram level where the shape element is positioned is the first surface layer, and the component height threshold value of the shape element is smaller than a preset value.

13. The method of claim 1, wherein the determining the effective area of the board to be developed based on the area of the first target shape element and the area of the at least one second target shape element comprises:

obtaining an inactive area based on a sum of areas of the at least one second target shape element, and

And subtracting the area of the invalid area from the sum of the areas of the at least one first target shape element to obtain the effective area of the board card to be developed.

14. An electronic device, comprising:

One or more processors;

a memory for storing one or more computer programs,

Characterized in that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1-13.