CN1206731C - Electrostatic discharge circuit suitable to bearing high roltage in high frequeny and analogue - Google Patents
Electrostatic discharge circuit suitable to bearing high roltage in high frequeny and analogue Download PDFInfo
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- CN1206731C CN1206731C CN 02105009 CN02105009A CN1206731C CN 1206731 C CN1206731 C CN 1206731C CN 02105009 CN02105009 CN 02105009 CN 02105009 A CN02105009 A CN 02105009A CN 1206731 C CN1206731 C CN 1206731C
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- pass transistor
- nmos pass
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Abstract
The present invention is suitable for electrostatic discharge circuits with high frequency and comprises a diode and stacked NMOS transistors which are connected in series between a pin pad and a voltage source or between the pin pad and the ground. The small capacitance of the diode is utilized to effectively reduce the capacitance of the pin pad, and the stacked NMOS transistors are utilized to make the pin pad can bear high voltage.
Description
Technical field
The present invention relates to be applied to deep-sub-micrometer CMOS manufacture process electrostatic discharge circuit, particularly relate to and be applied to high frequency and analog circuit bears high-tension electrostatic discharge circuit.
Background technology
The increase day by day of radio frequency (radio frequency) circuit and high speed analog transceiver (tranceiver), the ESD circuit of therefore low electric capacity are also just more and more important.The simulation pin of existing low electric capacity is to adopt the reverse bias diode; be respectively coupled between weld pad and voltage source, weld pad and the ground connection; a kind of electrostatic discharge protection method that is proposed as Ming-Dou ker; referring to " ESDprotection design on analog pin with very low input capacitancefor high frequency or current mode applications "; IEEE Journalof solid state circuit, Aug 2000.On the other hand, bearing high-tension digital pin is the mode that adopts suspension joint N-type well, yet existing simulation pin can't bear high voltage, and the electric capacity of suspension joint N-type well digital simulation pin is too big again, is not suitable for high-frequency operation.
Summary of the invention
Technical problem to be solved by this invention provides a kind of that be applicable to high frequency and simulation and can bear high-tension ESD protection circuit.
To achieve these goals, the present invention proposes a kind of electrostatic discharge circuit that is applicable to high frequency, it comprises: first diode, and its anode is couple to a weld pad; Second diode, its anode is couple to a low-voltage source, and negative electrode is couple to weld pad; First nmos pass transistor, its drain electrode is couple to the negative electrode of first diode, and grid leak is couple to a high voltage source; Second nmos pass transistor, its drain electrode is couple to the source electrode of first nmos pass transistor, and source electrode is couple to high voltage source; The 3rd nmos pass transistor, its drain electrode is couple to the grid of second nmos pass transistor, and source electrode is couple to low-voltage source; One resistance is coupled between the grid of high voltage source and the 3rd nmos pass transistor; One electric capacity is coupled between the grid of low-voltage source and the 3rd nmos pass transistor; The 4th nmos pass transistor, its drain electrode is couple to the negative electrode of first diode, and grid leak is couple to high voltage source; The 5th nmos pass transistor, its drain electrode is couple to the source electrode of the 4th nmos pass transistor, and source electrode is couple to low-voltage source, and grid is couple to the grid of the 3rd nmos pass transistor.
Further specify specific embodiments of the invention below in conjunction with accompanying drawing.
Description of drawings
Fig. 1 is the high-frequency electrostatic discharge protection circuit of first embodiment of the invention;
Fig. 2 is the high-frequency electrostatic discharge protection circuit of second embodiment of the invention;
Fig. 3 is the high-frequency electrostatic discharge protection circuit of third embodiment of the invention;
Fig. 4 is existing simulation pin and the HVT measurement result at HBM and MM level (level);
Fig. 5 is a capacitance of representing existing simulation pin and HVT when 1MHz.
Embodiment
First embodiment
Fig. 1 represents the high-frequency electrostatic discharge protection circuit of first embodiment of the invention; it is used to bear clamp circuit 10 (the high voltage tolerant power to VCC clamp of high voltage to voltage source; hereinafter referred to as HVTP2V 10), it comprises diode D2, nmos pass transistor Mn1, nmos pass transistor Mn2, nmos pass transistor MnO, resistance R 1, capacitor C 1.Diode D1 anode is coupled to low-voltage source VSS, and the negative electrode of diode D1 is coupled to weld pad PAD.The anode of diode D2 is coupled to weld pad PAD, and the negative electrode of diode D2 then is coupled to the drain electrode of nmos pass transistor Mn1.The grid of nmos pass transistor Mn1 is couple to high voltage source VDD, and the source electrode of nmos pass transistor Mn1 is couple to the drain electrode of nmos pass transistor Mn2.The grid of nmos pass transistor Mn2 is the mode ground connection with dynamic suspension joint grid (dynamic-floating-gate), in order to help to trigger the parasitic BJT of nmos pass transistor Mn2, make its even conducting, it is couple to the drain electrode of nmos pass transistor Mn0, and the source electrode of nmos pass transistor Mn2 is couple to high voltage source VDD.Nmos pass transistor Mn0, resistance R 1, capacitor C 1 constitute dynamic suspension joint grid circuit.The source electrode of nmos pass transistor Mn0 is couple to low-voltage source VSS.Resistance R 1 is coupled between the grid of high voltage source VDD and nmos pass transistor Mn0, and capacitor C 1 is coupled between the grid and low-voltage source VSS of nmos pass transistor Mn0.
The effective capacitance of HVTP2V 10 between weld pad PAD and high voltage source VDD is that it comprises Cgd-Mn1, Cgb-Mn1 and other parasitic capacitance by the electric capacity of the junction capacitance of diode D2 and nmos pass transistor Mn2 and nmos pass transistor Mn1 storehouse (stack).Electric capacity in the electric capacity of diode D2 much smaller than nmos pass transistor Mn1 again, so effective capacitance almost is the junction capacitance that equals diode D2, it is expressed as follows:
C
pad-VCC＝Cj
D2//C
Mn1-Mn2≈Cj
D2
Nmos pass transistor Mn2 and nmos pass transistor Mn1 storehouse can increase the ESD voltage that HVTP2V 10 can bear, and prevent that nmos pass transistor Mn1 from bearing the overvoltage of ESD (over-stress).HVTP2V 10 acts on PD-pattern and ND one pattern, adds the conducting voltage (cut in) of diode D2 above 6.8V when the voltage difference of weld pad PAD and high voltage source VDD.Diode D1 acts on the NS-pattern.Diode D1 also can with HVTP2V 10 1 react on the forward pin to pin (positive pin-to-pin) pattern and negative sense pin to pin (negativepin-to-pin) pattern, it does the time spent, forward conducting of diode D1, and nmos pass transistor Mn1, the Mn2 of storehouse collapse (breakdown) conducting by parasitic BJT.
Second embodiment
Fig. 2 is the high-frequency electrostatic discharge protection circuit of second embodiment of the invention.It is used to bear clamp circuit 20 (the high voltage tolerant power to GND clamp of high voltage to ground connection, below replace with HVTP2G 20), it comprises diode D2, nmos pass transistor Mn3, nmos pass transistor Mn4, nmos pass transistor Mn0, resistance R 1, capacitor C 1.Diode D1 anode is coupled to low-voltage source VSS, and the negative electrode of diode D2 is coupled to weld pad PAD.The anode of diode D2 is coupled to weld pad PAD, and the negative electrode of diode D2 then is coupled to the drain electrode of nmos pass transistor Mn3.The grid of nmos pass transistor Mn3 is couple to high voltage source VDD, and the source electrode of nmos pass transistor Mn3 is couple to the drain electrode of nmos pass transistor Mn4.The grid of nmos pass transistor Mn4 is the mode ground connection with dynamic suspension joint grid (dynamic-floating-gate), in order to help to trigger the parasitic BJT of nmos pass transistor Mn2, make its even conducting, it is couple to the drain electrode of nmos pass transistor Mn0, and the source electrode of nmos pass transistor Mn4 is couple to ground connection GND.Nmos pass transistor Mn0, resistance R 1, capacitor C 1 constitute dynamic suspension joint grid circuit.The source electrode of nmos pass transistor Mn0 is couple to low-voltage source VSS.Resistance R 1 is coupled between the grid of high voltage source VDD and nmos pass transistor Mn0, and capacitor C 1 is coupled between the grid and low-voltage source VSS of nmos pass transistor Mn0.
The effective capacitance of HVTP2V 10 between weld pad PAD and ground connection GND is that it comprises Cgd-Mn3, Cgb-Mn3 and other parasitic capacitance by the electric capacity of the junction capacitance of diode D2 and nmos pass transistor Mn3 and nmos pass transistor Mn4 storehouse (stack).Electric capacity in the electric capacity of diode D2 much smaller than nmos pass transistor Mn3 again, so effective capacitance almost is the junction capacitance that equals diode D2, it is expressed as follows:
C
pad-GND＝Cj
D2//C
Mn3-Mn4≈Cj
D2
Nmos pass transistor Mn3 and nmos pass transistor Mn4 storehouse can increase the ESD voltage that HVTP2G 20 can bear, and prevent that nmos pass transistor Mn3 from bearing the overvoltage of ESD (over-stress).HVTP2G 20 only acts on the PS-pattern, and action condition is that GND is couple to 0 volt, and weld pad PAD attacks voltage (positive zapping) difference with respect to the forward of ground connection GND and surpasses conducting voltage (cut in) 0.4V that 6.8V adds diode D2.Forward conducting of diode D1, and nmos pass transistor Mn3, the Mn4 of storehouse collapse (breakdown) conducting by parasitic BJT.If there is not HVTP2G 20, the PS-model electric current is through HVTP2V 10 and ESD power clamp, and it needs 6.8V and 6V conducting respectively, the trigger voltage of 12.8V just, and the grid oxic horizon that surpasses 40A ° can bear.
The 3rd embodiment
Fig. 3 represents the high-frequency electrostatic discharge protection circuit of third embodiment of the invention.It has concurrently and bears high voltage to the clamp circuit HVTP2V 10 of voltage source with bear the clamp circuit HVTP2G 20 of high voltage to ground connection, just HVTP2V 10 and HVTP2G 20 merged and draw and bear high voltage HVT40 circuit, share diode D2, can save the area of diode D2, reduce the capacitive load of weld pad PAD, an one benefit is to share dynamic suspension joint grid (dynamic-floating-gate) circuit, so resistance R 1, capacitor C 1, nmos pass transistor Mn0 also can share, save area.
As shown in Figure 3, it comprises diode D2, D1, nmos pass transistor Mn1, nmos pass transistor Mn2, nmos pass transistor Mn3, nmos pass transistor Mn4, nmos pass transistor Mn0, resistance R 1, capacitor C 1.Diode D1 anode is coupled to low-voltage source VSS, and the negative electrode of diode D2 is coupled to weld pad PAD.The anode of diode D2 is coupled to weld pad PAD, and the negative electrode of diode D2 then is coupled to the drain electrode of nmos pass transistor Mn1.The grid of nmos pass transistor Mn1 is couple to high voltage source VDD, and the source electrode of nmos pass transistor Mn1 is couple to the drain electrode of nmos pass transistor Mn2.The grid of nmos pass transistor Mn2 is couple to the drain electrode of nmos pass transistor Mn0, and the source electrode of nmos pass transistor Mn2 is couple to voltage source V DD.
The drain electrode of nmos pass transistor Mn3 is coupled to the negative electrode of diode D2, and the grid of nmos pass transistor Mn3 is couple to high voltage source VDD, and the source electrode of nmos pass transistor Mn3 is couple to the drain electrode of nmos pass transistor Mn4.The grid of nmos pass transistor Mn4 is couple to capacitor C 1, and the source electrode of nmos pass transistor Mn4 is couple to ground connection GND.
Similar with first embodiment, second embodiment, HVT 40 weld pad PAD and high voltage source VDD or and ground connection GND between effective capacitance be respectively electric capacity by electric capacity, nmos pass transistor Mn3 and the nmos pass transistor Mn4 storehouse (stack) of junction capacitance, nmos pass transistor Mn1 and the nmos pass transistor Mn2 storehouse (stack) of diode D2, again at the electric capacity of diode D2 electric capacity much smaller than nmos pass transistor Mn1, Mn3, so effective capacitance almost is the junction capacitance that equals diode D2, it is expressed as follows:
C
pad-GND＝C
pad-GND≈Cj
D2
Because HVT 40 merges HVTP2V 10, HVTP2G 20, and comprises diode D1, so can act in PD-pattern, ND-pattern, NS-pattern, PS-pattern.
At the HVT 40 of present embodiment is to form with 0.18um, single polymerization (single poly), the manufacturing of 4 layers of metal TSMC CMOS technology, and wherein, the NMOS channel width of HVTP2V 10 and HVTP2G 20, channel length are respectively 330um, 0.4um.The turn-on condition of the parasitic BJT of HVTP2V 10 and HVTP2G 20 be voltage difference greater than 6.8V, trigger current be 3A at 12V, it can be used for predicting that the HBM level is near 6KV.Fig. 4 represents existing simulation pin and the HVT measurement result at HBM and MM level; it comprises the electrostatic protection ESD pattern of 6 kinds of simulation pins; comprise: PS-pattern, PD-pattern, NS-pattern, ND-pattern, forward pin to pin (positive pin-to-pin) pattern, negative sense pin to pin (negative pin-to-pin) pattern; by JEDEC HBM 6KV and JEDEC MM 550v, be that 10um/0.18um, drain/source all are 15um in NMOS, the size of 40A ° of grid oxic horizon.
For reducing the junction capacitance of diode D1, D2, diode D1, D2 are respectively N-type well/P-type base, P+/N-type well.The capacitance of N-type/P-type based diode is 1/3rd of a N+/P-type well diode.P+/N-type well diode can reduce a large amount of drain electrode-grids (drain-gate) MOS diode capacitance and grid (gated) diode, and its area and girth are respectively 40um2 and 50um.
The capacitance of representing existing simulation pin and HVT when Fig. 5 is illustrated in 1MHz, measure with HP4284, curve A is represented HVT simulation pin, curve B is represented existing simulation pin, curve C is represented HVT numeral pin, the electric capacity of HVT simulation pin has only 250fF, and therefore the capacitance 3pF much smaller than HVT numeral pin can be applied in analog IC, RFIC.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, according to spirit of the present invention and design; easily carry out corresponding change and retouching, so protection scope of the present invention is when being as the criterion with claims content required for protection.
Claims (3)
1. high-frequency electrostatic discharge circuit is characterized in that comprising:
First diode, its anode is couple to a weld pad;
First nmos pass transistor, its drain electrode is couple to the negative electrode of first diode, and grid is couple to a high voltage source;
Second nmos pass transistor, its drain electrode is couple to the source electrode of first nmos pass transistor, and source electrode is couple to above-mentioned high voltage source;
The 3rd nmos pass transistor, its drain electrode is couple to the grid of second nmos pass transistor, and source electrode is couple to a low-voltage source;
One resistance is coupled between the grid of described high voltage source and the 3rd nmos pass transistor;
One electric capacity is coupled between the grid of described low-voltage source and the 3rd nmos pass transistor; And
Second diode, its anode is couple to above-mentioned low-voltage source, and negative electrode is couple to above-mentioned weld pad.
2. high-frequency electrostatic discharge circuit is characterized in that comprising:
First diode, its anode is couple to a weld pad;
First nmos pass transistor, its drain electrode is couple to the negative electrode of first diode, and grid is couple to a high voltage source;
Second nmos pass transistor, its drain electrode is couple to the source electrode of first nmos pass transistor, and source electrode is couple to a low-voltage source;
The 3rd nmos pass transistor, its drain electrode is couple to the grid of second nmos pass transistor, and source electrode is couple to described low-voltage source;
One resistance is coupled between the grid of described high voltage source and the 3rd nmos pass transistor;
One electric capacity is coupled between the grid of described low-voltage source and the 3rd nmos pass transistor; And
Second diode, its anode is couple to above-mentioned low-voltage source, and negative electrode is couple to above-mentioned weld pad.
3. electrostatic discharge circuit that is applicable to high frequency is characterized in that comprising:
First diode, its anode is couple to a weld pad;
Second diode, its anode is couple to a low-voltage source, and negative electrode is couple to a weld pad;
First nmos pass transistor, its drain electrode is couple to the negative electrode of first diode, and grid is couple to a high voltage source;
Second nmos pass transistor, its drain electrode is couple to the source electrode of first nmos pass transistor, and source electrode is couple to described high voltage source;
The 3rd nmos pass transistor, its drain electrode is couple to the grid of second nmos pass transistor, and source electrode is couple to described low-voltage source;
One resistance is coupled between the grid of above-mentioned high voltage source and the 3rd nmos pass transistor;
One electric capacity is coupled between the grid of above-mentioned low-voltage source and the 3rd nmos pass transistor;
The 4th nmos pass transistor, its drain electrode is couple to the negative electrode of first diode, and grid is couple to described high voltage source; And
The 5th nmos pass transistor, its drain electrode is couple to the source electrode of the 4th nmos pass transistor, and source electrode is couple to described low-voltage source, and grid is couple to the grid of the 3rd nmos pass transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105009 CN1206731C (en) | 2002-02-10 | 2002-02-10 | Electrostatic discharge circuit suitable to bearing high roltage in high frequeny and analogue |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105009 CN1206731C (en) | 2002-02-10 | 2002-02-10 | Electrostatic discharge circuit suitable to bearing high roltage in high frequeny and analogue |
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| Publication Number | Publication Date |
|---|---|
| CN1438704A CN1438704A (en) | 2003-08-27 |
| CN1206731C true CN1206731C (en) | 2005-06-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02105009 Expired - Lifetime CN1206731C (en) | 2002-02-10 | 2002-02-10 | Electrostatic discharge circuit suitable to bearing high roltage in high frequeny and analogue |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567557A (en) * | 2009-05-27 | 2009-10-28 | 上海宏力半导体制造有限公司 | Power clamping static protection circuit |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4484564B2 (en) * | 2003-09-19 | 2010-06-16 | シャープ株式会社 | Electrostatic protection circuit and high-frequency circuit device including the same |
| CN100339988C (en) * | 2004-02-26 | 2007-09-26 | 威盛电子股份有限公司 | Electrostatic discharge protection circuit with repeated structure |
| CN101854058A (en) * | 2009-04-01 | 2010-10-06 | 苏州芯美微电子科技有限公司 | Static protection circuit with working voltage higher than VDD and application thereof |
| US10734806B2 (en) | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
| US10861845B2 (en) | 2016-12-06 | 2020-12-08 | Analog Devices, Inc. | Active interface resistance modulation switch |
| US11387648B2 (en) | 2019-01-10 | 2022-07-12 | Analog Devices International Unlimited Company | Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces |
-
2002
- 2002-02-10 CN CN 02105009 patent/CN1206731C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567557A (en) * | 2009-05-27 | 2009-10-28 | 上海宏力半导体制造有限公司 | Power clamping static protection circuit |
| CN101567557B (en) * | 2009-05-27 | 2013-09-04 | 上海宏力半导体制造有限公司 | Power clamping static protection circuit |
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| Publication number | Publication date |
|---|---|
| CN1438704A (en) | 2003-08-27 |
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