CN120675840A

CN120675840A - Signal processing system and method based on LPTI controller

Info

Publication number: CN120675840A
Application number: CN202510950734.4A
Authority: CN
Inventors: 李锦成; 党光跃; 陈志列
Original assignee: Shenzhen Yiyike Data Equipment Technology Co ltd
Current assignee: Shenzhen Yiyike Data Equipment Technology Co ltd
Priority date: 2025-07-09
Filing date: 2025-07-09
Publication date: 2025-09-19

Abstract

The present application provides a signal processing system and method based on an LPTI controller. The system includes: an LPTI controller including: a channel controller, a link manager, a transmitting channel, and a receiving channel; wherein the channel controller is connected to the link manager, and the transmitting channel and the receiving channel are connected; the link manager is connected to the channel controller, and the transmitting channel and the receiving channel are connected; the transmitting channel includes: a frame generator, an encoder, a transmitting buffer, and a transmitting low-voltage differential signaling parallel-to-serial controller connected in sequence, and the frame generator is connected to the channel controller; the frame generator is connected to the link manager; the receiving channel includes: a frame parser, a decoder, a word alignment module, a receiving buffer, and a receiving low-voltage differential signaling serial-to-parallel controller connected in sequence, and the frame parser is connected to the channel controller; the frame parser is connected to the link manager; the link manager also includes a link manager state machine, which is used to train the controller for signal transmission and reception.

Description

Signal processing system and method based on LPTI controller

Technical Field

The application belongs to the technical field of computers, and particularly relates to a signal processing system and method based on LPTI controllers.

Background

DC-SCM (DATA CENTER-ready Secure Control Module, data center ready security control module) is an important specification of open computing project (Open Compute Project, OCP) hardware management subprojects, version 2.0 of DC-SCM reconstructs the server management architecture through modular design, which has a great impact on the design and management of servers. The OCP DC-SCM specification defines LPTI (Low PIN TEST INTERFACE, low pin count test interface) channel protocol interface specification, which is used for communication between interfaces such as GPIO (General-Purpose Input/Output interface), I2C (Inter-INTEGRATED CIRCUIT, internal integrated circuit), UART (Universal Asynchronous Receiver/Transmitter ) and the like in SCM (Secure Control Module, security control module) cards and motherboards.

However, how to design LPTI control based on CPLD (Complex Programmable Logic Device ) is a problem that each large server and SCM card designer must face.

Disclosure of Invention

The embodiment of the application provides a signal processing system and a signal processing method based on LPTI controllers, which can realize LPTI control.

In a first aspect, an embodiment of the present application provides a signal processing system based on LPTI a controller, where the LPTI controller includes a channel controller, a link manager, a transmit channel, and a receive channel, where the channel controller is connected to the link manager, the transmit channel, and the receive channel;

The link manager is connected with the channel controller and the receiving channel;

The transmitting channel comprises a frame generator, an encoder, a transmitting buffer memory and a transmitting low-voltage differential signal parallel-serial controller which are sequentially connected, wherein the frame generator is connected with the channel controller;

the receiving channel comprises a frame analyzer, a decoder, a word alignment module, a receiving buffer and a receiving low-voltage differential signal serial-parallel controller which are sequentially connected, wherein the frame analyzer is connected with the channel controller;

the link manager also includes a link manager state machine, which is used for training the LPTI controller to send and receive signals.

In one embodiment, the link management state machine of the link manager comprises a link training main state, a link configuration main state and a link operation main state, wherein the link training main state is used for detecting signals of a link and setting signal transmission speeds of the link, the link configuration main state is used for aligning signals of the link, and the link operation main state is used for operating the LPTI controller according to the signal transmission speeds set by the link training main state and data parameters aligned by the link configuration main state.

In one implementation mode, the link training main state comprises a link detection sub-state, a link speed sub-state and a link training completion sub-state, wherein the link detection sub-state is used for receiving and transmitting a link detection type data frame, the link speed sub-state is used for receiving and transmitting a link speed type data frame, and the link training completion sub-state is used for determining a configuration frequency interval of a safety control module.

In one implementation mode, the link configuration main state comprises an idle sub-state, a link notification alignment sub-state, a link notification sub-state, a link configuration sub-state, a link receiving sub-state and a link configuration completion sub-state, wherein the idle sub-state is used for configuring the speed of the transmitting channel and the speed of the receiving channel to be the maximum frequency corresponding to the frequency interval and reconfiguring the frequency of a clock enabling signal, the link notification alignment sub-state is used for receiving and transmitting a link notification type data frame, the link notification sub-state is used for forwarding a data frame of a configuration type of a serial management module to a host processor module and transmitting low-speed interface information of the serial management module to the host processor module, the link configuration sub-state is used for transmitting a data frame of the configuration type, the link receiving sub-state is used for forwarding a received data frame transmitted by the host processor module to the serial management module, and the link configuration completion sub-state is used for entering the link operation main state.

In a second aspect, an embodiment of the present application provides a signal processing method based on LPTI controllers, which is applied to a signal processing system based on LPTI controllers provided in any embodiment of the present application, where the method includes:

under the starting state of a link management state machine of the link manager, configuring a system clock as a fixed frequency, and configuring a serial clock, a receiving clock and a transmitting clock as non-fixed frequencies;

And in the starting state of the link management state machine, determining enabling signals of the link manager to a system clock, a serial clock, a receiving clock and a transmitting clock according to the main state of the link management state machine, wherein the enabling signals are used for enabling the system clock, the serial clock, the receiving clock and the transmitting clock to be matched with the main state of the link management state machine.

In one embodiment, the link management state machine comprises a link training master state, a link configuration master state and a link running master state, and the method further comprises:

In the link training main state, detecting a signal of a link and setting a signal transmission speed of the link;

In the link configuration main state, aligning the signals of the link;

And operating the LPTI controller in the link operation main state according to the signal transmission speed set by the link training main state and the data parameters aligned by the link configuration main state.

In one embodiment, in the link training master state, detecting a signal of a link and setting a signal transmission speed of the link includes:

In a link detection sub-state of the link training main state, the link manager outputs a link detection signal to be effective, sends a first encapsulation notification to the frame generator and sends a first detection notification to the frame parser, wherein the first encapsulation notification is used for notifying the frame generator that the encapsulated data frame type is a link detection type, and the detection notification is used for notifying the frame parser that the detected data frame type is a link detection;

in a link speed sub-state of the link training main state, the link manager outputs a link speed signal to be effective, sends a second encapsulation notification to the frame generator, and sends a second detection notification to the frame parser, wherein the second encapsulation notification is used for notifying the frame generator that the encapsulated data frame type is the link speed, and the second detection notification is used for notifying the frame parser that the detected data frame type is the link speed;

And in a link training completion sub-state of the link training main state, the link manager determines a configuration frequency interval of the safety control module by comparing the local link speed capability with the remote link speed capability, wherein the configuration frequency interval is a frequency interval of the safety control module for receiving and/or transmitting data.

In one embodiment, the configuring the master state in the link to align signals of the link includes:

in an idle sub-state of the link configuration main state, configuring the rate of the transmitting channel and the rate of the receiving channel to be the maximum frequency corresponding to the frequency interval, and reconfiguring the frequency of a clock enabling signal;

In a link notification alignment sub-state of the link configuration main state, sending a third encapsulation notification to the frame parser and sending a third detection notification to the frame parser, wherein the third encapsulation notification is used for notifying the frame generator that the encapsulated data frame type is a link notification, and the third detection notification is used for detecting the frame parser that the data frame type is a link notification;

Forwarding a data frame of a configuration type of the serial management module to the host processor module in a link notification sub-state of the link configuration main state, and sending low-speed interface information of the serial management module to the host processor module;

in the link receiving sub-state of the link configuration main state, forwarding a received data frame sent by the host processor module to the serial management module;

and after the link configuration of the link configuration main state is completed in the sub-state, entering a link operation main state.

In a third aspect, an embodiment of the application provides an electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing a method as provided in any one of the embodiments of the application when the computer program is executed.

According to a further aspect of the present application there is provided a computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the method provided by the related embodiments of the first aspect described above.

The system provided by the embodiment of the application can realize communication between a plurality of interfaces and the main board and realize LPTI control based on complex logic devices.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a link manager according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a link training master state according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a link configuration master state according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a frame generator state machine according to one embodiment of the application;

FIG. 6 is a schematic diagram of a clock signal according to an embodiment of the application;

FIG. 7 is a schematic diagram of the interface of a TX FIFO according to an embodiment of the present application;

FIG. 8 is a schematic diagram of the interface of an RX FIFO according to one embodiment of the present application;

FIG. 9 is a functional block diagram of a word alignment module according to one embodiment of the present application;

FIG. 10 is a functional schematic of a word alignment module according to an embodiment of the present application;

FIG. 11 is Low Latency GPIO Channel functions of an embodiment of the present application;

FIG. 12 is a Normal Latency GPIO Channel functional reference diagram of one embodiment of the present application;

FIG. 13 is a schematic diagram of UART Channel functionality according to an embodiment of the present application;

FIG. 14 is a schematic functional diagram DATA CHANNEL of one embodiment of the present application;

FIG. 15 is a schematic diagram of a method according to an embodiment of the application;

fig. 16 is a schematic diagram of an electronic device according to an embodiment of the application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The following description of the embodiments of the present application is given by way of example with reference to the accompanying drawings.

Fig. 1 shows a signal processing system based on a LPTI controller In an embodiment of the present application, where the LPTI controller includes a channel controller (Channel Controller), a link manager (LINK MANAGER), a transmitting channel and a receiving channel, where the channel controller connects the link manager, the transmitting channel and the receiving channel, the link manager connects the channel controller, the transmitting channel and the receiving channel, the transmitting channel includes a Frame Generator (Frame Generator), an encoder, a transmitting buffer (TX FIFO, transmit First-In-First-Out) and a transmitting Low Voltage Differential Signaling (LVDS) parallel-serial controller sequentially connected, the Frame Generator connects the channel controller, the Frame Generator connects the link manager, the receiving channel includes a Frame parser (FRAME PARSER), a decoder, a word alignment module (word aligner), a receiving buffer (RX FIFO, receive First-In-First-Out) and a receiving Low Voltage differential signaling parallel-serial controller sequentially connected, the channel controller further includes a link parser connected to the link manager, and the link parser is further connected to the link manager.

The signal processing system provided by the embodiment of the application is used for LPTI controllers and applies LPTI interface specifications defined in OCP DC-SCM specifications. The DC-SCM implements modular server management, specifying all firmware states that are already stored on a typical processor motherboard. DC-SCM typically transfers three critical functions into one standard size module (CFM, control Function Module, control function module), including management functions including BMC functions and LPTI interfaces, security functions, and control functions. The DC-SCM architecture defines input/output ports that interoperate with a CPU (central processing unit ) board. The DC-SCM server has only the basic CPU, high-speed memory and IO connectors on the HPM (host processor module) board, all other components on the modular DC-SCM (security, control, management) board.

In the embodiment of the application, the Encoder may be an 8b/10b Encoder (8b_10b encoding), which may refer to a line Encoder that converts 8-bit data into 10-bit encoded symbols. The Decoder may be an 8b/10b Decoder (8b_10b Decoder) and may refer to the restoration of the received 10-bit encoded symbols to the original 8-bit data. The link manager state machine is a logic control module in the communication protocol for managing link establishment, maintenance and termination, and ensures that both communication parties (such as devices and nodes) can reliably establish and maintain connection through state transition and event response.

Through the system provided by the embodiment of the application, the interfaces such as the GPIO interface, the UART interface, the I2C interface, the OEM (Original Equipment Manufacturer, original equipment producer) interface, the DATA (DATA) interface and the like can transmit DATA between the mainboard and the SCM, and the system has strong portability. In the running process, a target signal of a transmitting end is received through a channel controller, the target signal is transmitted by at least one interface of a GPIO interface, a UART interface, an I2C interface, an OEM interface and a DATA interface, the channel controller transmits information to a link manager according to the received target signal, and the link manager generates a clock enabling signal according to an interface corresponding to the target signal, wherein the clock enabling signal is used for dynamically enabling or disabling the transmission of the clock signal.

In the system of the embodiment of the application, the Clock signals comprise a system Clock (system Clock), a transceiver Clock (TRANSCEIVER CLOCK AND RECEIVER Clock, TX Clk and RX Clk), a Serdes (SERializer/DESerializer), and a Serial Clock (sclk). Further, since the channel controller needs to support multiple Serdes serial clock corresponding rates, including 25Mhz, and the actual run selectable rate. The transmission of the clock signal and the clock enable signal is shown in fig. 6, and the system clock is sent to the channel controller, the frame generator, the link manager, the frame parser, the encoder, the decoder, the word alignment module, the transmitting buffer and the receiving buffer. LVDS TX issues a transmit clock signal in the transceiver clock, LVDS RX receives a receive clock signal in the transceiver clock, LVDS TX also issues a transmit serial clock signal (TX sclk) to the transmit buffer, and LVDS RX also issues a receive serial clock signal (RX sclk) to the receive buffer. Meanwhile, the system also transmits clock enabling signals to a channel controller, a frame generator, a link manager, a frame parser, an encoder, a decoder, a word alignment module, a transmitting buffer and a receiving buffer.

In a possible implementation, the structure of the link manager is shown in fig. 2, and includes a state machine (STATE MACHINE) controller, a CSR (Control & Status Register) controller, a clken (clock enable) controller, and a word alignment (word aligner) controller. Wherein the state machine controller comprises a link management state machine.

In one embodiment, as shown in fig. 3, the Link manager includes a Link management state machine, where the Link management state machine includes a Link training (LINK TRAINNING) main state, a Link configuration (Link Configuration) main state, and a Link operation (Link operation) main state, where the Link training main state is used to detect a signal of a Link and set a signal transmission speed of the Link, the Link configuration main state is used to align a signal of the Link, and the Link operation main state operates the LPTI controller according to the signal transmission speed set by the Link training main state and the aligned data parameter of the Link configuration main state. In the embodiment of the present application, when the signal processing system based on LPTI controller is restarted, the link management state machine starts to enter the first main state (i.e. the link training main state) after receiving the restart signal (reset), enters the second main state (i.e. the link configuration main state) after the first main state is completed, and enters the third main state (i.e. the link operation main state) after the second main state is completed. The return link trains the master state in the event of a link configuration master state reset or timeout. The return link trains the primary state in the event that the link operational primary state resets or times out. In the link detection main state and the link speed main state, respectively transmitting a link detection type data frame and a link speed type data frame to the signal receiving end, wherein the number of transmitted data frames is a preset number, and if the type of the data frames or the number of the data frames transmitted in the main state is different from the preset number, the corresponding main state can be reset or overtime.

For example, in the link detection master state, the SCM transmits 255 link detection type data frames and the HPM receives 7 consecutive correct data frames according to a preset rule. Then if 255 link detection type data frames are sent to the signal receiving end at the link detection master state, 7 consecutive correct data frames are not received, then a master state reset or timeout occurs. For another example, in the link speed master state, the SCM sends 7 link speed type data frames and the HPM receives 3 link speed type data frames according to a preset rule, otherwise a master state reset or timeout may occur due to link loss.

In one implementation, the channel controller may support multiple Serdes serial clock corresponding rates using a PLL (Phase-Locked Loop) reconfiguration scheme. I.e., at LINK TRAINNING master state, TX Clk and RX Clk select 25MHz and sysclk select 2.5MHz (25 MHz/10), sclk 3.125MHz (25 MHz/8), and after LINK TRAINNING master state is completed, the rates agreed by SCM and HPM (Host Processor Module ) are reconfigured by PLL, e.g., configuring TX Clk and RX Clk to 100MHz, sysclk to 10MHz, sclk to 12.5MHz. If the PLL is reconfigured, the PLL clock will be in an out-of-lock state for some time, possibly causing unpredictable risks to the logic at the later stage, and clock variation is a new challenge to speed constraints during the place and route process, requiring matching of multiple clock speeds.

In another implementation, the channel controller may use a fixed system clock (corresponding to a rate of 25 Mhz) and reconfigurable sclk and TX Clk, RX Clk (up to 25Mhzx a, i.e., 250 Mhz) to match the system clock sysclk to sclk, TX Clk, RX Clk by clock enabling. As in stage LINK TRAINING, 1 cycle enable is active every 10 clock cycles, and the clock enable pulse period is modulated according to the selected frequency after LINK TRAINING is complete. The clock domains where the Sclk, the TX Clk and the RX Clk are located have no complex logic module, and only the LVDS module can minimize the unknown risk in the clock change process.

In one implementation, the link training master state comprises a link detection (LINK DETECT) sub-state, a link speed (LINK SPEED) sub-state and a link training completion (LINK TRAINING Done) sub-state, wherein the link detection sub-state is used for receiving and transmitting a link detection type data frame, the link speed sub-state is used for receiving and transmitting a link speed type data frame, and the link training completion sub-state is used for determining a configuration frequency interval of a safety control module.

When in LINK TRAINING master state, the LVDS rate is 25Mhz, enabling 1 clock cycle to be active every 10 clock cycles for the clken clock signal. In the LINK DETECT sub-state, the Link_Detect signal is output to be valid, the Frame Generator module is notified to encapsulate the data Frame type to LINK DETECT, the FRAME PARSER detection data Frame type to LINK DETECT is notified, in the LINK SPEED sub-state, the Link_Speed signal is output to be valid, the Frame Generator module is notified to encapsulate the data Frame type to LINK SPEED, the FRAME PARSER detection data Frame type to LINK SPEED is notified, in the LINK TRAINING Done sub-state, the host state machine is notified to enter Link Configuration a host state, and the highest configurable frequency of the SCM is determined by comparing the Local (Local) and Remote (Remote) Link Speed Capabilities (LINK SPEED Capabilities). In one possible example, the design of the scheme only supports SDR mode, so that the logic of the LPTI controller can be greatly simplified, and the occupation of module resources can be reduced.

In one embodiment, referring to fig. 4, the Link configuration main state includes an IDLE (IDLE) sub-state, a Link notification alignment (LINK ADVERTISE ALIGN) sub-state, a Link notification (LINK ADVERTISE) sub-state, a Link configuration (Link configuration) sub-state, a Link reception (LINK ACCEPT) sub-state and a Link configuration completion (Link Configuration Done) sub-state, where the IDLE sub-state is used to Configure the rate of the transmission channel and the rate of the reception channel to be the data frame of the most transceiving Link notification type corresponding to the frequency interval, the Link notification sub-state is used to forward the data frame of the configuration type of the serial management module to the host processor module, and send the low-speed interface information of the serial management module to the host processor module, the Link configuration sub-state is used to send the data frame of the configuration type, the Link reception sub-state is used to forward the received data frame sent by the host processor module to the serial management module, and the Link configuration completion sub-state is used to enter the Link operation main state.

In the link configuration main state, firstly, an idle sub-state is operated, after the idle sub-state is completed, a link notification alignment sub-state is entered, after the link notification sub-state is completed, a link notification sub-state is entered, after the link notification sub-state, a link configuration sub-state and a link receiving sub-state are entered, and after the link configuration sub-state and the link receiving sub-state are completed, a link configuration completion sub-state is entered. If a time period is set (e.g., 1 millisecond) at the link advertisement alignment sub-state reset or timeout, an idle sub-state is returned. If the link is reset or lost in the link advertisement sub-state, the idle sub-state is returned. If in the link configuration sub-state, the SCM sends 32 frames of link configuration type data, the link advertisement sub-state is returned. In the link advertisement alignment sub-state, if the PLL locks and receives 3 correct data frames, the link advertisement alignment sub-state is complete. In the link advertisement sub-state, if the SCM times out for a set period of time (e.g., 1 millisecond), the link advertisement sub-state completes entering the link configuration sub-state. In the link advertisement sub-state, if the HPM times out for a set period of time (e.g., 1 millisecond) and receives 1 correct link configuration type data frame, the link advertisement sub-state is complete and enters the link reception sub-state. If 1 matching link reception type data frame is received in the link configuration sub-state, the link configuration sub-state is completed. If in the link reception sub-state 1 correct link operation data frame is received, the link reception sub-state is completed.

While in Link Configuration master state, the sub-state machine jumps from IDLE to LINK ADVERTISER ALIGN sub-state, at which time LVDS TX and LVDS RX modules are configured to the highest rate determined in a), and the PLL in the LVDS module is reconfigured, outputting clken to 0 until the PLL is reloaded, and clken is set at the latest matching rate (e.g. configurable LVDS rates of 250MHz, 50MHz, 25MHz, clken are configured to full high level, 1/5 duty cycle, and 1/10 duty cycle, respectively). After the sub-state enters LINK ADVERTISE ALIGN, the Frame Generator module is notified to encapsulate the DATA Frame with the type LINK ADVERTISE, the Frame Generator module is notified to FRAME PARSER to detect the DATA Frame with the type LINK ADVERTISE, in LINK ADVERTISE, the DATA Frame is continuously received and transmitted LINK ADVERTISE, in Link Configurate, the SCM sends the configured type DATA Frame to the HPM to inform the signal receiving end of the low-speed interface information (including at least one of GPIO interface, I2C interface, UART interface, OEM interface and DATA interface) of the SCM, in LINK ACCEPT, the HPM sends the Accept DATA Frame to the SCM, and after the sub-state enters Link Configuration Done, the host state machine is notified to enter Link operation main state.

On the basis of the embodiment shown in fig. 2, the address and division of registers in the CSR Controller are shown in the general control and status registration map shown in table 1 below, and the LTPI control and status registration shown in table 2. When the state machine changes, the state of LPTI itself is updated to the Link Status register, and the peer state information received at FRAME PARSER is updated to the register.

TABLE 1

Table 2 the state of the local LTPI link state and the correspondence of codes are shown in table 3 below.

Status of	Encoding
		Link detection	0x0
Link speed	0x1
		Announcement of	0x2
Configuration of	0x3
		Operation	0x4
Reservation of	0x5-0xF

Table 3 the state and code correspondence for the remote LTPI link state is shown in table 4.

Table 4LTPI shows the correspondence between link speeds and codes.

Status of	Encoding
		Fundamental frequency (based freq) x1	0x0
Fundamental frequency x2	0x1
		Fundamental frequency x3	0x2
Fundamental frequency x4	0x3
		Fundamental frequency x6	0x4
Fundamental frequency x8	0x5
		Fundamental frequency x10	0x6
Fundamental frequency x12	0x7
		Fundamental frequency x16	0x8
Fundamental frequency x24	0x9
		Fundamental frequency x32	0xA
Fundamental frequency x40	0xB
		Reservation of	0xC-0xF

TABLE 5

Based on fig. 2, the WordAlign controller is a control module which interacts with the Word Aligner module in the LINK MANAGER module, when the FRAME PARSER module is in the IDLE state, the WordAlign controller sends 1 en_ rxdata _slip (Enable RECEIVED DATA SLIP) valid signal to the WordAligner module every 16 clken signals until CommaSymbol (comma symbol) detected by the FRAME PARSER module matches with the current Link state. Every time the frame counter in WordAlign controllers receives 1 matching signal, 1 is added (the initial value of the frame counter is 0, and the frame counter is reset to 0 when the Link state jumps), wordAlign controls the output of the value of the frame counter to STATEMACHINE controllers (reference is provided for LINK TRAINING, link Configuration and other state machine jumps).

The Frame Generator shown in fig. 1 is mainly used to encapsulate data frames, which are divided into a plurality of types. Each data Frame is fixed to 16 bits in length, e.g., LINKDETECT data frames, followed by a Frame subtype code. In the Frame Generator module, a state machine is set, as shown in FIG. 5, including a master state S0 through a master state S15. The main states S0-S15 correspond to bytes offset by 0-15 in the transmission data frame, and are valid in the main states S0-S15, clken. Link status and other frame content are input by LINKMANANGER modules and Channel controller modules. In the master state S15, if the PLL is locked, an idle master state is entered, and in the idle master state if clken is active, a master state S0 is entered.

The type of data frame that the frame generator can encapsulate is a frame type digest as shown in table 6.

TABLE 6

Table 7 shows the sub-frame field values corresponding to the frame types.

TABLE 7

Table 8 shows detailed information of the link detection type data frame.

TABLE 8

FRAME PARSER is mainly used for data Frame parsing, and the state machine includes a main state S0 to a main state S15, contrary to the Frame Generator function. The main states S0-S15 correspond to bytes offset by 0-15 in the data frame, and data of corresponding fields are output to LINK MANAGER or Channel Controller. In addition, the frame parser also cooperates LINK MANAGER to count the input data and frame number in the link training, i.e. LINK TRAINING and Configuration phases, so that LINK MANAGER can judge the link state and word alignment state.

In the embodiment of the application, the encoder and the decoder can respectively finish 8b/10b encoding and decoding, and the encoding and decoding are finished by adopting a table look-up.

The interfaces of the TX FIFO and the RX FIFO are shown in fig. 7 and 8, respectively, and in the example shown in fig. 7, the interfaces of the TX FIFO include a reset (rst) interface, a sysclk interface, a write data (wrdata) interface, a write enable signal (wren) interface, an almost full signal (almost full) interface, a full signal (full) interface, a sclk interface, a read data (rddata) interface, a read enable signal (rden) interface, an almost empty (almost) interface, and an empty (empty) interface. In the example shown in fig. 8, the interface of the RX FIFO is the same as the TX FIFO. The data width of wrdata interfaces and rddata interfaces is 10, the depth can be set to 8×16, the threshold of an all full interface can be set to 7x16,almost empty interfaces, and the threshold can be set to 16.

On the basis of the embodiment shown in fig. 1, the functional block diagram and functional schematic of the word alignment module are shown in fig. 9, and include a slip_counter (offset counter), a shift module, and a data_sel (data strobe) module. When en_ rxdata _slip (enable received data offset, from LINK MANAGER module) is active, slip_counter is incremented by 1 (assuming the count range of the offset counter is 0-N, which may be an integer greater than 0, e.g., N is 10). As shown in connection with fig. 9 and 10, the shift module connects the front and back 2 i_ rxdata (received data input) to 1 data variable data of width 2N, shifts data left by N bits when i_ rxdata _vld is valid, places new i_ rxdata in N-1~0 bits of data, and in the data_sel module, intercepts a piece of data output of width N from data based on the value of the slice_counter, for example, when the slice_counter= 0, the output o_ rxdata (received data output) is padded to N-1 bits to 0 bits of data, when the slice_counter= 1, the output o_ rxdata is padded to N-1+1 bits to 1 bits of data, when the slice_counter= 2, the output o_ rxdata is padded to N-1+2 bits to 2 bits of data, and so on.

On the basis of fig. 1, the functional block diagram of Channel Controller is shown in fig. 11, and the main function of the channel controller is to convert the low-speed interfaces such as GPIO, I2C, UART and the like into the format of the content of the transmitted data frame or convert the content of the received data frame into the low-speed Interface signal in the Link operation stage. The channel controllers include low latency GPIO channel 0 (low latency GPIO channel 0), low latency GPIO channel 1 (low latency GPIO channel 1), general latency GPIO channel 0 (normal latency GPIO channel 0), general latency GPIO channel 1 (normal latency GPIO channel 1), UART channel, I2C0/1 channel, I2C2/3 channel, I2C4/5 channel, data channel. The channel controller is capable of transmitting information between an interface (interface) and a data frame multiplexer, the data frame multiplexer transmitting information of a general-delay GPIO channel 0, a general-delay GPIO channel 1, a UART channel, an I2C0/1 channel, an I2C2/3 channel, an I2C4/5 channel, a data channel to the frame generator and the frame parser, or transmitting information of the frame generator and the frame parser to the general-delay GPIO channel 0, the general-delay GPIO channel 1, the UART channel, the I2C0/1 channel, the I2C2/3 channel, the I2C4/5 channel, the data channel. The Data frame is divided into IO (input/output) frame and Data (Data type) frame, the Data frame is burst Data frame, the Data frame mux (multiplexer) is normally connected with interfaces such as UART, I2C and the like, namely the Data frame is generally IO frame, when DATA CHANNEL (Data channel) transmission signals are valid, the mux is switched to DATA CHANNEL, and when the received Data frame is Data frame, the mux is switched to DATA CHANNEL.

Illustratively, the format of the IO frame is shown with reference to Table 9 below.

TABLE 9

The Low Latency GPIO Channel functions in fig. 10 are shown in fig. 11, low Latency GPIO Channel to sample and convert GPIOs in real time to data frame content, or to convert data frames to real-time IO signals. When each clken clock enable is active, the GPIO is latched into the register and the register is output to the Frame Generator. Similarly, byte (bit) corresponding to Low Latency GPIO of the data frame content received from FRAME PARSER is latched into reg (registration space) when clken is valid and output to GPIO.

As shown in fig. 12, the function Normal Latency GPIO Channel refers to the GPIO interface corresponding to the Normal Latency GPIO Channel channel has no high real-time requirement, but the number of supported interfaces is large, and the GPIO value is transferred to the Frame Generator by a multi-Frame time division multiplexing mode. Setting a sending counter frame_counter, wherein the maximum value of the counter depends on the number of GPIO channels supported, when the number of GPIO channels required to be supported is 8, the maximum value of the counter is 8-1=7, when the frame_offset is 15, the counter +1 selects the corresponding GPIO channel in mux for next frame data transmission, and when clken arrives, the data of the GPIO channel is latched into reg and output to FrameGenerator. Similarly, when receiving a data frame, clken, lock the byte corresponding to the data frame to reg, and then switch mux through the receiving counter frame_counter, so as to allocate the data to the corresponding GPIO channel.

The UART Channel function is shown in fig. 13. UART interface to data frame conversion is realized, wherein UART interface is sampled 3 times every 1 data frame, UART interface TX value sampling is latched into reg1 when frame_offset is 0, 5 and 10, and data in reg1 is latched into reg2 and output to FrameGenerator modules when frame_offset is 15. Similarly, when clken is valid, the received data frame content is latched into reg4, when the offset is 15, the content of reg4 is latched into reg3, and when the offset is 0, 5 and 10, the content in reg3 is converted into UART RX signals.

DATA CHANNEL functions are shown in fig. 14 for implementing conversion of a local bus (local bus) into a data frame format, which is as follows. Local bus conversion and payload (payload) corresponding to a Data frame are converted from each other, and payload is fixed to 10x8bit width.

The embodiment of the application also provides a signal processing method based on LPTI controllers, which is applied to the signal processing system based on LPTI controllers provided by any one of the embodiments of the application, as shown in fig. 15, the signal processing method based on LPTI controllers includes the following steps S151 to S152.

Step S151, in the starting state of the link management state machine, configuring the system clock to be a fixed frequency, and configuring the serial clock, the receiving clock and the transmitting clock to be non-fixed frequencies.

In step S152, in the start state of the link management state machine, according to the main state of the state machine, enable signals of the link manager to the system clock, the serial clock, the receiving clock and the transmitting clock are determined, where the enable signals are used to match the system clock, the serial clock, the receiving clock and the transmitting clock with the main state of the state machine.

In one embodiment, the link management state machine comprises a link training main state, a link configuration main state and a link operation main state, and the signal processing method based on LPTI controller further comprises the following steps:

In the link configuration main state, aligning the signals of the link;

In a link speed sub-state of the link training main state, the link manager outputs a link speed signal to be effective, sends a second encapsulation notification to the frame generator, and sends a second detection notification to the frame parser, wherein the second encapsulation notification is used for notifying the frame generator that the type of an encapsulation data frame is the link speed, and the second detection notification detects that the type of the data frame is the link speed;

It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.

Fig. 16 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 16, the electronic device 6 of this embodiment comprises a processor 60, a memory 61 and a computer program 62 stored in said memory 61 and executable on said at least one processor 60, said processor 60 comprising the processor and the respective cores of the server in any of the system embodiments described above.

The electronic device 6 may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, etc. The electronic device may include, but is not limited to, a processor 60, a memory 61. It will be appreciated by those skilled in the art that fig. 3 is merely an example of the electronic device 6 and is not meant to be limiting as the electronic device 6, and may include more or fewer components than shown, or may combine certain components, or different components, such as may also include input-output devices, network access devices, etc.

The Processor 60 may be a central processing unit (Central Processing Unit, CPU), the Processor 60 may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL processors, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), off-the-shelf Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 61 may in some embodiments be an internal storage unit of the electronic device 6, such as a hard disk or a memory of the electronic device 6. The memory 61 may also be an external storage device of the electronic device 6 in other embodiments, such as a plug-in hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD) or the like, which are provided on the electronic device 6. Further, the memory 61 may also include both an internal storage unit and an external storage device of the electronic device 6. The memory 61 is used for storing an operating system, application programs, boot loader (BootLoader), data, other programs, etc., such as program codes of the computer program. The memory 61 may also be used for temporarily storing data that has been output or is to be output.

The embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program realizes the steps executed by the server or any kernel in each method embodiment when being executed by a processor.

Embodiments of the present application provide a computer program product that, when executed on an electronic device, causes the electronic device to perform the steps performed by the server or any one of the kernels in the above-described method embodiments.

The embodiment of the application also provides a chip which comprises a processing unit and a communication unit, wherein the processing unit can be a processor, and the communication unit can be an input/output interface, a pin or a circuit, and the like. The processing unit may execute computer instructions to cause a computer device to perform the steps performed by the server or any one of the cores in any one of the method embodiments provided by the embodiments of the present application described above.

Optionally, the computer instructions are stored in a storage unit.

Alternatively, the storage unit is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit in the terminal located outside the chip, such as a ROM or other type of static storage device that can store static information and instructions, a random RAM, etc. The processor mentioned in any of the above may be a CPU, microprocessor, ASIC, or one or more integrated circuits for controlling the execution of the programs of the above method. The processing unit and the storage unit may be decoupled and respectively disposed on different physical devices, and the respective functions of the processing unit and the storage unit are implemented by wired or wireless connection, so as to support the system chip to implement the various functions in the foregoing embodiments. Or the processing unit and the memory may be coupled to the same device.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/device and method may be implemented in other manners. For example, the apparatus/device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium can include at least any entity or device capable of carrying computer program code to an electronic archive generating device/terminal device, recording medium, computer Memory, read-Only Memory (ROM), random access Memory (RAM, random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.

The foregoing embodiments are merely illustrative of the technical solutions of the present application, and not restrictive, and although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that modifications may still be made to the technical solutions described in the foregoing embodiments or equivalent substitutions of some technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. The signal processing system based on LPTI controller is characterized in that the LPTI controller comprises a channel controller, a link manager, a transmitting channel and a receiving channel, wherein the channel controller is connected with the link manager, the transmitting channel and the receiving channel;

the link manager is connected with the transmitting channel and the receiving channel;

2. The system of claim 1, wherein the link management state machine of the link manager comprises a link training master state, a link configuration master state and a link operation master state, wherein the link training master state is used for detecting signals of a link and setting signal transmission speeds of the link, the link configuration master state is used for signal alignment of the link, and the link operation master state operates the LPTI controller according to the signal transmission speeds set by the link training master state and the data parameters aligned by the link configuration master state.

3. The system of claim 2, wherein the link training master state comprises a link detection sub-state, a link speed sub-state and a link training completion sub-state, wherein the link detection sub-state is used for receiving and transmitting link detection type data frames, the link speed sub-state is used for receiving and transmitting link speed type data frames, and the link training completion sub-state is used for determining a configuration frequency interval of a security control module.

4. The system of claim 3, wherein the link configuration master state comprises an idle sub-state, a link notification alignment sub-state, a link notification sub-state, a link configuration sub-state, a link reception sub-state and a link configuration completion sub-state, wherein the idle sub-state is used for configuring a rate of the transmission channel and a rate of the reception channel to a maximum frequency corresponding to the frequency interval and a frequency for reconfiguring a clock enable signal, the link notification alignment sub-state is used for receiving and transmitting a link notification type data frame, the link notification sub-state is used for forwarding a data frame of a configuration type by a serial management module to a host processor module and transmitting low-speed interface information of the serial management module to the host processor module, the link configuration sub-state is used for transmitting a data frame of a configuration type, the link reception sub-state is used for forwarding a received data frame transmitted by the host processor module to the serial management module, and the link configuration completion sub-state is used for entering a link operation master state.

5. A signal processing method based on LPTI controller, applied to the signal processing system based on LPTI controller according to any one of claims 1 to 4, characterized in that the method comprises:

And in the starting state of the link management state machine, determining enabling signals of a link manager to a system clock, a serial clock, a receiving clock and a transmitting clock according to the main state of the link management state machine, wherein the enabling signals are used for enabling the system clock, the serial clock, the receiving clock and the transmitting clock to be matched with the main state of the link management state machine.

6. The method of claim 5, wherein the link management state machine comprises a link training master state, a link configuration master state, and a link running master state, the method further comprising:

In the link configuration main state, aligning the signals of the link;

7. The method of claim 6, wherein detecting the signal of the link and setting the signal transmission speed of the link in the link training master state comprises:

8. The method of claim 7, wherein said aligning signals of a link in said link configuration master state comprises:

Forwarding a data frame of a configuration type of a serial management module to a host processor module in a link notification sub-state of the link configuration main state, and sending low-speed interface information of the serial management module to the host processor module;

9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 8 when executing the computer program.

10. A computer readable storage medium storing a computer program, which when executed by a processor performs the method according to any one of claims 1-8.