CN120669098A

CN120669098A - Low pin count scanning without dedicated scan enable pins

Info

Publication number: CN120669098A
Application number: CN202510313812.XA
Authority: CN
Inventors: S·贾因; S·帕塔克
Original assignee: Italian Semiconductor International Co
Current assignee: Italian Semiconductor International Co
Priority date: 2024-03-18
Filing date: 2025-03-17
Publication date: 2025-09-19
Also published as: US20250290980A1; EP4621425A1; US12480993B2

Abstract

The present disclosure relates to low pin count scan without a dedicated scan enable pin. According to one embodiment, a method for testing using a scan chain without a separate scan enable pin is provided. The method includes selectively indicating a capture phase and a load phase/unload phase of the scan chain based on encoding of a scan enable signal in a desired signal and a mask signal; loading test parameters into the scan chain during the load phase/unload phase; operating the scan chain in a functional mode during the capture phase; and generating an error signal based on comparing the output of the scan chain during the unload phase with the desired signal, wherein the mask signal is used to mask the output of the scan chain during cycles with invalid results.

Description

Low pin count scanning without dedicated scan enable pins

Technical Field

The present disclosure relates generally to design for test (DFT) and, in particular embodiments, to DFT devices, circuits, and methods of operation having low pin count scanning and no dedicated scan enable pins.

Background

Integrated Circuits (ICs) are typically tested for faults. In particular, logic circuits of integrated circuits are typically tested using a method commonly referred to as scan testing. During scan testing, a test pattern (pattern) is shifted in through one or more flip-flop chains (i.e., scan chains) to stimulate one or more logic circuits. The results of the stimulated logic are loaded into the scan chain and shifted out for evaluation. When the shifted out pattern matches the expected pattern (based on normal operation of one or more logic circuits), no faults are detected and the circuit may be free of defects. When the shifted out pattern does not match the expected pattern, a fault is detected.

Achieving higher scan compression is the core of Integrated Circuit (IC) testing. This goal is becoming more and more important as it directly affects the test cost and thus the profitability of the IC design. Scan compression techniques allow more IC functions to be tested with fewer test vectors. As the complexity and density of ICs continue to grow, the amount of test data required to ensure quality and reliability also increases. This presents challenges for the time required to store test data and apply the test. Higher scan compression addresses this challenge by reducing the amount of test data required, which can significantly reduce test application time and test data volume. The reduction in test time and data translates directly into cost savings because less time is used on Automated Test Equipment (ATE) to reduce the cost per chip, thereby increasing overall design revenue by achieving higher manufacturing throughput.

With the advent of new technologies and applications (such as those found in the automotive industry), multi-site testing requirements proliferate. Multiple devices or chips can be tested simultaneously in parallel by multi-site testing, thereby improving throughput and efficiency. This approach is particularly beneficial when producing large numbers of automotive related chips, which require stringent quality standards due to their critical security applications. However, multi-site testing requires that large amounts of scan data be delivered to multiple dies simultaneously without affecting speed or reliability. With this challenge, new failure models have emerged, resulting in explosive growth in the amount of test data, due to the increasing complexity of automotive electronics and the need for high reliability. Thus, multi-site test requirements and new fault models in automotive applications are driving the need for enhanced scan compression solutions capable of handling dramatically increased scan volumes.

In view of these challenges, it would be advantageous to have a solution to manage and mitigate lengthy test application times without sacrificing test coverage or fault detection capabilities to meet increasing test requirements and to maintain the integrity and reliability of complex systems in safety critical areas such as automotive electronics.

Disclosure of Invention

Technical advantages may generally be realized by embodiments of the present disclosure, which describe a design of a test (DFT) device, circuit, and method of operation with low pin count scanning and no dedicated scan enable pins.

A first aspect relates to a method for testing using a scan chain without an independent scan enable pin. The method includes selectively indicating an acquisition phase and a loading/unloading phase of a scan chain based on an encoding of a scan enable signal in a desired signal and a masking signal, loading test parameters to the scan chain in the loading/unloading phase, operating the scan chain in a functional mode in the acquisition phase, and generating an error signal based on comparing an output of the scan chain in the unloading phase with the desired signal, wherein the masking signal is used to mask the output of the scan chain for periods having invalid results.

A second aspect relates to a method for testing using a scan chain without an independent scan enable pin. The method includes preloading a first number of shift cycles into a shift counter circuit, the first number of shift cycles corresponding to a set of test patterns, preloading a second number of capture cycles into the capture counter circuit, the second number of capture cycles corresponding to the set of test patterns, initiating a loading/unloading phase of the test by maintaining an internally generated scan enable signal at a high logic level, wherein the shift counter circuit counts the number of shift cycles preloaded, transitioning the internally generated scan enable signal to a logic level in response to the shift counter circuit completing the preloaded count, wherein the transitioning initiates the capture phase of the test, and initiating a subsequent loading/unloading phase of the test by transitioning the internally generated scan enable signal to the high logic level in response to the capture counter circuit completing the preloaded count.

A third aspect relates to a method for testing using scan chains in a digital circuit without independent scan enable pins. The method includes designating a first pin assignment having N input pins and R merge input pins, N and R being integers, N corresponding to a number of input pins for carrying scan-in chain test data and R corresponding to a number of input pins for carrying a merged desired test result and masking instruction signal, designating a second pin assignment having N input pins and M output pins, M being integers and corresponding to a number of output pins for carrying scan-out chain test data, inserting a comparator circuit and a decoding logic circuit into the digital circuit, generating an N by M codec, integrating the N by M codec and inserting a scan chain, wherein a device register is spliced into the plurality of scan chains and coupled between the compression circuit and the decompression circuit, and decoding an internally generated scan enable signal using one of 2 ^R states provided by the R merge input pins, wherein 3 ^N states are decoded outputs from the decoding logic circuit.

Embodiments may be implemented in hardware, software, or any combination thereof.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of an architecture for testing scan chains;

FIG. 2 is a block diagram of an on-chip comparator circuit;

FIG. 3 is a block diagram of an embodiment logic circuit;

FIG. 4 is a block diagram of an embodiment circuit configured to identify a shift stage and a capture stage;

FIG. 5 is a block diagram of an embodiment on-chip comparator circuit;

FIG. 6 is a block diagram of an embodiment comparator circuit;

FIG. 7 is an example table mapping five binary input states to data having one of three states;

FIG. 8 is a flow chart of an embodiment method;

FIG. 9 is a flow chart of an embodiment method, and

Fig. 10 is a flow chart of an embodiment method.

Detailed Description

The present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments are merely illustrative of specific configurations and do not limit the scope of the claimed embodiments. Features from different embodiments may be combined to form further embodiments unless otherwise specified. Various embodiments are illustrated in the drawings, wherein like components and elements are identified by like reference numerals, and duplicate descriptions are omitted for brevity.

Variations or modifications described in one embodiment may also be applied to other embodiments. Further, various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

While aspects of the invention are described primarily in the context of design for test (DFT), it should also be understood that these aspects of the invention may also be applied to other aspects of circuit design. Embodiments of the present disclosure are applicable to combination and sequential compression, and may be applied to factory testing using, for example, automatic Test Pattern Generation (ATPG) tools, or field testing using, for example, logic built-in self-test (LBIST) controllers. In particular, aspects of the present disclosure may be applied to DC-DC Active Matrix Organic Light Emitting Diode (AMOLED) display drivers, power Management Integrated Circuits (PMICs), rectifier-type applications, and the like.

Advances in semiconductor technology, particularly in industries requiring high reliability such as automotive and medical equipment, have led to new failure models that override traditional fixed and transitional failures. Complex fault models, such as small delay faults (SDDs) and cell-aware fault models, are being developed to capture fine defects that occur with smaller geometries, which can significantly impact the performance and reliability of ICs. These contemporary failure models take into account manufacturing process variations and subtle interactions between transistors within the cell that may lead to failure. While these advanced fault models provide higher quality testing, they also help to greatly increase scan volume. This is due to the additional test patterns generated to cover these finer defects. The resulting extended scan data must be applied during testing to ensure that the IC meets stringent quality requirements, thereby increasing the amount of data that needs to be managed during testing.

The additional test patterns required by these new fault models translate directly into increased test time per device. Since testing is performed at various stages of the overall manufacturing process, and potentially at the end of line quality checks, increased testing time becomes a recurring cost per shipping facility. This affects the overall cost base of the IC and may reduce the profit margin, so semiconductor companies must seek methods for reducing test time without affecting quality. Test time may be reduced by more advanced scan compression techniques, improved test equipment, enhanced design for testability (DFT) practices, and optimizing test schedules to minimize overhead.

Advantageously, embodiments of the present disclosure allow for significant savings in testing costs, which is manifested in an increase in product life revenue. The proposed compression architecture does not sacrifice scan data and is flexible enough to be used with existing scan architectures.

In an integrated circuit test environment limited by a limited number of external pins (e.g., available at chip boundaries or packages), a decompressor is typically used to internally fan out these few input test signals over multiple scan chains to maximize scan test coverage. The intermediate layer then bridges the gap between the decompressor and the compressor to process test data from the scan chain extension network.

The middle layer may include various functional components such as logic gates, multiplexers, buffers, or any other form of digital circuitry to facilitate the processing of test data within the scan chain. It may also involve error detection and correction mechanisms, signal routing, control logic for scan chain selection, or any other related art function that supports test infrastructure within the integrated circuit.

The compressor integrates the responses from these scan chains to compress them into several outputs corresponding to the limited external pins. This strategic arrangement allows extensive internal testing without a direct correlation between the number of scan chains and the number of external pins, thereby optimizing pin utilization during the testing phase. Using the previously assigned scan enable pins as internal test signals in a limited number of external pins may reduce the overall scan test volume and increase the test compression.

Fig. 1 illustrates a block diagram of an architecture for testing a scan chain 100 in, for example, a digital circuit. Scan chain 100 includes a first scan flip-flop 102, a second scan flip-flop 104, a third scan flip-flop 106, a first multiplexer 108, a second multiplexer 110, a third multiplexer 112, and combinational logic 114, which may or may not be arranged as shown. Scan flip-flop 100 may include additional components not shown, such as additional scan flip-flops and associated multiplexers for each scan flip-flop.

The first scan flip-flop 102, the second scan flip-flop 104, and the third scan flip-flop 106 are arranged in the scan chain 100 to test one or more logic components of the combinational logic 114 in the digital circuit using, for example, ATPG techniques.

The data input (D) of the first scan flip-flop 102 is coupled to the output of the first multiplexer 108, the data input (D) of the second scan flip-flop 104 is coupled to the output of the second multiplexer 110, and the data input (D) of the third scan flip-flop 106 is coupled to the output of the third multiplexer 112. The outputs of the first scan flip-flop 102 and the second scan flip-flop 104 are coupled to the combinational logic 114. Each multiplexer 108, 110, and 112 includes a functional input terminal, a test input terminal, a select terminal, and an output terminal. Functional input terminals of the second multiplexer 110 and the third multiplexer 112 are coupled to the combinational logic 114.

The value at the select terminal of each multiplexer 108, 110 and 112 determines whether the functional signal or the test input signal (scan_in) is selected at its output terminal by the SCAN enable signal (scan_en). The output signal (scan_out) of the third SCAN flip-flop 106 provides the result of the test mode for the digital circuit during the test mode.

A clock signal (scan_clk) is coupled to the clock input of each of the first SCAN flip-flop 102, the second SCAN flip-flop 104, and the third SCAN flip-flop 106. The clock signal controls the timing of the operation and synchronizes the movement of data in the scan chain 100. In test mode, scan chain 100 uses clock signals to serially shift test data into and out of scan flip-flops. When a clock signal is applied, test data is moved from one scan flip-flop to the next. In functional mode, the clock signal is used to control the normal operation of the digital circuit to ensure that data is moved in the circuit and to ensure that the scan flip-flops are synchronized.

By changing the input at the selection terminal of the corresponding multiplexer by means of a SCAN enable signal (scan_en), a transition from functional mode to test mode and vice versa can be achieved. This provides an efficient mechanism for testing combinational logic 114 within digital circuits during normal operation and when fault detection and diagnosis is performed. The workflow between functional and test modes is different, determined by the logic level of the scan enable signal at the select terminal of each multiplexer 108, 110 and 112. During functional mode (i.e., when the scan enable signal is deasserted), multiplexers 108, 110, and 112 select the functional inputs. This allows the digital circuit to operate normally by passing the input signal through the combinational logic 114 and scan chain 100. The first scan flip-flop 102, the second scan flip-flop 104, and the third scan flip-flop 106 produce the functional outputs of the combinational logic 114.

During test mode (i.e., when the scan enable signal is asserted), multiplexers 108, 110, and 112 select the test inputs. The predefined test pattern is fed to the SCAN chain 100 as a test input signal (scan_in). After the test pattern is completely shifted into the SCAN chain, the clock signal then shifts OUT the result of the test pattern as an output signal (scan_out). The outputs of scan flip-flops 102, 104, and 106, which are triggered by a clock signal, provide test data reflecting the state of combinational logic 114 under test.

During test mode, scan testing is typically divided into three phases, scan in, capture, and scan out. In the scan in phase, a test pattern is provided to the scan chain. The test mode passes through the scan chain 100, where the third scan flip-flop 106 captures and stores the output of the scan chain 100. During the scanout phase, the output signal (scan_out) is compared to an expected value to identify a discrepancy, indicating a fault or error in the SCAN chain 100.

One persistent bottleneck in efficiently managing scan testing is the limited number of available scan pins, which limits the amount of scan data that can be loaded onto the device per cycle. In view of this limitation, IC designers and test engineers are faced with the challenge of increasing the amount of scan data that can be fed into and out of a chip in a given test period. Such constraints typically require different data compression and scan architecture optimization methods. Advances in multiplexing techniques, serial scanning methods, and on-chip decompression hardware have been explored to maximize the utilization of the available pins. Each technique aims to amplify the amount of data passing through each scan pin, thereby achieving wider test coverage while respecting pin count limitations. Thus, strategies that allow for higher compression of test data and more efficient data delivery systems are critical to reduce test time, save costs, and ensure that the delivered equipment meets the high quality standards required for advanced applications.

The test procedure includes different loading, capturing and unloading phases. Each stage corresponds to a different step in the test procedure, controlled by the state of the scan enable signal. In the loading phase, the SCAN enable signal (scan_en) is set to a high logic level. IN this state, test data is loaded into the SCAN chain through the scan_in pin. This action prepares the internal flip-flops of scan chain 100 for the particular test data pattern required for the upcoming acquisition phase.

After the test data is loaded, the system transitions to the capture phase. At this stage, the SCAN enable signal (scan_en) is set to a low logic level for one or two clock pulses. During this time, the integrated circuit operates in its functional mode (normal operation) to capture functional data within the flip-flops that were previously loaded with test data.

After capturing the functional data, an offloading phase begins in which the SCAN enable signal is again asserted (scan_en) (i.e., high logic level). The data captured in the flip-flop is now serially shifted out to the external pin for analysis. During this shift, new test data for the next test period may be loaded simultaneously, thereby optimizing test efficiency.

During these phases, in particular during loading and unloading, the SCAN enable signal (scan_en) remains static or pseudo-static, it remains high during both the loading phase and the unloading phase, and drops low only during the acquisition phase. Its predictability means that there is no need to associate the SCAN enable signal (scan_en) with different functions at different clock cycles.

Thus, by controlling the state of the multiplexer that directs the functional signal or test mode to the SCAN flip-flop, the SCAN enable signal (scan_en) is responsible for switching between the functional mode of operation and the test mode of operation. During the SCAN phase (both SCAN in and SCAN out), the SCAN enable signal (scan_en) remains static, either always active or always inactive. Thus, dedicating only the entire pin to the SCAN enable signal (scan_en) may result in inefficiency in use, particularly considering that the pin on the integrated circuit is a resource that can increase design complexity and production cost.

Aspects of the present disclosure propose a SCAN compression architecture that eliminates the traditional reliance on an external SCAN Enable (SE) pin that feeds a SCAN enable signal (scan_en) from an external device or circuit. In an embodiment, the method involves internal (i.e., on-chip) decoding of the capture window from the existing scanin state, thereby squeezing (squeeze) the device compression more efficiently within a limited pin count, reducing test costs. The proposed architecture derives an internal SCAN enable signal (scan_en) without an additional pin for Automatic Test Pattern Generation (ATPG).

Fig. 2 illustrates a block diagram of an on-chip comparator circuit 200. In an embodiment, an on-chip comparator circuit 200 is coupled to the output of the scan chain 100. The on-chip comparator circuit 200 receives, for example, an output signal (scan_out) of the SCAN chain 100 (or from a compressor) as a SCAN input (scan_in). The scan input is compared to an expected signal (EXPECT) to determine if the digital circuit is operating properly. A MASK signal (MASK) is used to indicate which period of the scan chain or compressor output should be ignored.

The on-chip comparator circuit 200 includes an XOR gate 202, an AND gate 204 with one inverting input, an OR gate 206, AND a flip-flop 208, which may OR may not be arranged as shown. The on-chip comparator circuit 200 may include additional components not shown. For example, the on-chip comparator circuit 200 may include an additional OR gate coupled to the output of the AND gate 204 AND an accumulator signal for testing multiple scan chains with the same circuit.

XOR gate 202 is a digital logic gate having two inputs and one output. The digital logic gate outputs a high logic level signal only when the two inputs have different logic values. The first input of XOR gate 202 is coupled to, for example, the output signal (scan_out) of SCAN chain 100 (or the output of the compressor), while the second input is coupled to the desired signal (extract) which is used as a reference for comparison.

The output of XOR gate 202 is coupled to the non-inverting input of AND gate 204. The MASK signal (MASK) is provided to the inverting input of AND gate 204. When the output of XOR gate 202 is at a high logic level AND the MASK signal (MASK) is at a low logic level, AND gate 204 outputs a logic high signal.

The output of AND gate 204 is coupled to a first input of OR gate 206. A second input of OR gate 206 is coupled to an output (Q) of flip-flop 208. The output of OR gate 206 is coupled to an input (D) of flip-flop 208. When at least one input of the OR gate 206 is at a high logic level, the output of the OR gate 206 is at a high logic level.

In an embodiment, the flip-flop 208 is a D-type flip-flop. When a clock pulse occurs, flip-flop 208 stores the data at its input (D). The stored data is available at its output (Q).

XOR gate 202 compares the output signal (scan_out) of SCAN chain 100 with the desired signal (extract). If the two are equal (meaning that both bits are either logic low or both logic high), XOR gate 202 outputs a logic low signal. If they are different, the XOR gate outputs a logic high signal to indicate the difference.

AND gate 204 allows masking (ignoring) certain bits during the comparison. When the MASK signal (MASK) is at a high logic level, the inverting input goes to a low logic level to enable AND gate 204 to pass the output of XOR gate 202 (indicating a mismatch) to OR gate 206. If masking of a particular bit is not desired, the masking signal (MASK) will be at a low logic level to prevent any difference signals from passing.

The OR gate 206 acts as an accumulator of differences along with the flip-flop 208. If any previous difference is detected and stored in flip-flop 208 (indicating that its output (Q) is at a high logic level), it will ensure that the output of OR gate 206 remains at a high logic level even if the current comparison does not show a difference. In this way, any detected errors are captured and stored until the errors can be handled. The output (Q) of flip-flop 208 may be read through, for example, an internal joint test action group (ijjtag) interface as a pass/fail indicator for each scan chain.

The on-chip comparator circuit 200 may allow real-time error detection during scan chain testing by comparing each scan bit to the desired signal and selectively ignoring the bit as needed using the masking signal. The accumulation function ensures that even transient errors can be captured without being overridden by subsequent correct comparisons.

The error detection mechanism provided in the on-chip comparator circuit 200 may be summarized using table I.

SCAN_IN	EXPECT	MASK
			SSSSSSSS	EEEEEEEE	00000000
SSSSSSSS	EXEEXEEE	01001000
			SSSSSSSS	XXXXXXXX	11111111

TABLE I

Table I includes three columns. The first column indicates the output of the SCAN chain 100 or the compressor as a SCAN IN signal (scan_in). The second column indicates various possible desired signals (EXPECT). The third column indicates various possible masking signals (MASK). In Table I, eight chains with monocycle data are shown, however, it should be understood that the number of chains is not limiting and fewer or more may be considered in embodiments.

The SCAN IN signal (scan_in) of the on-chip comparator circuit 200 of each SCAN chain is denoted as 'S', which may be a high logic level ('1') or a low logic level ('0'). The desired signal (EXPECT) is denoted as 'E', which is either a high logic level or a low logic level. When the desired signal (EXPECT) is to be ignored during this period, the desired signal (EXPECT) is denoted as 'X', which may be a high logic level or a low logic level without affecting the output of the on-chip comparator circuit 200. When the SCAN IN signal (scan_in) will not be ignored during this period, the MASK signal (MASK) is at a low logic level ('0'). Conversely, when the SCAN IN signal (scan_in) is to be ignored during this period, the MASK signal (MASK) is at a high logic level ('1').

The first row corresponds to the case where the SCAN IN signal (SCAN IN) is compared with the desired signal (extract) without masking. The third row corresponds to the case where the SCAN IN signal (scan_in) is to be masked (i.e., the output of the SCAN chain is invalid) regardless of whether the desired signal (extract) is '1' or '0'. The second row corresponds to the case where several scan chains are masked (i.e., some scan chains provide an undetermined output and will not be compared to the expected value). The SCAN IN signal (SCAN IN) is compared with the expected signal (extract) only when the MASK signal (MASK) is equal to the low logic level. For the second row, the desired signal (extract) may be set to '1' or '0' IN a period IN which the SCAN input signal (scan_in) is to be ignored, because the MASK signal (MASK) of the period is set to a high logic level ('1').

Thus, it can be observed that when the SCAN IN signal (scan_in) is to be ignored, the desired signal (extract) becomes redundant because the MASK signal (MASK) determines the output of the on-chip comparator circuit 200. Thus, the capture or loading phase may be indicated by encoding the operation of the SCAN enable signal (scan_en) using a combination of the desired signal (extract) and the MASK signal (MASK).

Table II below indicates proposed encoding of the SCAN enable signal (scan_en) within the desired signal (extract) and the MASK signal (MASK).

SCAN_IN	EXPECT	MASK
			SSSSSSSS	EEEEEEEE	00000000
SSSSSSSS	EXEEXEEE	01001000
			SSSSSSSS	11111111	11111111
SSSSSSSS	00000000	11111111

Table II

The first two rows of Table II are as in Table I. But the third row of table I is split into two different classifications IN the third and fourth rows of table II, corresponding to the case where all SCAN IN signals (scan_in) are masked.

In the third row of table II, the desired signal (extract) of all scan chains is set to a high logic level '1', and the MASK signal (MASK) is set to a high logic level '1'. In the fourth row of table II, the desired signal (extract) of all scan chains is set to a high logic level '0', and the MASK signal (MASK) is set to a high logic level '1'.

In an embodiment, setting the desired signal (extract) and the MASK signal (MASK) to a high logic level '1' is decoded with the SCAN enable signal (scan_en) at a low logic level '0', which indicates the capture phase. In an embodiment, setting the desired signal (extract) to a low logic level '0' and setting the MASK signal (MASK) to a high logic level (1) is decoded with the SCAN enable signal (scan_en) at a high logic level '1', which indicates a loading phase/unloading phase.

In an embodiment, setting the desired signal (extract) and the MASK signal (MASK) to a high logic level '1' is decoded as the SCAN enable signal (scan_en) to be at a high logic level '1', which indicates a loading phase/unloading phase. In an embodiment, setting the desired signal (extract) to a low logic level '0' and setting the MASK signal (MASK) to a low logic level '0' is decoded with the SCAN enable signal (scan_en) at a high logic level '1', which indicates a capture phase.

Thus, by selectively assigning a state to a desired signal (EXPECT) when a MASK signal (MASK) is asserted (asserted), either a capture phase or a load/unload phase may be indicated to the scan chain without requiring a separate Scan Enable (SE) pin.

Fig. 3 illustrates a block diagram of an embodiment logic 300 that may be implemented to decode a desired signal (extract) and a masking signal (MASK) to determine whether a phase corresponds to capture or load/unload. Logic circuit 300 includes a first AND gate 302, a second AND gate 304, AND a NAND gate 306, which may or may not be arranged as shown.

The first AND gate 302 is an N-input AND gate, where N is an integer greater than 1. The value of N corresponds to the number of scan chains tested by the on-chip comparator circuit 200 (i.e., N equals the number of scan chains tested minus 1). For example, if the number of scan chains tested by the on-chip comparator circuit 200 is 8, then N equals 7. Each input of the N-input AND gate of the first AND gate 302 is coupled to a desired input of a corresponding scan chain. The first AND gate 302 is configured to output a high logic level only in response to the desired value being equal to the high logic level. If any of the input signals of the first AND gate 302 is a low logic level, then the output of the first AND gate 302 is also a low logic level.

The second AND gate 304 is an N-input AND gate, where N is an integer greater than 1. The value of N corresponds to the number of scan chains tested by the on-chip comparator circuit 200. For example, if the number of scan chains tested by the on-chip comparator circuit 200 is 8, then N equals 8. Each input of the N-input AND gate of the second AND gate 304 is coupled to a mask input of a corresponding scan chain. The second AND gate 304 is configured to output a high logic level only in response to all masking values being equal to the high logic level. If any of the input signals of the second AND gate 304 is a low logic level, the second AND gate will 304 the output to a low logic level.

The outputs of the first AND gate 302 AND the second AND gate 304 are coupled to inputs of the NAND gate 306, respectively. The output of NAND gate 306 is a low logic level in response to (i) all desired values being equal to a high logic level and (ii) all masking values being equal to a high logic level. Conversely, the output of NAND gate 306 is a high logic level in response to (i) all desired values being equal to a low logic level and (ii) all masking values being equal to a high logic level. The output of NAND gate 306 is provided as a SCAN enable signal (SCAN_EN), for example, of SCAN chain 100.

It should be appreciated that logic circuit 300 may be implemented using other logic gates. For example, the first AND gate 302 may be implemented using a cascade of two input AND gates (instead of an N-input AND gate). Thus, the arrangement of logic gates may vary as long as the output of logic circuit 300 provides (i) a low logic level when the desired signal (EXPECT) and the masking signal (MASK) are at a high logic level on all input pins, and (ii) a high logic level when the desired signal (EXPECT) is at a low logic level on all input pins and when the masking signal (MASK) is at a high logic level on all input pins.

Fig. 4 illustrates a block diagram of an embodiment circuit 400 configured to identify a shift stage and a capture stage. In an embodiment, circuit 400 includes a Finite State Machine (FSM) 402 coupled to a shift counter circuit 404 and a capture counter circuit, which may or may not be arranged as shown. The circuit 400 may include additional components not shown.

FSM circuit 402 has two states. In the first state 408, the output of FSM circuit 402 is a SCAN enable signal (SCAN_EN) having a high logic level. In the second state 410, the output of FSM circuit 402 is a SCAN enable signal (SCAN_EN) with a low logic level. The shift counter circuit 404 and capture counter circuit 406 use a handshake feature (HANDSHAKING FEATURE) to control the SCAN enable signal (scan_en) by counting down from the preloaded counter values and signaling the end of the counter to the FSM circuit 402.

In an embodiment, the shift counter circuit 404 is preset with a shift cycle number for each test mode. Instead, capture counter circuit 406 is responsible for determining the required capture period. The two counter circuits, shift counter circuit 404 and capture counter circuit 406, cooperate through a handshake mechanism to manage the SCAN enable signal (SCAN _ EN). Each time a scanning process is initiated, the shift counter circuit 404 and the capture counter circuit 406 are preloaded with initial values. Thus, the counter counts these specified preload cycles, which prompts them to output a binary 0 or 1.

During the load/unload phase, the SCAN enable signal (scan_en) remains at a high logic level while the shift counter circuit 404 counts to a pre-load number. When the shift counter circuit 404 reaches the pre-load number, the SCAN enable signal (scan_en) transitions from a high logic level to a low logic level to begin the capture phase. The capture counter circuit 406 counts to a pre-load number and the SCAN enable signal (scan_en) remains at a low logic level during this period. When the capture counter circuit 406 reaches the preload number, the SCAN enable signal (scan_en) transitions from low logic to high logic. The process then repeats at the next load/unload stage.

For example, if the SCAN chain length is N, the shift counter circuit 404 will hold the SCAN enable signal (SCAN_EN) at a high logic level for N cycles during the shift (i.e., load/unload) phase, and then switch it to a low logic level. At the same time, capture counter circuit 406 will ensure that the SCAN enable signal (scan_en) remains at a low logic level during the capture phase for M cycles and then switches to a high logic level again. When each counter reaches its preset limit, it switches the state of the SCAN enable signal (scan_en). The test pattern set defines a certain number M and N and can be directly loaded into the counter as these values are known in advance. The JTAG interface may be used as a pipeline to input these counter values.

FSM circuit 402 begins with a first state 408 during the shift phase, which causes shift counter circuit 404 to count down or up N cycles in shift counter circuit 404 preloaded into the test mode. When FSM circuit 402 receives a signal from shift counter circuit 404 indicating the passage of N cycles, FSM circuit 402 transitions to second state 410 which causes capture counter circuit 406 to count down or up the M cycles for the test mode preloaded into capture counter circuit 406. When FSM circuit 402 receives a signal from capture counter circuit 406 indicating the passage of M cycles, FSM circuit 402 transitions back to first state 408 and the process repeats.

Fig. 5 illustrates a block diagram of an embodiment on-chip comparator circuit 500. Reference is made to an on-chip comparator circuit disclosed in U.S. patent No. 11,782,092 ("Jain"), the entire contents of which are incorporated herein by reference.

In an embodiment, jain discloses an efficient test data communication and processing method to facilitate on-chip testing, potentially reducing pin counts required for testing by combining signals and selectively comparing or masking test data as needed.

The process involves the digital circuit receiving multiple chains of test data (N scan-in chains) from off-chip devices and using the data to perform a test to generate a result. The combined signal containing the desired test results and masking instructions is sent to fewer pins (X pins) on the chip than the number of test chains. The combined signal is decoded into individual outputs that match each test chain and then compared to the actual test results using a comparator or masked as indicated.

The method is improved to include decompressing scan-in chains, serially loading test registers with data derived from the chains, storing test results in the test registers, and compressing the test results into N output chains. Furthermore, it is also provided that an X calculation based on the number of test chains is output for comparison results using a single bit, and the comparison results are stored on the chip and output after a set number of comparisons.

The digital circuit includes input pins for receiving test data, test registers, decoding logic for combining signals, and on-chip comparators for comparing and masking actions. Additional components include logic for decompressing and compressing test data, memory for storing comparison results, and outputs for relaying the results, which may consist of a single bit.

The on-chip comparator circuit 500 may include digital circuitry 502 or electronics. As will be appreciated, it may be advantageous to perform various functional, performance, quality, or stress tests on the digital circuit 502. Off-chip test equipment 550 (or off-device) may be used for testing, such as Automated Test Equipment (ATE) using, for example, input pins. The first input pin 504 may receive a first scan input chain. As will be appreciated, various embodiments may include more input pins. Additional input pins may receive additional scan input chains from off-chip test equipment 550. The more pins that are used to input data, the more scan-in chains that can be provided, the shorter the scan-in chain length can be, and faster data can be input.

The digital circuit 502 may include a clock input 506 for receiving a clock signal. The clock signal may be received from off-chip test equipment 550. The scan-in chain received at the input may be in compressed form. The decompression logic may expand the data signal received from the input pin. The number of internal data streams that may be extracted from the data signals received from the off-chip test equipment may depend on the number of pins available for transmitting data.

Data received through the input pins may be provided to test registers on digital circuit 502. For example, the first test register 508 may receive a segment of scan-in data. Various embodiments may include a different number of test registers for receiving a different number of scan input chains. Multiple test registers may be required per scan-in chain, as the decompression logic may expand each scan-in chain. The number of scan-in chains available may depend on the number of pins available to receive data from off-chip test equipment, such as ATE.

The first test register 508 may include a flip-flop for storing the received data. A different number of flip-flops may be used in different embodiments. The number of flip-flops of the test register may depend on the length of the scan-in chain.

The data may be serially loaded into the test registers. One bit of data may be loaded into each test register every cycle of the clock signal (e.g., the clock signal received at clock input 506). In embodiments with multiple test registers, each register may be serially loaded in parallel. For example, in an embodiment having 1000 test registers, each of the 1000 test registers may be loaded with one bit of data on a first cycle. Additional bits may be loaded and shifted each time a shift operation is scanned. Taking the first test register as an example, the first periodic data may be loaded into a first flip-flop 508A of the first test register 508. In a second period, the data may be shifted to a second flip-flop. The data may remain shifted until the nth flip-flop 508B of the first test register is filled. Additional test registers may also be loaded simultaneously in the same manner.

After the test data is loaded into the test registers, the data stored in the test registers may be used to perform different tests on the digital circuit 502. For example, the data may be used to test for stuck-at faults (stuck-at faults) in internal logic circuitry. Data from the test registers may be carried to other portions of digital circuit 502 using internal logic 503. This may be performed using scan load, unload, and capture operations.

The test register may include input and output shift patterns for serially shifting and outputting data. The test register may also include parallel input and parallel output modes for loading data into or from all flip-flops of the test register in parallel. After being loaded with data from off-chip test equipment (such as ATE), data from the test registers may output data from the flip-flops in parallel to perform test operations. When the test is complete, the results may be loaded into a test register. Test result data may be loaded in parallel into the test registers.

In an embodiment, the digital circuit 502 may include a comparator circuit 510. The comparator circuit 510 may be used to compare the expected test result of the test operation with the actual test result. The comparator circuit 510 may be in communication with a test register, such as a first test register and any additional test registers, to receive test result data from the test registers after the test result data is loaded into the test registers.

In various embodiments, the compressor logic may compress the data from the test registers before it is provided to the comparator circuit 510. Thus, the comparator circuit 510 may receive a scanout chain. The test registers may operate in a shift mode to serially output test results to the compression logic and then to the comparator circuit 510.

The comparator circuit 510 may receive the desired test results from the off-chip test equipment. There may be situations where it is not desirable to compare one or more data bits. Masking comparisons may be required when there is some uncertainty in the captured data of the relevant period or the data may be invalid for a number of reasons. The time anomaly provides one possible example of this.

The data input from off-chip test equipment (such as ATE) for comparison with test results may include one of three states, a high state, a low state, or a masked state. As will be readily appreciated, more than one binary pin is required to carry the information of the three states of each scan chain.

Taking the three scan chain embodiment as an example, each of the three scan chains may include a high or low state depending on the desired result or masking state. The status may be determined by a signal received from an off-chip test device. The signals of the three-state scan chains cannot be carried on the three pins in one cycle. The use of two pins (i.e., six pins) for each scan chain consumes pin resources that can be used to load scan-in data and speed up test time. By encoding the desired result data with masking data on the shared pins, the number of pins required to carry the three states can be reduced.

For example, three scan chains with three possible states yields 27 possible combinations for the three scan chains. This data may be transmitted using the combined expected test results and masking instruction signals using only five pins (instead of six). The decoding logic may then extract the appropriate data or masking signal. And, the additional pins may be used for other purposes. The more scan chains, the more advantageous this approach is, as more pins can be saved for other uses.

Digital circuit 502 may include an input pin 512 and an input pin 514. The desired test results may be loaded onto digital circuit 502 from input pin 512. In an embodiment, additional input and masking pins may be used to input the combined desired test results and masking instruction signals.

For example, five pins may be used to receive the combined desired test results and masking instruction signals. The combined expected test results and masking instruction signals may be provided to decode logic 516. When the desired test results are not masked, the decoded desired results may be provided to comparator circuit 510 for comparison with actual test results. As will be appreciated, masking may be achieved by converting the received data to a constant value using AND/OR gating.

The comparison result may be output at output port 518. Using comparator circuit 510 on digital circuit 502 to perform the comparison of the desired result with the actual test result may reduce the number of output pins required to output the data. This is accomplished by using input pins to transfer desired test result data onto digital circuitry 502, rather than using output pins to transfer actual results to off-chip test equipment such as ATE.

For example, results from 20 (or more) scan chains may be output by a single output port instead of 20 (or more) output ports. The switching takes advantage of the speed of the input pins relative to the output pins, improving overall test time speed. Transmitting data on the shared pins using the combined desired test results and masking command signals may free up additional pins instead of having dedicated pins for masking and desired test results.

Fig. 6 illustrates a block diagram of an embodiment comparator circuit 600, which may be implemented as comparator circuit 510. Comparator circuit 600 includes an input 602 for receiving a test data result. This may be received directly from the test register. Test data results may be received from compression logic. The number of inputs of the comparator circuit 600 for receiving test data results may correspond to the number of scan chains being compared.

Comparator circuit 600 includes an input 604 for receiving the decoded expected test result. This may result from the decode logic 516. Comparator circuit 600 may include additional inputs for receiving the decoded desired result and a masking indication for additional comparisons (scan chains).

The test result received at input 602 and the desired result received at input 604 may be provided to XOR gate 608. The mask indicator received at input 606 may be provided to AND gate 610 along with the output of XOR gate 608.

Comparator circuit 600 may include additional XOR gates for receiving the desired test result AND the actual test result from additional scan chains, AND additional AND gates for receiving additional masking inputs. In various embodiments, the results may be aggregated, for example, using an OR gate 612. Input 611 may carry the comparison result from the first scan chain. Input 613 may carry the comparison result from the nth scan chain. This may allow the output of OR gate 612 to be asserted if the expected result from any scan chain deviates from the actual test result. The output of OR gate 612 may be provided to flip-flop 610A.

In an embodiment, the output of flip-flop 610A may be fed back to OR gate 612 such that when a deviation is detected, the output may be held until the flip-flop is reset. This allows tracking of all results by a single trigger.

FIG. 7 illustrates an example table 700 that maps five binary input states to data having one of three states. A typical three scan chain design includes three input pins and three output pins (i.e., six pins total) with 27 states (i.e., 3 ³ =27). The scan architecture proposed using the circuits in fig. 5 and 6 provides a code for generating 27 valid states using five pins, because the on-chip decode logic extracts the correct masking and compares the bits of each scan chain.

Thus, a three scan chain design using the circuits in fig. 5 and 6 is implemented using three scan input channels and five scan data channels configured as eight input pins. The encoding and decoding of each cycle is performed without cross-cycle interference.

The scan out values of table 700 may correspond to decoded outputs from decode logic 516 configured for a design having three scan chains.

For example, SO ₀ of table 700 may correspond to a first decoded output of decode logic 516, SO ₁ of table 700 may correspond to a second decoded output of decode logic 516, and SO ₂ of table 700 may correspond to a third decoded output of decode logic 516.

For ease of illustration, '0' may correspond to a low state, '1' to a high state, and 'M' to a masking state for a desired test result. The cells of the scan pins in table 700 may correspond to the input pins of a digital circuit.

For example, RSI ₀ may correspond to a first data input pin, RSI ₁ may correspond to a second data input pin, RSI ₂ may correspond to a third data input pin, RSI ₃ may correspond to a fourth data input pin, and RSI ₄ may correspond to a fifth input pin.

All 27 possible states of the decoded output may correspond to one of the 32 possible states allowed by the five input pins. Various embodiments may use more input pins to provide desired results and masking instructions for more test chains. The number of pins used to encode the combined desired test result and masking instruction signal may be described by the following equation input pin = log ₂(3^S). The input pins refer to the number of pins for receiving the combined desired test result and masking instruction signal, and S refers to the number of three-state outputs from the decode logic 516, which may be equal to the number of scanout chains of test results received from the comparator circuit 600.

In an embodiment, more than one output pin may be used to carry decoded output data, which may include one of three states. And, the function ceiling maps the value to a minimum integer greater than or equal to.

For example, when=4.7, ceiling is equal to 5. Thus, the number of input pins may depend on the number of three-state outputs required. Using the above equation, 16 input pins may be used to receive the combined desired test result and masking instruction signal for 10 scan chains. Since the exemplary three scan chain design requires only 27 states, the 32 states described above (i.e., 2 ⁵ available states) using five input pins result in five unused states.

IN the case of the single SCAN chain of fig. 5, the number of pins at the input side increases from two pins (i.e., scan_in and scan_out) to three pins. Despite the increased pin count, a significant improvement in frequency shifting is achieved by repositioning all components to the input side of the circuit. This configuration takes advantage of the faster performance of the SCAN _ IN process compared to SCAN _ OUT, thereby improving the overall efficiency and speed of the scanning operation.

There are two different states of the 'scan enable' function in the scan chain design. The first state or state 1 is active during a shift phase, which is the interval in which scan data is fully loaded into the system. Conversely, a second state or state 0 indicates that the 'scan in/out' pin is in an inactive state when not engaged in data transfer.

Referring to fig. 7, it can be elucidated that any point from state 0 to state 26 represents a shift window. During this time, the decode logic 516 decodes the 'scan enable' signal to a logic level high. This is an active shift of data in the scan chain. The sequence then proceeds to five states, specifically from state 27 to state 31, previously designated as unused or idle in the scan operation.

In an embodiment, the present disclosure suggests reusing one of these idle states (e.g., state 27) as an indicator of the capture window. This adaptation will be decoded by the decode logic 516, during which state the 'scan enable' signal is represented as a logic level low. With this strategy, five pins involved in loading the "scan in" data can be used simultaneously to extract the 'scan enable' signal. The main benefit of this configuration is that it successfully eliminates the need for dedicated pins dedicated to 'scan enable', simplifying the design and potentially reducing the associated costs.

More generally, since 2 ^N states are never multiples of three ('0' state, '1' state, and 'M' state), the proposed decoding framework necessarily results in a few unused states.

Fig. 8 illustrates a flow chart of an embodiment method 800. The method 800 may be implemented using, for example, an on-chip comparator circuit 200 coupled to the scan chain 100. The method 800 is implemented without an independent scan enable signal externally provided to the digital circuit under test by the test equipment. In an embodiment, an Automatic Test Pattern Generation (ATPG) tool runs tests on digital circuits.

In step 802, a capture phase or a load/unload phase is selectively indicated to the scan chain based on the encoding in the desired signal and the masking signal. In an embodiment, encoding a high logic level in the desired signal and the masking signal indicates a load phase/an unload phase, and encoding a low logic level in the desired signal and a high logic level in the masking signal indicates a capture phase. In an embodiment, the scan chain is tested over a plurality of periods determined by the test protocol, the states of the desired signal and the masking signal inputs being variably set during each period according to the test protocol.

At step 804, a scan out signal is received from a scan chain at a scan input of an on-chip comparator circuit.

In step 806, the scan input signal is compared to the desired signal using an XOR gate to generate a comparison result. In an embodiment, when the scan out signal and the desired signal are different, a difference is determined, which is indicated by a high logic level result of the XOR gate.

At step 808, the selected bits of the comparison result are masked using an AND gate having an inverting input based on the masking signal. In an embodiment, when both inputs of the AND gate indicate a mismatch, the difference is passed to the OR gate, with one of the inputs being inverted by the masking signal.

In step 810, the differences in the OR gate are accumulated and stored in a flip-flop coupled to the OR gate. Accumulating includes maintaining a high logic level at the output of the OR gate if any discrepancies were previously stored in the flip-flop.

In step 812, an error condition is read from the trigger output to determine the function of the digital circuit. In an embodiment, an Internal Joint Test Action Group (IJTAG) interface is used to read out error states from the flip-flops.

Fig. 9 illustrates a flow chart of an embodiment method 900. Method 900 may be implemented using, for example, circuit 400 coupled to scan chain 100. The method 900 is implemented without an independent scan enable signal externally provided to the digital circuit under test by the test equipment. The method is repeated for a number of iterations corresponding to different segments of the test pattern. In an embodiment, an Automatic Test Pattern Generation (ATPG) tool runs tests on digital circuits.

At step 902, a number of shift cycles corresponding to a test pattern are preloaded into a shift counter circuit. In an embodiment, the preloaded shift periods are defined based on a set of test patterns and loaded into the shift counter circuit using the JTAG interface.

At step 904, a number of capture cycles corresponding to the test pattern are preloaded into the capture counter circuit. In an embodiment, the preloaded capture periods are defined based on a set of test patterns and loaded into the capture counter circuit using a JTAG interface.

At step 906, a load/unload phase is initiated by the finite state machine circuit holding an internally generated scan enable signal at a high logic level, during which a shift counter circuit counts the number of shift cycles preloaded. In an embodiment, the shift counter circuit implements a count up or down mechanism depending on the test pattern details (specifics).

At step 908, after counting by the shift counter circuit, the internally generated scan enable signal is transitioned to a low logic level. The transition corresponds to the acquisition phase being initiated. In an embodiment, the FSM circuit receives a count end signal from the shift counter circuit that transitions the FSM circuit from a first state corresponding to the load phase/unload phase to a second state corresponding to the capture phase.

At step 910, the internally generated scan enable signal is held at a low logic level while the capture counter circuit counts the number of capture cycles preloaded. In an embodiment, the capture counter circuit implements a count up or down mechanism depending on the test pattern details.

At step 912, after the count by the capture counter circuit is complete, the internally generated scan enable signal is transitioned to a high logic level to initiate a subsequent load/unload phase. In an embodiment, the FSM circuit receives a count end signal from the capture counter circuit that transitions the FSM circuit from the second state to the first state.

In an embodiment, each transition of the internally generated scan enable signal corresponds to a switch between two states in the FSM circuit. In an embodiment, the shift counter and capture counter circuits employ a handshake feature to signal the FSM circuit that the count is complete to control the logic level transitions of the internally generated scan enable signal. In an embodiment, steps 902 through 912 are repeated for each test pattern in a series of test patterns designed to verify the functionality of the digital circuit.

Fig. 10 illustrates a flow chart of an embodiment method 1000. The method 1000 may be implemented using, for example, an on-chip comparator circuit 500 coupled to the scan chain 100. The method 1000 is implemented without an independent scan enable signal externally provided to the digital circuit under test by the test equipment. In an embodiment, an Automatic Test Pattern Generation (ATPG) tool runs tests on digital circuits.

At step 1002, a first pin assignment having N input pins and R merged input pins is specified. N and R are integers, N corresponding to the number of input pins for carrying scan-in chain test data, and R corresponding to the number of input pins for carrying combined desired test results and masking instruction signals. In embodiments, R is equal to or greater than log ₂(3^N).

At step 1004, a second pin assignment having N input pins and M output pins is specified. M is an integer and corresponds to the number of output pins for carrying scanout chain test data. In an embodiment, scanout chain test data is encoded from M pins and the encoding is mapped to R pin test data.

In step 1006, an N by M codec is generated. In an embodiment, pins of the digital circuit are configured in an N by M diagnostic mode to perform testing of the digital circuit.

In step 1008, an N by M codec is integrated and a scan chain is inserted. The device registers are stitched into a plurality of scan chains and coupled between the compression circuitry and the decompression circuitry.

At step 1010, the internally generated scan enable signal is decoded using one of the 2 ^R states provided by the R merge input pins. The 3 ^N states are decoded outputs from the decode logic circuit.

It should be noted that all steps outlined in the flowcharts of method 800, method 900 and method 1000 are not necessarily required, but may be optional. Further, changing the arrangement of steps, removing one or more steps and path connections, and adding steps and path connections may be similarly considered.

In a first implementation form of the method according to the first aspect, the scan chain is tested in a plurality of cycles determined by the test protocol. The desired signal and the masking signal are variably set during each cycle according to the test protocol.

In a second implementation form of the method according to the first aspect or any of the previous implementation forms of the first aspect, the method further comprises generating the scan enable signal internally by the internal logic circuit to operate the scan chain based on the desired signal and the masking signal.

In a third implementation form of the method according to the first aspect or any of the previous implementation forms of the first aspect, encoding the high logic levels in the desired signal and the masking signal indicates a load phase/an unload phase. Encoding a low logic level in the desired signal and a high logic level in the masking signal indicates the acquisition phase.

In a fourth implementation form of the method according to the first aspect or any of the previous implementation forms of the first aspect, the method further comprises comparing the output of the unloading stage scan chain with an expected signal.

In a fifth implementation form of the method according to the first aspect or any of the preceding implementation forms of the first aspect, the encoding of the scan enable signals in the desired signal and the mask signal comprises determining logic levels of the desired signal and the mask signal and generating the scan enable signals internally based on the logic levels.

In a sixth implementation form of the method according to the first aspect or any of the previous implementation forms of the first aspect, the scan chain is coupled to an external test device. The method further includes providing the set of test patterns to the scan chain without an external scan enable signal.

In a first implementation form of the method according to the second aspect, the first number of shift periods is defined based on the test pattern set and loaded into the shift counter circuit using the JTAG interface.

In a second implementation form of the method according to the second aspect or any of the preceding implementation forms of the second aspect, the second number of capture cycles is defined based on the set of test patterns and loaded into the capture counter circuit using the JTAG interface.

In a third implementation form of the method according to the second aspect or any of the previous implementation forms of the second aspect, the method further comprises implementing a count up or down mechanism in the shift counter circuit according to the test pattern details.

In a fourth implementation form of the method according to the second aspect or any of the previous implementation forms of the second aspect, the method further comprises implementing a count up or down mechanism in the capture counter circuit according to the test mode details.

In a fifth implementation form of the method according to the second aspect or any of the previous implementation forms of the second aspect, each transition of the internally generated scan enable signal corresponds to a switch between two states in a Finite State Machine (FSM) circuit.

In a sixth implementation form of the method according to the second aspect or any of the previous implementation forms of the second aspect, the scan chain is coupled to an external test device, the method further comprising providing the set of test patterns to the scan chain without an external scan enable signal.

In a first implementation form of the method according to the third aspect, the method further comprises configuring pins of the digital circuit in an N by M diagnostic mode to perform the test on the digital circuit.

In a second implementation form of the method according to the third aspect or any of the previous implementation forms of the third aspect, an Automatic Test Pattern Generation (ATPG) tool runs tests on the digital circuit.

In a third implementation form of the method according to the third aspect or any of the preceding implementation forms of the third aspect, the method further comprises encoding the scanout chain test data from the M pins and mapping the encoding to R pin test data.

In a fourth implementation form of the method according to the third aspect or any of the previous implementation forms of the third aspect, R is equal to or greater than log ₂(3^N).

In a fifth implementation form of the method according to the third aspect or any of the previous implementation forms of the third aspect, the scan chain is coupled to an external test device, the method further comprising providing the set of test patterns to the scan chain without an external scan enable signal.

Although the specification has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. Like elements in the various figures are denoted by like reference numerals. Furthermore, the scope of the present disclosure is not intended to be limited to the particular embodiments described herein, since one of ordinary skill in the art will readily appreciate from the disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, may perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Accordingly, the specification and drawings should be considered a simple description of the disclosure as defined in the appended claims, and should cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the disclosure.

Claims

1. A method for testing using a scan chain without an independent scan enable pin, the method comprising:

selectively indicating a capture phase and a load phase/unload phase for the scan chain based on encoding of a scan enable signal in the desired signal and the mask signal;

loading test parameters into the scan chain during the loading phase/unloading phase;

operating the scan chain in a functional mode during the capture phase; and

An error signal is generated based on comparing an output of the scan chain during an unload phase with the expected signal, wherein the mask signal is used to mask the output of the scan chain during cycles with invalid results.

2 . The method of claim 1 , wherein the scan chain is tested over a plurality of cycles determined by a test protocol, wherein the desired signal and the mask signal are variably set according to the test protocol during each cycle.

3 . The method of claim 1 , further comprising internally generating, by an internal logic circuit, a scan enable signal to operate the scan chain based on the desired signal and the mask signal.

4. The method of claim 1 , wherein encoding a high logic level in the desired signal and the mask signal indicates the load phase/unload phase, and wherein encoding a low logic level in the desired signal and the high logic level in the mask signal indicates the capture phase.

5 . The method of claim 1 , further comprising comparing the output of the scan chain during the unload phase with the expected signal.

6. The method of claim 1 , wherein encoding the scan enable signal in the desired signal and the mask signal comprises determining a logic level of the desired signal and a logic level of the mask signal, and internally generating the scan enable signal based on the logic level of the desired signal and the logic level of the mask signal.

7 . The method of claim 1 , wherein the scan chain is coupled to external test equipment, the method further comprising providing a set of test patterns to the scan chain in the absence of an external scan enable signal.

8. A method for testing using a scan chain without independent scan enable pins, the method comprising:

preloading a first number of shift cycles into a shift counter circuit, the first number of shift cycles corresponding to a set of test patterns;

preloading a second number of capture cycles into a capture counter circuit, the second number of capture cycles corresponding to the set of test patterns;

initiating a load phase/unload phase of the test by holding an internally generated scan enable signal at a high logic level, wherein the shift counter circuit counts the preloaded number of shift cycles;

responsive to completion of the preload count by the shift counter circuit, transitioning the internally generated scan enable signal to a logic level, wherein the transition initiates a capture phase of the test; and

In response to completion of the preload count by the capture counter circuit, a subsequent load phase/unload phase of the test is initiated by transitioning the internally generated scan enable signal to the high logic level.

9. The method of claim 8, wherein the first number of shift cycles is defined based on the test pattern set and loaded into the shift counter circuit using a JTAG interface.

10. The method of claim 8, wherein the second number of capture cycles is defined based on the test pattern set and is loaded into the capture counter circuit using a JTAG interface.

11. The method of claim 8, further comprising implementing an up- or down-counting mechanism in the shift counter circuit according to the test mode details.

12. The method of claim 8, further comprising implementing an up or down counting mechanism in the capture counter circuit according to the test mode details.

13. The method of claim 8, wherein each transition of the internally generated scan enable signal corresponds to a switch between two states in a finite state machine (FSM) circuit.

14. The method of claim 8, wherein the scan chain is coupled to external test equipment, the method further comprising providing the set of test patterns to the scan chain in the absence of an external scan enable signal.

15. A method for testing a digital circuit using a scan chain without an independent scan enable pin, the method comprising:

specifying a first pin assignment having N input pins and R merged input pins, N and R being integers, N corresponding to the number of input pins for carrying scan input chain test data, and R corresponding to the number of input pins for carrying merged expected test result and mask instruction signals;

specifying a second pin assignment having N input pins and M output pins, where M is an integer and corresponds to the number of output pins used to carry scan output chain test data;

inserting a comparator circuit and a decoding logic circuit into the digital circuit;

Generate N by M codec;

integrating the N by M codec and inserting scan chains, wherein device registers are spliced into multiple scan chains and coupled between compression circuitry and decompression circuitry; and

An internally generated scan enable signal is decoded using one of 2 ^R states provided by the R binning input pins, where 3 ^N states are decoded outputs from the decode logic circuit.

16 . The method of claim 15 , further comprising configuring pins of the digital circuit to an N by M diagnostic mode to perform testing on the digital circuit.

17. The method of claim 15, wherein an automatic test pattern generation (ATPG) tool runs the test on the digital circuit.

18. The method of claim 15, further comprising encoding scan output chain test data from M pins and mapping the encoding into R pin test data.

The method of claim 15 , wherein R is equal to or greater than log ₂ ( 3 ^N ) .

20. The method of claim 15, wherein the scan chain is coupled to external test equipment, the method further comprising providing a set of test patterns to the scan chain in the absence of an external scan enable signal.