CN120653056A - Voltage stabilizing circuit - Google Patents
Voltage stabilizing circuitInfo
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- CN120653056A CN120653056A CN202511164619.0A CN202511164619A CN120653056A CN 120653056 A CN120653056 A CN 120653056A CN 202511164619 A CN202511164619 A CN 202511164619A CN 120653056 A CN120653056 A CN 120653056A
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Abstract
本发明实施例公开了一种稳压电路。该稳压电路包括：运放模块、比较模块、通道选择模块、输出控制模块和分压模块；通道选择模块选通任一输入端与输出端；比较模块根据分压模块的分压输出端的电压与参考电压输出第一控制信号至输出控制模块的控制端；运放模块根据分压模块的分压输出端的电压与参考电压输出第二控制信号至输出控制模块的控制端；输出控制模块根据第一控制信号或第二控制信号控制输出控制模块的输出端的输出电压。本发明实施例的技术方案，根据接入的负载电路的情况，通过通道选择模块切换稳压电路的工作模式，既解决了传统数字稳压电路电源抑制比差的问题，也改善了传统模拟稳压电路响应速度慢的不足，提高了稳压电路的性能。
The embodiment of the present invention discloses a voltage stabilizing circuit. The voltage stabilizing circuit includes: an operational amplifier module, a comparison module, a channel selection module, an output control module, and a voltage divider module; the channel selection module selects any input terminal and output terminal; the comparison module outputs a first control signal to the control terminal of the output control module according to the voltage of the voltage divider output terminal of the voltage divider module and a reference voltage; the operational amplifier module outputs a second control signal to the control terminal of the output control module according to the voltage of the voltage divider output terminal of the voltage divider module and a reference voltage; the output control module controls the output voltage of the output terminal of the output control module according to the first control signal or the second control signal. The technical solution of the embodiment of the present invention switches the working mode of the voltage stabilizing circuit through the channel selection module according to the situation of the connected load circuit, which not only solves the problem of poor power supply rejection ratio of traditional digital voltage stabilizing circuits, but also improves the disadvantage of slow response speed of traditional analog voltage stabilizing circuits, thereby improving the performance of the voltage stabilizing circuit.
Description
Technical Field
The present disclosure relates to integrated circuits, and particularly to a voltage stabilizing circuit.
Background
The low dropout linear regulator (Low Dropout Regulator, LDO) can convert a range of input voltages into a stable output voltage to power a load circuit. LDO is widely applied to large-scale digital systems such as System on Chip (SoC) because of the advantages of simple structure, low power consumption, small ripple, high integration and the like. In general, the load circuit is often a large-scale digital circuit, and along with different working states of the load circuit, different currents are required to be drawn from the voltage source at different moments, so that the LDO needs to have stronger driving capability and quick response capability to ensure stable operation of the system.
As the SoC integration level is higher and higher, the requirements on the power consumption and the area cost of the LDO are stricter, and the cost needs to be reduced while good stability is ensured. The traditional analog LDO has the defects that the PMOS type LDO is suitable for small current, small voltage difference and poor power supply rejection ratio (Power Supply Rejected Ratio, PSRR), and the NMOS type LDO is suitable for large current, good PSRR but large voltage difference and requires an additional charge pump circuit, so that design complexity and reliability risks are increased. Compared with the analog LDO scheme, the digital LDO has the advantages of small area of the adjusting tube, easy guarantee of stability, good process expansibility and the like, and becomes a research hot spot. However, the digital LDO regulates the output voltage discontinuously, which generates a large ripple. In addition, the power tube in the on state of the digital LDO works in a deep linear region to enable the equivalent resistance of the power tube to be extremely small, so that the overall PSRR performance is poor.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the invention provides a voltage stabilizing circuit for realizing high-performance voltage stabilization.
According to one aspect of the invention, a voltage stabilizing circuit is provided, which comprises an operational amplifier module, a comparison module, a channel selection module, an output control module and a voltage division module;
The first input end of the operational amplifier module is connected with the voltage division output end of the voltage division module, the second input end of the operational amplifier module is connected with the reference voltage end, the output end of the operational amplifier module is connected with the first input end of the channel selection module, the first input end of the comparison module is connected with the voltage division output end of the voltage division module, the second input end of the comparison module is connected with the reference voltage end, the output end of the comparison module is connected with the second input end of the channel selection module, the output end of the channel selection module is connected with the control end of the output control module, the input end of the output control module is connected with the input voltage end, the first end of the output control module is connected with the first end of the voltage division module, the second end of the output control module is connected with the bias current source, and the output end of the output control module is connected with the second end of the voltage division module.
The channel selection module is used for gating any input end and any output end, the comparison module is used for outputting a first control signal to the control end of the output control module according to the voltage of the voltage division output end of the voltage division module and the reference voltage, the operational amplifier module is used for outputting a second control signal to the control end of the output control module according to the voltage of the voltage division output end of the voltage division module and the reference voltage, and the output control module is used for controlling the output voltage of the output control module according to the first control signal or the second control signal.
Optionally, the voltage stabilizing circuit further includes a logic control module, an input end of the logic control module is connected with an output end of the output control module, an output end of the logic control module is connected with a control end of the channel selection module, and the logic control module is configured to generate a first gating signal or a second gating signal according to a magnitude relation between a voltage of the output end of the output control module and a target voltage.
Optionally, the logic control module includes a successive approximation logic device and a logic controller, where an input end of the successive approximation logic device is connected with an output end of the output control module, an output end of the successive approximation logic device is connected with an input end of the logic controller, an output end of the logic controller is connected with a control end of the channel selection module, the successive approximation logic device is configured to output a digital logic signal after comparing a voltage of the output end of the output control module with the target voltage, and the logic controller is configured to generate a first strobe signal or a second strobe signal according to the digital logic signal.
Optionally, the output control module comprises a first current mirror unit, a first transistor, a second current mirror unit, a second transistor and an output control unit, wherein the first end of the first current mirror unit is connected with the input voltage end, the second end of the first current mirror unit is connected with a reference current source, the third end of the first current mirror unit is connected with the first pole of the first transistor, the grid electrode of the first transistor is connected with the output end of the channel selection module, the second pole of the first transistor is connected with the first end of the second current mirror unit, the second end of the second current mirror unit is connected with the first end of the voltage dividing module, the third end of the second current mirror unit is connected with the second pole of the second transistor, the first pole of the second transistor is connected with the input voltage end, the grid electrode of the second transistor is respectively connected with the second pole of the second transistor and the first end of the output control unit, the second end of the output control unit is connected with the second end of the voltage dividing module.
Optionally, the first current mirror unit includes a third transistor and a fourth transistor, where a first pole of the third transistor is connected to the input voltage terminal, a second pole of the third transistor is connected to a gate of the third transistor, the second pole of the third transistor is further connected to a reference current source, the gate of the third transistor is further connected to a gate of the fourth transistor, a first pole of the fourth transistor is connected to the input voltage terminal, and a second pole of the fourth transistor is connected to the first pole of the first transistor.
Optionally, the second current mirror unit includes a fifth transistor and a sixth transistor, where a second pole of the fifth transistor is connected to a second pole of the first transistor, the second pole of the fifth transistor is further connected to a gate of the fifth transistor, the gate of the fifth transistor is further connected to a gate of the sixth transistor, the first pole of the fifth transistor and the first pole of the sixth transistor are both connected to the first end of the voltage division module, and the second pole of the sixth transistor is connected to the second pole of the second transistor.
Optionally, the output control unit includes a seventh transistor, an eighth transistor, and a ninth transistor, where a first pole of the seventh transistor and a first pole of the eighth transistor are both connected to the input voltage terminal, a gate of the seventh transistor is connected to a gate of the second transistor, a gate of the seventh transistor is further connected to a second pole of the ninth transistor, a gate of the eighth transistor is connected to the first pole of the ninth transistor, a second pole of the seventh transistor and a second pole of the eighth transistor are both connected to the second terminal of the voltage division module, and a gate of the ninth transistor is connected to an output terminal of the logic controller.
Optionally, the channel selection module includes a first gate switch and a second gate switch, a first end of the first gate switch is connected with an output end of the op-amp module, a control end of the first gate switch is connected with an output end of the logic controller, a second end of the first gate switch and a second end of the second gate switch are both connected with a control end of the output control module, a first end of the second gate switch is connected with an output end of the comparison module, and a control end of the second gate switch is connected with an output end of the logic controller.
Optionally, the operational amplifier module includes an operational amplifier, a first input end of the operational amplifier is connected with a voltage division output end of the voltage division module, a second input end of the operational amplifier is connected with the reference voltage end, and an output end of the operational amplifier is connected with a first end of the first gating switch.
Optionally, the voltage dividing module includes a first resistor and a second resistor, a first end of the first resistor is connected with the output end of the output control module, a second end of the first resistor is connected with a first end of the second resistor, and a second end of the second resistor is connected with the first end of the output control module.
According to the technical scheme of the embodiment of the invention, the operational amplifier module and the comparison module can output control signals according to the voltage of the voltage division output end of the voltage division module and the magnitude of the reference voltage, and the current of the input voltage end flowing to the output end of the voltage stabilizing circuit is controlled, so that the output voltage of the voltage stabilizing circuit is regulated to be stable. The channel selection module may select an op amp module or a comparison module. The voltage stabilizing circuit when the operational amplifier module is selected is similar to a traditional analog voltage stabilizing circuit, and the output voltage of the voltage stabilizing circuit is maintained to be near the target voltage by controlling the current flowing to the output end of the voltage stabilizing circuit from the input voltage end. The comparison module can realize the rapid adjustment of the output voltage of the voltage stabilizing circuit. The channel selection module can switch the working mode of the voltage stabilizing circuit, and select a switching mode in light load, so that output ripple waves can be reduced. Under the heavy load condition, a mixed voltage stabilizing mode can be adopted, and a switching mode is selected in the power-on process, so that the output voltage rises rapidly to reach the vicinity of a target value, and can be switched into a linear mode after being stabilized. According to the technical scheme of the embodiment of the invention, the working mode of the voltage stabilizing circuit is switched through the channel selection module according to the condition of the accessed load circuit, so that the problem of poor power supply rejection ratio of the traditional digital voltage stabilizing circuit is solved, the defect of slow response speed of the traditional analog voltage stabilizing circuit is overcome, and the performance of the voltage stabilizing circuit is improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an analog LDO in the related art.
Fig. 2 is a schematic diagram of another structure of an analog LDO in the related art.
Fig. 3 is a schematic diagram of a digital LDO in the related art.
Fig. 4 is a schematic structural diagram of a voltage stabilizing circuit according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of another voltage stabilizing circuit according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a voltage stabilizing circuit according to another embodiment of the present invention.
Fig. 7 is a schematic circuit diagram of a voltage stabilizing circuit according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of signal variation in the operation of the voltage stabilizing circuit according to the embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 and fig. 2 are schematic diagrams of analog linear voltage stabilizing circuits in related art, and fig. 1 is a schematic diagram of a PMOS LDO in related art, where the PMOS LDO mainly includes a first operational amplifier EA1, a first voltage dividing resistor Rf1, a second voltage dividing resistor Rf2, a first capacitor C1 and a PMOS transistor MP1. The PMOS LDO adjusts the PMOS transistor MP1 according to the first divided voltage Vf1 and the first reference voltage Vref1 through the operational amplifier EA1, thereby adjusting the output voltage Vout1 of the PMOS LDO. The PMOS LDO is mainly applied to a small-current application scene, and has the characteristics of large output impedance, small voltage difference between input voltage VIN1 and output voltage Vout1, poor power supply rejection ratio (Power Supply Rejected Ratio, PSRR) performance and the like. Fig. 2 is a schematic diagram of an NMOS LDO in the related art, which mainly includes an operational amplifier EA2, a third voltage dividing resistor Rf3, a fourth voltage dividing resistor Rf4, a charge pump circuit (charge pump), a second capacitor C2, and an NMOS transistor MN1.Clk is a clock signal. The NMOS LDO adjusts the NMOS transistor MN1 according to the second divided voltage Vf2 and the second reference voltage Vref2 through the second operational amplifier EA2, thereby adjusting the output voltage Vout2 of the NMOS LDO. NNOS LDO is mainly applied to a large-current application scene, has small output impedance and good PSRR performance, but has the defects of large pressure difference between input voltage VIN2 and output voltage Vout2, more additional circuits, increased design difficulty, poor reliability and the like.
Fig. 3 shows a structure of a related art digital LDO, which mainly includes a comparator COMP, a clock module OSC, a digital control logic Digital Control Logic, a plurality of transistors MP2-MPn, a fifth dividing resistor Rf5, a sixth dividing resistor Rf6, and a third capacitor C3. The digital LDO adjusts the number of turns on the plurality of transistors MP2, MP3, MPn according to the comparison result of the third divided voltage Vf3 and the third reference voltage Vref3 by the comparator COMP and the clock module OSC and the digital control logic Digital Control Logic, thereby adjusting the output voltage Vout3 of the digital LDO. The digital control logic Digital Control Logic is typically a bi-directional shift register. The digital LDO realizes the conduction quantity of the regulating transistor by means of the clock module OSC and the bidirectional shift register. This approach may result in discontinuous control of the output voltage Vout3 of the digital LDO, and a larger ripple is generated in the output. In addition, the power tube in the on state of the digital LDO works in a deep linear region, and the equivalent resistance of the adjusting transistor in the region is very small, so that the PSRR of the whole digital LDO is very poor.
In view of this, fig. 4 is a schematic structural diagram of a voltage stabilizing circuit according to an embodiment of the present invention, which is suitable for a scenario with high requirements on output voltage precision, response speed or anti-interference performance, especially in applications with a wide load variation range, such as the fields of microprocessors, power supplies of communication devices, automotive electronics, industrial automation, etc. As shown in fig. 4, the voltage stabilizing circuit comprises an operational amplifier module 101, a comparison module 102, a channel selection module 103, an output control module 104 and a voltage division module 105;
The first input end of the operational amplifier module 101 is connected with the voltage division output end of the voltage division module 105, the second input end of the operational amplifier module 101 is connected with the reference voltage end, the output end of the operational amplifier module 101 is connected with the first input end of the channel selection module 103, the first input end of the comparison module 102 is connected with the voltage division output end of the voltage division module 105, the second input end of the comparison module 102 is connected with the reference voltage end, the output end of the comparison module 102 is connected with the second input end of the channel selection module 103, the output end of the channel selection module 103 is connected with the control end of the output control module 104, the input end of the output control module 104 is connected with the input voltage end VIN, the first end of the output control module 104 is connected with the first end of the voltage division module 105, the second end of the output control module 104 is connected with the bias current source Ib, and the output end of the output control module 104 is connected with the second end of the voltage division module 105;
The channel selection module 103 is used for gating any input end and any output end of the channel selection module, the comparison module 102 is used for outputting a first control signal to a control end of the output control module 104 according to the voltage Vf and the reference voltage Vref of the voltage division output end of the voltage division module 105, the operational amplifier module 101 is used for outputting a second control signal to the control end of the output control module 104 according to the voltage Vf and the reference voltage Vref of the voltage division output end of the voltage division module 105, and the output control module 104 is used for controlling the output voltage Vout of the output control module 104 according to the first control signal or the second control signal.
The voltage dividing module 105 may divide the output voltage Vout of the output control module 104 to obtain the voltage Vf of the divided output terminal. The output voltage of the output control module 104 is the output voltage of the voltage stabilizing circuit, where the output voltage of the output control module 104 and the output voltage of the voltage stabilizing circuit may be denoted by Vout. The reference voltage terminal provides a reference voltage. The reference voltage terminal is connected to a second input terminal of the op-amp block 101 and to a second input terminal of the comparison block 102. The operational amplifier module 101 may be an operational amplifier, and may continuously detect the voltage Vf of the divided output terminal and the reference voltage Vref, amplify the voltage difference according to the voltage difference between the two input terminals, and thereby generate the second control signal. The second control signal may be a continuous analog control signal. If the channel selection module 103 selects the operational amplifier module 101 to participate in the voltage stabilizing operation, the operation mode of the voltage stabilizing circuit may be referred to as a linear mode. The comparison module 102 may be a high-speed comparator, and may compare the voltage Vf of the divided output terminal with the reference voltage Vref and output a first control signal according to a magnitude relationship between the two input terminals. The first control signal may be a switch control signal, for example, may be 0 or 1. If the channel selection module 103 selects the comparison module 102 to participate in the voltage stabilizing operation, the operation mode of the voltage stabilizing circuit may be referred to as a switch mode. For example, when the external load is light, the switching mode may be selected. Under the light load condition, the output ripple wave can be reduced by adopting a switch mode, and the function of stable output is achieved. Under the heavy load condition, a mixed voltage stabilizing mode can be adopted, and a switching mode can be selected in the power-on process, so that the output voltage rapidly rises to reach the vicinity of a target value, and the output voltage can be switched into a linear mode after being stabilized. The mixed voltage stabilizing mode is adopted during heavy load, so that the problem of poor PSRR of the traditional digital LDO can be solved, and the stability of the voltage stabilizing circuit is improved.
The channel selection module 103 may be a multiplexer or a plurality of switches, and may selectively connect the output terminal of the op-amp module 101 or the output terminal of the comparison module 102 to the output terminal thereof, and transmit the control signal to the control terminal of the output control module 104. The channel selection module 103 may select a switching mode or a linear mode according to a magnitude relation between the output voltage Vout of the voltage regulator circuit and the target voltage. For example, when the output voltage Vout of the voltage regulator circuit is close to the target voltage, i.e., the difference between the output voltage Vout of the voltage regulator circuit and the target voltage is small, a linear mode may be selected, and the second control signal is output to the control terminal of the output control module 104. The output control module 104 may include a plurality of transistors. The current flowing from the input voltage terminal VIN to the output terminal of the voltage stabilizing circuit can be adjusted according to the control signal selected by the channel selection module 103, so as to adjust the output voltage Vout of the voltage stabilizing circuit to be stable.
Specifically, the voltage dividing module 105 may divide the output voltage Vout of the voltage stabilizing circuit to obtain the voltage Vf1 at the divided output terminal. The operational amplifier module 101 detects the voltage Vf1 at the divided output terminal and the reference voltage Vref, and outputs a second control signal. The comparison module 102 may also compare the voltage Vf1 at the divided output terminal with the reference voltage Vref, and output a first control signal. The channel selection module 103 selects and outputs the first control signal or the second control signal to transmit to the control end of the output control module 104 according to the magnitude relation between the output voltage Vout of the voltage stabilizing circuit and the target voltage. The output control module 104 may adjust the output voltage Vout of the voltage stabilizing circuit by linearly adjusting the turn-on level of the power device, similar to the conventional analog voltage stabilizing circuit, if it receives the second control signal from the operational amplifier module 101. The output control module 104 may adjust the output voltage Vout of the voltage regulator circuit by switching the power device fast if the first control signal from the comparison module 102 is received. The regulated output voltage Vout of the voltage stabilizing circuit is divided by the voltage dividing module 105 to obtain the voltage Vf of the divided output end, and the voltage Vf is compared with the reference voltage Vref to form a closed-loop negative feedback system. Whichever mode is selected, the objective is to maintain the output voltage Vout of the voltage regulator circuit near the target voltage.
According to the technical scheme provided by the embodiment of the invention, the operational amplifier module and the comparison module can output control signals according to the magnitude relation between the voltage of the voltage division output end of the voltage division module and the reference voltage, and the current of the input voltage end flowing to the output end of the voltage stabilizing circuit is controlled, so that the output voltage of the voltage stabilizing circuit is regulated to be stable. The channel selection module may select an op amp module or a comparison module. The voltage stabilizing circuit when the operational amplifier module is selected is similar to a traditional analog voltage stabilizing circuit, and the output voltage of the voltage stabilizing circuit is maintained to be near the target voltage by controlling the current flowing to the output end of the voltage stabilizing circuit from the input voltage end. The comparison module can realize the rapid adjustment of the output voltage of the voltage stabilizing circuit. The channel selection module can switch the working mode of the voltage stabilizing circuit, and select a switching mode in light load, so that output ripple waves can be reduced. Under the heavy load condition, a mixed voltage stabilizing mode can be adopted, and a switching mode is selected in the power-on process, so that the output voltage rises rapidly to reach the vicinity of a target value, and can be switched into a linear mode after being stabilized. According to the technical scheme of the embodiment of the invention, the working mode of the voltage stabilizing circuit is switched through the channel selection module according to the condition of the accessed load circuit, so that the problem of poor power supply rejection ratio of the traditional digital voltage stabilizing circuit is solved, the defect of slow response speed of the traditional analog voltage stabilizing circuit is overcome, and the performance of the voltage stabilizing circuit is improved.
Fig. 5 is a schematic diagram of another voltage stabilizing circuit according to an embodiment of the present invention, in some alternative embodiments of the present invention, the voltage stabilizing circuit further includes a logic control module 106, an input end of the logic control module 106 is connected to an output end of the output control module 104, an output end of the logic control module 106 is connected to a control end of the channel selection module 103, and the logic control module 106 is configured to generate a first strobe signal or a second strobe signal according to a magnitude relation between a voltage Vout at the output end of the output control module 104 and a target voltage.
Wherein an input of the logic control module 106 is connected to an output of the output control module 104, i.e. an output of the voltage stabilizing circuit. The logic control module 106 can directly monitor the output voltage Vout of the voltage regulator circuit, compare the output voltage Vout with the target voltage, and generate and output a corresponding strobe signal. The first strobe signal may indicate that the output of the select op amp block 101 is connected to the output of the channel select block 103. The second strobe signal may indicate that the output of the selection comparison module 102 is connected to the output of the channel selection module 103.
Specifically, the logic control module 106 may continuously monitor the output voltage Vout of the voltage regulator circuit and compare it with the target voltage. If the output voltage Vout of the voltage stabilizing circuit is close to the target voltage, i.e. the difference between the output voltage Vout of the voltage stabilizing circuit and the target voltage is small, the logic control module 106 generates a first strobe signal, and the channel selection module 103 connects the output terminal of the op amp module 101 to the control terminal of the output control module 104. The output voltage Vout of the voltage stabilizing circuit is maintained near the target voltage by controlling the magnitude of the current flowing from the input voltage end to the output end of the voltage stabilizing circuit through adjusting the state of the power tube in the linear region. If the output voltage Vout of the voltage regulator circuit is much smaller than the target voltage, i.e. the difference between the output voltage Vout of the voltage regulator circuit and the target voltage is large, the logic control module 106 generates a second strobe signal, and the channel selection module 103 connects the output of the comparison module 102 to the control terminal of the output control module 104. The output of the comparison module 102 is usually high or low, so as to rapidly boost the output voltage Vout of the voltage stabilizing circuit.
In some alternative embodiments of the present invention, with continued reference to fig. 5, the logic control module 106 includes a successive approximation logic 1061 and a logic controller 1062, the input end of the successive approximation logic 1061 is connected to the output end of the output control module 104, the output end of the successive approximation logic 1061 is connected to the input end of the logic controller 1062, the output end of the logic controller 1062 is connected to the control end of the channel selection module 103, the successive approximation logic 1061 is configured to output a digital logic signal after comparing the voltage at the output end of the output control module 104 with the target voltage, and the logic controller 1062 is configured to generate the first strobe signal or the second strobe signal according to the digital logic signal.
The successive approximation logic 1061 may digitally evaluate the deviation degree of the output voltage Vout of the voltage regulator circuit with respect to the target voltage by adopting a successive approximation method. The digital logic signal output by the successive approximation logic 1061 may be a digital quantity representing an evaluation of the output voltage Vout of the voltage regulator circuit. The logic controller 1062 may output the first strobe signal or the second strobe signal to the control terminal of the channel selection module 103 based on the evaluation result of the successive approximation logic 1061.
Specifically, the successive approximation logic 1061 may continuously or periodically sample the output Vout of the voltage regulator circuit, convert the magnitude relationship between the output voltage Vout of the voltage regulator circuit and the target voltage into a digital logic signal through the successive approximation process, and output the digital logic signal to the logic controller 1062. The logic controller 1062 outputs a corresponding strobe signal to the control terminal of the channel selection module 103 according to the received digital logic signal. The channel selection module 103 connects the output end of the operational amplifier module 101 or the output end of the comparison module 102 to the control end of the output control module 104 according to the received gating signal, so as to adjust the output voltage Vout of the voltage stabilizing circuit. The adjusted successive approximation logic 1061 resamples to begin a new round of evaluation and selection.
In some alternative embodiments of the present invention, as shown in fig. 5, the output control module 104 includes a first current mirror unit 1041, a first transistor M1, a second current mirror unit 1042, a second transistor M2, and an output control unit 1043, wherein a first end of the first current mirror unit 1041 is connected to an input voltage terminal VIN, a second end of the first current mirror unit 1041 is connected to a reference current source Ib, a third end of the first current mirror unit 1041 is connected to a first pole of the first transistor M1, a gate of the first transistor M1 is connected to an output terminal of the channel selection module 103, a second pole of the first transistor M1 is connected to a first end of the second current mirror unit 1042, a second end of the second current mirror unit 1042 is connected to a first end of the voltage dividing module 105, a third end of the second current mirror unit 1042 is connected to a second pole of the second transistor M2, a first pole of the second transistor M2 is connected to the input voltage terminal VIN, and a gate of the second transistor M2 is connected to the second end of the second transistor 1043 and the output control unit 1043 is connected to the second end of the output control unit 105.
The first current mirror unit 1041 may be a POMS current mirror. The first current mirror unit 1041 mirrors the reference current Ib to the third terminal thereof, and provides the first transistor M1 with a static operating current. Here both the reference current source and the reference current are denoted Ib. The first transistor M1 may be a PMOS transistor. The first pole of the first transistor M1 may be a source and the second pole may be a drain. The gate of the first transistor M1 is connected to the output terminal of the channel selection module 103, and may transmit a current signal to the second current mirror unit 1042 according to the control signal of the channel selection module 103. The second current mirror unit 1042 may be an NMOS current mirror. The second current mirror unit 1042 may drive the second transistor M2 with the current signal transmitted by the first transistor M1. The second transistor M2 may be a PMOS transistor. The first pole of the second transistor M2 may be a source and the second pole may be a drain. The gate and drain of the second transistor M2 are shorted to operate in the saturation region. When a current flows through the second current mirror unit 1042, since the second transistor operates in the saturation region, the output control unit 1043 can be driven at the gate of the second transistor M2.
Fig. 6 is a schematic diagram of a voltage stabilizing circuit according to another embodiment of the present invention, in some alternative embodiments of the present invention, as shown in fig. 6, the first current mirror unit 1041 includes a third transistor M3 and a fourth transistor M4, a first pole of the third transistor M3 is connected to the input voltage terminal VIN, a second pole of the third transistor M3 is connected to a gate of the third transistor M3, a second pole of the third transistor M3 is further connected to the reference current source Ib, a gate of the third transistor M3 is further connected to a gate of the fourth transistor M4, a first pole of the fourth transistor M4 is connected to the input voltage terminal VIN, and a second pole of the fourth transistor M4 is connected to a first pole of the first transistor M1.
The third transistor M3 and the fourth transistor M4 may be PMOS transistors. The first poles of the third and fourth transistors M3 and M4 may be sources and the second poles may be drains. The first current mirror unit 1041 may be used to provide a current proportional to the bias current source Ib to the first transistor M1. The drain and gate of the third transistor M3 are shorted to operate in the saturation region. The reference current source Ib pulls current from the second pole of the third transistor M3, mirrored by the fourth transistor M4, and supplied to the first transistor M1. Here, the fourth transistor M4 may be set to have a size n times that of the third transistor M3, and when the first transistor M1 is operated in the switching mode, the current flowing through the first transistor M1 is equal to n×ib, and when the first transistor M1 is operated in the linear mode, the linear loop controls the operation state of the first transistor, and the current flowing through the first transistor M1 is equal to or less than n×ib.
In some alternative embodiments of the present invention, with continued reference to fig. 6, the second current mirror unit 1042 includes a fifth transistor M5 and a sixth transistor M6, the second pole of the fifth transistor M5 is connected to the second pole of the first transistor M1, the second pole of the fifth transistor M5 is also connected to the gate of the fifth transistor M5, the gate of the fifth transistor M5 is also connected to the gate of the sixth transistor M6, the first pole of the fifth transistor M5 and the first pole of the sixth transistor M6 are both connected to the first end of the voltage dividing module 105, and the second pole of the sixth transistor M6 is connected to the second pole of the second transistor M2.
The fifth transistor M5 and the sixth transistor M6 may be NMOS transistors. The first poles of the fifth and sixth transistors M5 and M6 may be sources and the second poles may be drains. The gate and the drain of the fifth transistor M5 are shorted to make the fifth transistor M5 work in a saturation region, and the current flowing through the fifth transistor M5 is the drain current of the first transistor M1, and the second transistor M2 is directly driven after being mirrored by the sixth transistor. Here, the fifth transistor M5 and the sixth transistor M6 may be provided to have the same size.
In some alternative embodiments of the present invention, with continued reference to fig. 6, the output control unit 1043 includes a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, wherein the first pole of the seventh transistor M7 and the first pole of the eighth transistor M8 are both connected to the input voltage terminal VIN, the gate of the seventh transistor M7 is connected to the gate of the second transistor M2, the gate of the seventh transistor M7 is also connected to the second pole of the ninth transistor M9, the gate of the eighth transistor M8 is connected to the first pole of the ninth transistor M9, the second pole of the seventh transistor M7 and the second pole of the eighth transistor M8 are both connected to the second terminal of the voltage dividing module 105, and the gate of the ninth transistor M9 is connected to the output terminal of the logic controller 1062.
The seventh transistor M7 and the eighth transistor may be PMOS transistors. The first poles of the seventh and eighth transistors M7 and M8 may be sources and the second poles may be drains. The gate of the seventh transistor M7 is connected to the gate of the second transistor M2, the gate of the second transistor M2 is shorted to the drain, and the seventh transistor M7 and the second transistor M2 may form a current mirror structure. The seventh transistor M7 may mirror the current flowing through the second transistor. The ninth transistor M9 may be a switching transistor, and controls whether the eighth transistor M8 is connected to the voltage stabilizing circuit. The gate of the ninth transistor M9 is connected to the output terminal of the logic controller 1062. The ninth transistor M9 may be turned on when the channel selection module selects the operational amplifier module 101. For example, when the output voltage Vout of the voltage stabilizing circuit is close to the target voltage, i.e. the difference between the output voltage Vout of the voltage stabilizing circuit and the target voltage is small, the logic control module 106 generates a first strobe signal, the channel selection module 103 connects the output terminal of the op amp module 101 to the control terminal of the output control module 104, at this time, the gate of the ninth transistor M9 receives the high level signal, the ninth transistor M9 is turned on, the eighth transistor M8 is connected to the voltage stabilizing circuit and controls the output voltage Vout of the voltage stabilizing circuit together with the seventh transistor M7, and when the output voltage Vout of the voltage stabilizing circuit is much smaller than the target voltage, i.e. the difference between the output voltage Vout of the voltage stabilizing circuit and the target voltage is large, the logic control module 106 generates a second strobe signal, and the channel selection module 103 connects the output of the comparison module 102 to the control terminal of the output control module 104. At this time, the gate of the ninth transistor M9 receives the low level signal, the ninth transistor M9 is not turned on, and at this time, the eighth transistor M8 is not connected to the voltage stabilizing circuit.
Fig. 7 is a schematic circuit diagram of a voltage stabilizing circuit according to an embodiment of the present invention, in some alternative embodiments of the present invention, as shown in fig. 7, the channel selection module 103 includes a first gate switch 1031 and a second gate switch 1032, a first end of the first gate switch 1031 is connected to an output end of the op amp module 101, a control end of the first gate switch 1031 is connected to an output end of the logic controller 1062, a second end of the first gate switch 1031 and a second end of the second gate switch 1032 are both connected to a control end of the output control module 104, a first end of the second gate switch 1032 is connected to an output end of the comparison module 102, and a control end of the second gate switch 1032 is connected to an output end of the logic controller 1062.
The first gating switch 1031 is used for controlling the output terminal of the operational amplifier module 101 to be connected to the control terminal of the output control module 104. The second gating switch 1032 is used to control the output of the comparison module 102 to be connected to the control terminal of the output control module 104. The gate signals may include a first gate switch control signal en_l and a second gate switch control signal en_s. The first gate signal may be a high level of the first gate switch control signal en_l and a low level of the second gate switch control signal en_s. The second gate signal may be a low level of the first gate switch control signal en_l and a high level of the second gate switch control signal en_s. For example, when the logic controller 1062 outputs the first strobe signal, the first strobe switch 1031 is turned on, the output terminal of the op amp module 101 is connected to the control terminal of the output control module 104, and the output voltage Vout of the voltage stabilizing circuit is adjusted by using the linear mode, and when the logic controller 1062 outputs the second strobe signal, the second strobe switch 1032 is turned on, the output terminal of the comparison module 102 is connected to the control terminal of the output control module 104, and the output voltage Vout of the voltage stabilizing circuit is adjusted by using the switch mode.
In some alternative embodiments of the present invention, the operational amplifier module 101 includes an operational amplifier EA, a first input terminal of the operational amplifier EA is connected to the divided voltage output terminal Vf of the voltage dividing module 105, a second input terminal of the operational amplifier EA is connected to the reference voltage terminal Vref, and an output terminal of the operational amplifier EA is connected to the first terminal of the first gate switch 1031.
The first input of the operational amplifier EA may be a non-inverting input and the second input may be an inverting input. The operational amplifier EA may continuously sample the voltage Vf at the divided output of the voltage dividing module 105 and send the voltage Vf to the non-inverting input of the operational amplifier EA, which may be a differential amplifier, and may detect a voltage difference between the two input terminals and amplify the voltage difference, thereby generating the second control signal. The second control signal may be a continuous analog control signal. The second control signal may regulate the output voltage Vout of the voltage regulator circuit in the linear voltage regulator mode. Similar to the operation mode of the conventional analog voltage stabilizing circuit, the magnitude of the current flowing through the first transistor M1 is controlled by the second control signal, so that the output voltage Vout of the voltage stabilizing circuit is maintained near the target voltage.
In some alternative embodiments of the present invention, the voltage dividing module 105 includes a first resistor R1 and a second resistor R2, where a first end of the first resistor R1 is connected to the output end of the output control module 104, a second end of the first resistor R1 is connected to a first end of the second resistor R2, and a second end of the second resistor R2 is connected to the first end of the output control module 104.
The connection point between the second end of the first resistor and the first end of the second resistor is the voltage division output end of the voltage division module 105. The voltage dividing module 105 may sample the output voltage Vout of the voltage stabilizing circuit, and then generate a voltage Vf at a divided output end, and the voltage Vf is respectively transmitted to the first input end of the op-amp module 101 and the first input end of the comparing module 102 for comparing with the reference voltage Vref.
Referring to fig. 7 and 8, fig. 8 shows the changes of the output voltage Vout, the reference voltage Vref, the voltage Vf at the divided output terminal, the first gate switch control signal en_l and the second gate switch control signal en_s of the voltage stabilizing circuit in the operation process of the voltage stabilizing circuit of the present invention. When the output voltage Vout of the voltage stabilizing circuit is much smaller than the target voltage, i.e. the difference between the output voltage Vout of the voltage stabilizing circuit and the target voltage is large, the successive approximation logic 1061 will output the second gating signal en_s according to the comparison between the output voltage Vout of the voltage stabilizing circuit and the target voltage, at this time, the second gating switch 1032 is turned on, and the comparison module 102 participates in the operation of the voltage stabilizing circuit. The comparison module 102 generates a first control signal according to the voltage Vf at the divided output end and compares the first control signal with the reference voltage Vf, and transmits the first control signal to the gate of the first transistor M1, so that the first transistor M1 is turned on, and finally flows through the seventh transistor M7 through the fifth transistor M5, the sixth transistor M6 and the second transistor M2, so that the seventh transistor M7 outputs an external current, and the output voltage Vout of the voltage stabilizing circuit is raised. When the output voltage Vout of the voltage stabilizing circuit approaches the target voltage, i.e. the difference between the output voltage Vout of the voltage stabilizing circuit and the target voltage is small, the successive approximation logic 1061 generates a first strobe signal according to the comparison between the output voltage Vout of the voltage stabilizing module and the target voltage, and the operational amplifier EA participates in the operation of the voltage stabilizing circuit. Similar to the conventional analog loop operation mode, the operational amplifier EA generates the second control signal according to the voltage Vf at the voltage dividing output end of the voltage dividing module and the reference voltage Vref, and transmits the second control signal to the gate of the first transistor M1, and the output voltage Vout of the voltage stabilizing circuit is maintained near the target voltage by controlling the magnitude of the current flowing through the first transistor M1.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
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| CN202511164619.0A CN120653056A (en) | 2025-08-20 | 2025-08-20 | Voltage stabilizing circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540542A (en) * | 2009-03-18 | 2009-09-23 | 浙江大学 | Single-inductor switch direct current voltage converter and 4-mode control method |
| US20140070778A1 (en) * | 2012-09-07 | 2014-03-13 | Seiko Instruments Inc. | Voltage regulator |
| CN119105601A (en) * | 2024-08-28 | 2024-12-10 | 深圳市国微电子有限公司 | A low voltage dropout linear regulator and control method |
| CN120045005A (en) * | 2023-11-24 | 2025-05-27 | 茂达电子股份有限公司 | Low dropout linear voltage regulator with output voltage switching circuit |
-
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- 2025-08-20 CN CN202511164619.0A patent/CN120653056A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101540542A (en) * | 2009-03-18 | 2009-09-23 | 浙江大学 | Single-inductor switch direct current voltage converter and 4-mode control method |
| US20140070778A1 (en) * | 2012-09-07 | 2014-03-13 | Seiko Instruments Inc. | Voltage regulator |
| CN120045005A (en) * | 2023-11-24 | 2025-05-27 | 茂达电子股份有限公司 | Low dropout linear voltage regulator with output voltage switching circuit |
| CN119105601A (en) * | 2024-08-28 | 2024-12-10 | 深圳市国微电子有限公司 | A low voltage dropout linear regulator and control method |
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