CN120631817A - Data transmission method and data transmission device - Google Patents
Data transmission method and data transmission deviceInfo
- Publication number
- CN120631817A CN120631817A CN202410279894.6A CN202410279894A CN120631817A CN 120631817 A CN120631817 A CN 120631817A CN 202410279894 A CN202410279894 A CN 202410279894A CN 120631817 A CN120631817 A CN 120631817A
- Authority
- CN
- China
- Prior art keywords
- stream
- stream buffer
- host
- processor core
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Information Transfer Systems (AREA)
Abstract
本申请提供了数据传输方法及数据传输装置。数据传输方法包含以下步骤:通过设备串流缓冲区传输串流至第一主机串流缓冲区或第一处理器核心;判断第一主机串流缓冲区或第一处理器核心是否已满;以及若判定第一主机串流缓冲区已满或第一处理器核心已满,改由备用设备串流缓冲区传输串流至第二主机串流缓冲区或第二处理器核心。
The present application provides a data transmission method and a data transmission apparatus. The data transmission method comprises the following steps: transmitting a stream to a first host stream buffer or a first processor core via a device stream buffer; determining whether the first host stream buffer or the first processor core is full; and if the first host stream buffer or the first processor core is determined to be full, transmitting the stream to a second host stream buffer or a second processor core via a backup device stream buffer.
Description
Technical Field
The present disclosure relates to a data transmission method and a data transmission device, and more particularly, to a data transmission method and a data transmission device for transmitting a stream through a standby device stream buffer.
Background
During streaming data transfer, if the processor core (CPU core) or the host streaming buffer (host stream buffer) cannot digest the streaming, the USB (Universal Serial Bus, USB) will be starved (starvation). The load balancing scheme load balance scheme may be used to help balance the loads to solve the above problem, however, the load balancing scheme generally needs a passive time before starting, which results in starvation of the usb during the passive time, thereby reducing the utilization of the usb.
Disclosure of Invention
In view of the shortcomings of the prior art, it is an object of the present disclosure to provide (but not limited to) a data transmission method and a data transmission device, so as to improve the shortcomings of the prior art.
In some embodiments, the data transmission method includes transmitting a stream to a first host stream buffer or a first processor core through a device stream buffer, determining whether the first host stream buffer or the first processor core is full, and if it is determined that the first host stream buffer is full or the first processor core is full, transmitting the stream to a second host stream buffer or the second processor core from a standby device stream buffer.
In some embodiments, the data transmission device includes a memory and a processor. The memory is used for storing at least one instruction. The processor is configured to read at least one instruction to transfer a stream to a first host stream buffer or a first processor core through the device stream buffer, determine whether the first host stream buffer or the first processor core is full, and transfer the stream to a second host stream buffer or a second processor core from the standby device stream buffer if the first host stream buffer is full or the first processor core is full.
The technical means embodied by the embodiments of the present disclosure may ameliorate at least one of the disadvantages of the prior art. According to the data transmission method and the data transmission device, streaming is transmitted through the standby equipment streaming buffer zone, so that the problem that the universal serial bus is in a starvation state is solved, and the utilization rate of the universal serial bus is improved.
The features, operations and technical effects of the present disclosure will be described in detail below with reference to preferred embodiments of the present disclosure in conjunction with the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of a data transmission device, drawn in accordance with some embodiments of the present disclosure;
FIG. 2 is a flow chart of a method of data transmission, drawn in accordance with some embodiments of the present disclosure;
fig. 3 is a block diagram of a data transmission device according to some embodiments of the present disclosure, and
Fig. 4 is a block diagram of a data transmission device, drawn in accordance with some embodiments of the present disclosure.
Symbol description
100 Data transmission device
110 Processor
120 Memory
200 Data transmission method
210-230 Steps of
310 Multiplexer
320 Device controller
330 Pipeline
340 Host controller
341 Multiplexer
Detailed Description
All terms used herein have their ordinary meaning. The foregoing definitions of words and phrases in commonly used dictionaries, including any examples of use of words and phrases in this disclosure are not intended to limit the scope and meaning of the present disclosure. Likewise, the disclosure is not limited to the various embodiments shown in this specification.
As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also mean that two or more elements are in operation or action with each other. As used herein, the term "circuit" may be a device connected by at least one transistor and/or at least one active and passive element in a manner to process a signal.
As used herein, the term "and/or" includes any combination of one or more of the listed associated items. The terms first, second, third, etc. are used herein to describe and distinguish between various elements. Thus, a first element could also be termed a second element herein without departing from the spirit of the present disclosure. For ease of understanding, like elements in the various figures will be designated with the same reference numerals.
In order to improve the problem that the processor core or the host stream buffer cannot digest streams, resulting in the general-purpose serial bus presenting starvation status, the disclosure provides a data transmission method and a data transmission device, which are described in detail below.
Fig. 1 is a schematic diagram of a data transmission device 100 according to some embodiments of the present disclosure. As shown, the data transmission device 100 includes a processor 110 and a memory 120. The memory 120 is used for storing at least one instruction. The processor 110 is configured to read at least one instruction to perform data transmission. For easy understanding of the operation of the data transmission apparatus 100, please refer to fig. 2, fig. 2 is a flowchart illustrating a data transmission method 200 according to some embodiments of the present disclosure.
In step 210, a stream is transmitted to a first host stream buffer or a first processor core through a device stream buffer. For example, referring to fig. 3, when a stream is to be transmitted, the stream may be transmitted from the device stream buffer (DEVICE STREAM buffer) (X) to the host stream buffer (host stream buffer) (X) or the processor core (CPU core) 0.
In some embodiments, the device stream buffer (X) transmits the stream to the multiplexer 310. The multiplexer 310 transmits the stream to the device controller device controller. The device controller 320 then transmits the stream to a multiplexer 341 of a host controller 340 through a pipe (pipe) 330. Then, the multiplexer 341 of the host controller 340 transmits the stream to the corresponding host stream buffer (X) or processor core 0.
In some embodiments, the pipe 330 may be a universal serial bus (Universal Serial Bus, USB), and the device stream buffer (X) may transmit streams to the host stream buffer (X) or the processor core 0 over the universal serial bus.
In step 220, it is determined whether the first host stream buffer or the first processor core is full. For example, referring to FIG. 3, it is determined whether the host stream buffer (X) or the processor core 0 is full and cannot process the stream.
In step 230, if it is determined that the first host stream buffer is full or the first processor core is full, the standby device stream buffer is used to transfer the stream to the second host stream buffer or the second processor core. For example, referring to fig. 3, if it is determined that the host stream buffer (X) is full or the processor core 0 is full, the standby device stream buffer (N) transfers the stream to the host stream buffer (N) or the processor core N.
In this way, when the host stream buffer is full or the processor core is full, the data transmission apparatus 100 and the data transmission method 200 of the present disclosure can transmit the stream to the idle host stream buffer or the idle processor core through the standby device stream buffer, thereby improving the problem that the usb is starved, and thus improving the utilization rate of the usb.
In some embodiments, step 230 further comprises exchanging the identification code of the stream to exchange the stream transmitting end from the device stream buffer to the standby device stream buffer. For example, if the stream is transmitted in the device stream buffer (X) corresponding to the original identifier (stream ID), the stream cannot be digested by the corresponding host stream buffer (X) or the processor core 0, and then the identifier may be exchanged by the identifier mechanism of the exchange (swap) stream. After the identification code is exchanged, the original equipment stream buffer area (X) is exchanged into the standby equipment stream buffer area (N), so that the standby equipment stream buffer area (N) can be used for transmitting the stream to the corresponding host stream buffer area (N) or the processor core N so as to process the stream, thereby avoiding the universal serial bus from being in a starvation state and improving the utilization rate of the universal serial bus.
In some embodiments, the second host stream buffer of step 230 is an idle host stream buffer and the second processor core is an idle processor core. In some embodiments, the present disclosure may also obtain the second host stream buffer or the second processor core that is idle by performing a polling operation. For example, the present disclosure may employ a round robin (round robin) mechanism to learn that the host streaming buffer (N) or the processor core N is in an idle state.
In some embodiments, the disclosure may also select a standby device stream buffer according to a standby look-up table, thereby transmitting the stream to the second host stream buffer or the second processor core. For example, if only a unique HASH number (RSS HASH value) is allocated, no swap (swap) operation is performed, and to improve this problem, the disclosure has a backup lookup table to provide a connection aggregation manner of different HASH numbers, thereby transmitting streams to an idle host stream buffer or an idle processor core.
In some embodiments, the present disclosure may select the standby device stream buffer based on an interrupt state of the bus, thereby transmitting the stream to the second host stream buffer or the second processor core. For example, the disclosure may specify which identifier (stream ID) corresponds to the device stream buffer to perform streaming according to the interrupt state (USB Host PCIE Interrupt) of the bus, so as to transmit the stream to the idle host stream buffer or the idle processor core.
In some embodiments, the present disclosure may transmit a first portion of the sub-stream of the stream to the first host stream buffer or the first processor core through the device stream buffer and a second portion of the sub-stream of the stream to the second host stream buffer or the second processor core through the standby device stream buffer. Referring to fig. 4, for example, a first portion of the sub-streams 1-N of the device stream buffer (X) are transmitted to the host stream buffer (X) or the processor core 0, and a second portion of the sub-streams n+1~M of the device stream buffer (N) are transmitted to the host stream buffer (N) or the processor core N. In some embodiments, the disclosure may include only one set of standby device stream buffers and standby host stream buffers, such as only standby device stream buffer (N) and standby host stream buffer (N), to save costs.
In some embodiments, the present disclosure may reorder the first and second partial sub-streams of the stream to fit a stream order. Referring to fig. 4, for example, the present disclosure may transmit a first portion of sub-streams 1 to N and a second portion of sub-streams n+1~M of a stream from a device stream buffer (X) and a standby device stream buffer (N) to a host stream buffer (X), a standby host stream buffer (N) or processor cores 0 and N, respectively, so that the utilization of the usb is maintained, and then reorder (re-order) the first portion of sub-streams 1 to N and the second portion of sub-streams n+1~M to conform to the stream order (in order). In this way, even if the following sub-stream (e.g., packet) is already transmitted in advance, the present disclosure can conform to the stream sequence by re-ordering the sub-stream after the transmission of the previously blocked sub-stream (e.g., packet), so as to smoothly perform the following stream processing.
In some embodiments, the re-ordering operations described above may be performed by the device side (e.g., by the device driver (DEVICE DRIVER)), or by the host side (e.g., by the host control driver (host controller driver), by the filter driver (FILTER DRIVER)), or the like. It should be noted that, since the switching time (turnaround time) of the universal serial bus is much longer than the reordering (re-order) time, the reordering time of the present disclosure is almost negligible. In addition, the above operation is only performed continuously for a Network stack (Network stack) of an upper Operating System (OS). The present disclosure does this with previously stuck streams and with standby streams only when implemented underneath.
In some embodiments, if it is determined that the first host stream buffer is full or the first processor core is full, the present disclosure may instead transmit multiple sub-streams of the stream from the multiple standby device stream buffers to the multiple second host stream buffers or the multiple second processor cores, respectively, at different time points. For example, if it is determined that the host stream buffer (X) is full or the processor core 0 is full, the present disclosure may instead transmit multiple sub-streams from the multiple standby device stream buffers (B), (N) to the multiple host stream buffers (B), (N) or the multiple processor cores B, N at different time points, respectively. However, the disclosure is not limited to this embodiment, and in other embodiments, the disclosure may also transmit multiple sub-streams from the multiple standby device stream buffers (B), (N) to the multiple host stream buffers (B), (N) or the multiple processor cores B, N at the same time, depending on the actual requirements.
It should be noted that the present disclosure is not limited to the embodiment shown in fig. 1 to 4, which is only used to exemplarily show one of the implementation manners of the present disclosure, so that the technology of the present disclosure is easy to understand, and the claims of the present disclosure are subject to the claims of the present invention. Modifications and variations which may be made to the embodiments of the present disclosure by those skilled in the art without departing from the spirit of the disclosure will still fall within the scope of the invention of the present disclosure.
In summary, the data transmission device 100 and the data transmission method 200 of the present disclosure transmit a stream through the standby device stream buffer, thereby improving the problem that the usb is starved, and improving the utilization of the usb.
Although the embodiments of the present disclosure have been described above, these embodiments are not intended to limit the present disclosure, and those skilled in the art may make variations to the technical features of the present disclosure according to the explicit or implicit disclosure, where the variations may belong to the scope of patent protection sought by the present disclosure, in other words, the scope of patent protection of the present disclosure should be defined by the claims of the present disclosure.
Claims (10)
1. A data transmission method, a processor reading at least one instruction stored in a memory to perform the data transmission method, comprising:
transmitting a stream to a first host stream buffer or a first processor core through a device stream buffer;
Determining whether the first host stream buffer or the first processor core is full, and
If the first host stream buffer is determined to be full or the first processor core is determined to be full, a standby device stream buffer is used to transfer the stream to a second host stream buffer or a second processor core.
2. The method of claim 1, wherein transferring the stream from the standby device stream buffer to the second host stream buffer or the second processor core comprises:
exchanging an identification code of the stream to exchange a stream transmitting end from the equipment stream buffer to the standby equipment stream buffer, and transmitting the stream from the standby equipment stream buffer to the second host stream buffer or the second processor core.
3. The method of claim 1, wherein the second host stream buffer comprises an idle host stream buffer, and the second processor core comprises an idle processor core.
4. The data transmission method of claim 1, further comprising:
a polling operation is performed to obtain the second host stream buffer or the second processor core that is idle.
5. The data transmission method of claim 1, further comprising:
Selecting the backup device stream buffer according to a backup lookup table, thereby transmitting the stream to the second host stream buffer or the second processor core.
6. The method of claim 1, wherein transferring the stream from the standby device stream buffer to the second host stream buffer or the second processor core comprises:
Selecting the standby device stream buffer according to an interrupt state of a bus, thereby transmitting the stream to the second host stream buffer or the second processor core.
7. The method of claim 1, wherein transmitting the stream to the first host stream buffer or the first processor core via the device stream buffer comprises:
Transmitting a first portion of the sub-stream of the stream to the first host stream buffer or the first processor core via the device stream buffer;
wherein transferring the stream from the standby device stream buffer to the second host stream buffer or the second processor core comprises:
Transmitting a second portion of the sub-stream of the stream to the second host stream buffer or the second processor core via the standby device stream buffer.
8. The data transmission method of claim 7, further comprising:
the first partial sub-stream and the second partial sub-stream are reordered to fit a stream order.
9. The method of claim 1, wherein transferring the stream from the standby device stream buffer to the second host stream buffer or the second processor core comprises:
And transmitting the multiple sub-streams of the stream to multiple second host stream buffers or multiple second processor cores at different time points respectively by using the multiple standby device stream buffers.
10. A data transmission device, comprising:
A memory for storing at least one instruction, and
A processor for reading the at least one instruction to perform the steps of:
transmitting a stream to a first host stream buffer or a first processor core through a device stream buffer;
Determining whether the first host stream buffer or the first processor core is full, and
If the first host stream buffer is determined to be full or the first processor core is determined to be full, a standby device stream buffer is used to transfer the stream to a second host stream buffer or a second processor core.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410279894.6A CN120631817A (en) | 2024-03-12 | 2024-03-12 | Data transmission method and data transmission device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410279894.6A CN120631817A (en) | 2024-03-12 | 2024-03-12 | Data transmission method and data transmission device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN120631817A true CN120631817A (en) | 2025-09-12 |
Family
ID=96962920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410279894.6A Pending CN120631817A (en) | 2024-03-12 | 2024-03-12 | Data transmission method and data transmission device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN120631817A (en) |
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2024
- 2024-03-12 CN CN202410279894.6A patent/CN120631817A/en active Pending
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