CN120600076A

CN120600076A - Memory device and operation method thereof, and memory system

Info

Publication number: CN120600076A
Application number: CN202410253871.8A
Authority: CN
Inventors: 董志鹏; 万维俊; 史维华
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2024-03-05
Filing date: 2024-03-05
Publication date: 2025-09-05

Abstract

Embodiments of the present disclosure provide a memory device, an operating method thereof, and a memory system, wherein the memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit coupled to the memory cell array; the peripheral circuit being configured to: perform a target state programming operation on a target memory cell among the plurality of memory cells; perform a verification operation on the target memory cell that has undergone the target state programming operation, the verification operation including a first verification operation and a second verification operation, the voltage corresponding to the second verification operation being greater than the voltage corresponding to the first verification operation; during the verification operation, recording a fail bit count of the first verification operation; and when it is determined that the fail bit count is less than or equal to the preset value, only performing the second verification operation in the next verification operation of the target state programming operation.

Description

Memory device, operation method thereof and memory system

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a memory device, an operation method thereof and a memory system.

Background

Memory devices are memory devices used in modern information technology to hold information. As a typical nonvolatile semiconductor Memory, a NAND flash Memory (NAND FLASH Memory) has become a mainstream product in the Memory market due to its high storage density, controllable production cost, suitable erasing speed and retention characteristics.

However, with the increasing demand for memory devices, there are a number of problems with memory devices in performing programming operations.

Disclosure of Invention

The embodiment of the disclosure provides a memory device, an operation method thereof and a memory system.

In a first aspect, an embodiment of the present disclosure provides a memory device including a memory cell array including a plurality of memory cells, a peripheral circuit coupled to the memory cell array, the peripheral circuit configured to perform a program operation of a target state on a target memory cell of the plurality of memory cells, perform a verify operation on the target memory cell subjected to the program operation of the target state, the verify operation including a first verify operation and a second verify operation, the second verify operation having a voltage greater than a voltage corresponding to the first verify operation, record a fail bit count of the first verify operation during the verify operation, and perform only the second verify operation in a next verify operation of the program operation of the target state when the fail bit count is determined to be less than or equal to the preset value.

In an alternative embodiment, the peripheral circuitry is further configured to perform the first verify operation and the second verify operation in a next verify operation of the program operation of the target state upon determining that the failed bit count is greater than the preset value.

In an alternative embodiment, the first verify operation includes a first sub-verify operation, the peripheral circuitry is configured to record a first failed bit count for the first sub-verify operation, and to perform only the second verify operation in a next verify operation of the program operation for the target state when the first failed bit count is determined to be less than or equal to the first preset value.

In an alternative embodiment, the first verification operation comprises a first sub-verification operation and a second sub-verification operation, the voltage corresponding to the second sub-verification operation is larger than the voltage corresponding to the first sub-verification operation, the peripheral circuit is configured to record a first failure bit count of the first sub-verification operation, only execute the second sub-verification operation and the second verification operation in the next verification operation of the target state programming operation when the first failure bit count is smaller than or equal to the first preset value, or execute the second verification operation only in the next verification operation of the target state programming operation when the second failure bit count is smaller than or equal to the second preset value.

In an alternative embodiment, the first verification operation includes a first sub-verification operation, a second sub-verification operation, and a third sub-verification operation, the third sub-verification operation corresponds to a voltage greater than the second sub-verification operation, the second sub-verification operation corresponds to a voltage greater than the first sub-verification operation, the peripheral circuit is configured to record a first failed bit count of the first sub-verification operation, to perform only the second sub-verification operation, the third sub-verification operation, and the second verification operation in a next verification operation of the target state when the first failed bit count is determined to be less than or equal to the first preset value, or to perform only the second failed bit count of the second sub-verification operation when the second failed bit count is determined to be less than or equal to the second preset value, to perform only the third sub-verification operation and the third sub-verification operation when the second failed bit count is determined to be less than or equal to the third preset value in a next verification operation of the target state.

In an alternative embodiment, the peripheral circuit is further configured to apply a first bit line voltage to bit lines of the target memory cells coupled to the memory cells that do not pass a first sub-verify operation, apply a second bit line voltage to bit lines of the target memory cells coupled to the memory cells that do not pass a second verify operation, and apply a third bit line voltage to bit lines of the target memory cells coupled to the memory cells that do not pass a second verify operation, wherein the first bit line voltage is less than the second bit line voltage and the second bit line voltage is less than the third bit line voltage.

In an alternative embodiment, the peripheral circuit is further configured to apply a first bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a first sub-verify operation, apply a second bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a second sub-verify operation, apply a fourth bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a second sub-verify operation, apply a third bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a second verify operation, wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

In an alternative embodiment, the peripheral circuit is further configured to apply a first bit line voltage to a bit line coupled to the memory cells of the target memory cells that do not pass the first sub-verify operation, apply a second bit line voltage to a bit line coupled to the memory cells of the target memory cells that do not pass the second sub-verify operation, apply a fourth bit line voltage to a bit line coupled to the memory cells of the target memory cells that do not pass the third sub-verify operation, apply a fifth bit line voltage to a bit line coupled to the memory cells of the target memory cells that do not pass the third sub-verify operation, apply a third bit line voltage to a bit line coupled to the memory cells of the target memory cells that do not pass the second sub-verify operation, wherein the first bit line voltage is less than the second bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage.

In a second aspect, the disclosed embodiments provide a memory system comprising a memory device as described in the first aspect, and a memory controller coupled to the memory device and configured to control the memory device.

In a third aspect, an embodiment of the present disclosure provides an operation method of a memory device, the memory device including a memory cell array including a plurality of memory cells, the operation method including performing a program operation of a target state on a target memory cell of the plurality of memory cells, performing a verify operation on the target memory cell subjected to the program operation of the target state, the verify operation including a first verify operation and a second verify operation, the second verify operation having a voltage greater than a voltage corresponding to the first verify operation, recording a fail bit count of the first verify operation during the verify operation, and performing only the second verify operation in a next verify operation of the program operation of the target state when the fail bit count is determined to be less than or equal to the preset value.

In an alternative embodiment, the method further comprises performing the first verify operation and the second verify operation in a next verify operation of the program operation of the target state when the fail bit count is determined to be greater than the preset value.

In an alternative embodiment, the first verifying operation includes a first sub-verifying operation, recording a failed bit count of the first verifying operation, determining that the failed bit count is less than or equal to the preset value, and executing only the second verifying operation in a next verifying operation of the program operation of the target state, including recording a first failed bit count of the first sub-verifying operation, determining that the first failed bit count is less than or equal to the first preset value, and executing only the second verifying operation in a next verifying operation of the program operation of the target state.

In an alternative implementation, the first verification operation includes a first sub-verification operation and a second sub-verification operation, the second sub-verification operation corresponds to a voltage greater than the voltage corresponding to the first sub-verification operation, the failed bit count of the first verification operation is recorded, when the failed bit count is determined to be less than or equal to the preset value, only the second verification operation is executed in the next verification operation of the target state programming operation, including recording the first failed bit count of the first sub-verification operation, when the first failed bit count is determined to be less than or equal to the first preset value, only the second sub-verification operation and the second verification operation are executed in the next verification operation of the target state programming operation, or recording the second failed bit count of the second coarse verification operation, and when the second failed bit count is determined to be less than or equal to the second preset value, executing only the second verification operation in the next verification operation of the target state programming operation.

In an alternative embodiment, the first verification operation includes a first sub-verification operation, a second sub-verification operation, and a third sub-verification operation, the third sub-verification operation corresponds to a voltage greater than the second sub-verification operation, the second sub-verification operation corresponds to a voltage greater than the first sub-verification operation, the failed bit count of the first verification operation is recorded, when the failed bit count is determined to be less than or equal to the preset value, only the second verification operation is executed in a next verification operation of the target state programming operation, including recording a first failed bit count of the first sub-verification operation, when the first failed bit count is determined to be less than or equal to the first preset value, only the second sub-verification operation, the third sub-verification operation, and the second verification operation are executed in a next verification operation of the target state programming operation, or recording a second failed bit count of the second sub-verification operation, when the second failed bit count is determined to be less than or equal to the preset value, and when the second failed bit count is determined to be less than or equal to the first preset value, and the third verification operation is executed in the target state programming operation.

In an alternative embodiment, the method further comprises applying a first bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a first sub-verify operation, applying a second bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a first sub-verify operation, and applying a third bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a second verify operation, wherein the first bit line voltage is less than the second bit line voltage and the second bit line voltage is less than the third bit line voltage.

In an alternative embodiment, the method further comprises applying a first bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a first sub-verify operation, applying a second bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a second sub-verify operation, applying a fourth bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a second sub-verify operation, applying a third bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass a second verify operation, wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

In an alternative embodiment, the method further comprises applying a first bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass the first sub-verify operation, applying a second bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass the second sub-verify operation, applying a fourth bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass the third sub-verify operation, applying a fifth bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass the third sub-verify operation, applying a third bit line voltage to bit lines coupled to the memory cells of the target memory cells that do not pass the second sub-verify operation, wherein the first bit line voltage is less than the second bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage.

The embodiment of the disclosure provides a memory device and an operation method thereof, and a memory system, wherein the memory device comprises a memory cell array, a peripheral circuit, wherein the memory cell array comprises a plurality of memory cells, the peripheral circuit is coupled to the memory cell array and is configured to perform target state programming operation on target memory cells in the plurality of memory cells, perform verification operation on target memory cells subjected to the target state programming operation, the verification operation comprises a first verification operation and a second verification operation, the voltage corresponding to the second verification operation is larger than the voltage corresponding to the first verification operation, the failure bit count of the first verification operation is recorded in the verification operation process, and only the second verification operation is executed in the next verification operation of the target state programming operation when the failure bit count is smaller than or equal to the preset value. Based on this, in the embodiment of the disclosure, whether the first verification operation needs to be performed can be determined according to the failed bit count of the first verification operation of the target memory cell, so that the number of unnecessary verification operations is reduced, and further, the programming efficiency can be improved, and the programming verification time can be shortened.

Drawings

FIG. 1 is a schematic diagram of an exemplary system having a memory system according to one embodiment of the present disclosure;

FIG. 2a is a schematic diagram of an exemplary memory card having a memory system according to one embodiment of the present disclosure;

FIG. 2b is a schematic diagram of an exemplary solid state drive with a memory system according to an embodiment of the present disclosure;

FIG. 3 is a schematic circuit diagram of an exemplary memory device including peripheral circuitry provided in accordance with an embodiment of the present disclosure;

FIG. 4 is a schematic cross-sectional view of a memory cell array including NAND memory strings provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry provided in accordance with one embodiment of the present disclosure;

FIG. 6 is a diagram illustrating a first threshold voltage distribution of a memory cell according to one embodiment of the present disclosure;

FIG. 7 is a second threshold voltage distribution diagram of a memory cell according to an embodiment of the disclosure;

FIG. 8 is a third threshold voltage distribution diagram of a memory cell according to an embodiment of the present disclosure;

fig. 9 is a flowchart illustrating an implementation of an operation method of a memory device according to an embodiment of the disclosure.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known functions and constructions are not described in detail to avoid obscuring the present disclosure, i.e., not all features of an actual embodiment are described herein.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

Spatial relationship terms such as "under", "above", "over" and the like may be used herein for convenience of description to describe one element or feature as illustrated in the figures in relation to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.

The memory device in the embodiments of the present disclosure includes, but is not limited to, a three-dimensional NAND-type memory, which is exemplified for ease of understanding.

Fig. 1 illustrates a block diagram of an exemplary system 100 having a memory device in accordance with aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a pointing device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an augmented Reality (AR, augmented Reality) device, or any other suitable electronic device having a memory therein. As shown in fig. 1, system 100 may include a host 108 and a memory system 102, memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU, central Processing Unit)) or a System-on-a-chip (SoC) (e.g., an application processor (AP, application Processor)). Host 108 may be configured to send data to memory device 104 or receive data from memory device 104.

According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 may manage data stored in memory device 104 and communicate with host 108. In some implementations, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal serial bus (USB, universal Serial Bus) Flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment Solid state disk (SSD, solid STATE DRIVES) or embedded multimedia card (eMMC, eMMC MEDIA CARD), which are used as data storage and enterprise storage arrays for mobile devices such as smartphones, tablet computers, laptop computers, and the like.

The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in the memory device 104 including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, the memory controller 106 is also configured to process Error Correction Codes (ECC) on data read from the memory device 104 or written to the memory device 104. The memory controller 106 may also perform any other suitable function, such as formatting the memory device 104. Memory controller 106 may communicate with external devices (e.g., host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI, PERIPHERAL COMPONENT INTERCONNECT) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA, advanced Technology Attachment) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small interface (SCSI, small Computer SYSTEM INTERFACE) protocol, an enhanced Small disk interface (ESDI, enhanced Small Drive Interface) protocol, an integrated drive Electronics (IDE, integrated Drive Electronics) protocol, a Firewire (Firewire) interface protocol, and the like.

The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS, universal Flash Storage) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronics. In one example as shown in fig. 2a, the memory controller 106 and the single memory device 104 may be integrated into the memory card 202. Memory card 202 may include a PC card (PCMCIA, personal computer memory card International Association), a CF card (Compact Flash), a Smart Media card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (Secure DIGITAL CARD) (SD, miniSD, microSD, SDHC), a UFS, or the like. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in fig. 1). In another example as shown in fig. 2b, the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. SSD206 can also include SSD connector 208 that couples SSD206 with a host (e.g., host 108 in FIG. 1). In some implementations, the storage capacity and/or the operating speed of the SSD206 is greater than the storage capacity and/or the operating speed of the memory card 202.

Fig. 3 shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry provided in accordance with an embodiment of the present disclosure. Memory device 300 may be an example of memory device 104 in fig. 1. The memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND memory cell array in which memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, e.g., voltage or charge, depending on the number of electrons trapped within the area of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

In some embodiments, each memory cell 306 is a Single Level Cell (SLC) that has two possible memory states and thus can store one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a Multi-level cell (MLC, multi-LEVEL CELL) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three level cell (TLC, trinary-LEVEL CELL)), or four bits per cell (also known as a four level cell (QLC, quad-LEVEL CELL)). Each MLC may be programmed to take a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible program levels from the erased state by writing one of three possible nominal storage values to the cell. The fourth nominal stored value may be used for the erased state.

As shown in fig. 3, each NAND memory string 308 may include a lower select gate (BSG, bottom SELECT GATE) 310 at its source end and an upper select gate (TSG, top SELECT GATE) 312 at its drain end. BSG310 and TSG312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some implementations, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same Source Line 314 (e.g., common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS, array Common Source). According to some embodiments, the TSG312 of each NAND memory string 308 is coupled to a respective Bit Line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., above the threshold voltage of the transistor having TSG 312) or a deselect voltage (e.g., 0V) to the respective TSG312 via one or more TSG lines 313 and/or by applying a select voltage (e.g., above the threshold voltage of the transistor having BSG 310) or a deselect voltage (e.g., 0V) to the respective BSG310 via one or more BSG lines 315.

As shown in FIG. 3, the NAND memory strings 308 may be organized into a plurality of memory blocks 304, each of the plurality of memory blocks 304 may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic unit of data for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase memory cells 306 in a selected memory block, source lines 314 coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block may be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, the erase operation may be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 may be coupled by a word line 318, the word line 318 selecting which row of memory cells 306 is affected by the read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cells 306, the page 320 being the basic unit of data for a programming operation. The size of a page 320 in bits may be related to the number of NAND memory strings 308 coupled by word lines 318 in one memory block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a respective page 320 and a gate line coupling the control gates.

FIG. 4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including NAND memory strings 308 provided in accordance with an embodiment of the present disclosure. As shown in fig. 4, the NAND memory string 308 may include a stacked structure 410, the stacked structure 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and the memory string 308 vertically penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and adjacent two gate layers 411 are separated by one insulating layer 412. The number of pairs of the gate layer 411 and the insulating layer 412 in the stacked structure 410 can determine the number of memory cells included in the memory cell array 401.

The constituent material of the gate layer 411 may include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 comprises a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding the memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper select gate line and the lower select gate line may act as a word line layer.

In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include Silicon (e.g., single crystal Silicon), silicon Germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-Insulator (SOI), germanium-on-Insulator (GOI), or any other suitable material.

In some embodiments, the NAND memory string 308 includes channel structures that extend vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with semiconductor material(s) (e.g., as a semiconductor channel) and dielectric material(s) (e.g., as a memory film). In some embodiments, the semiconductor channel comprises silicon, e.g., polysilicon. In some embodiments, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a "charge trapping/storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, the tunneling layer, the memory layer, and the barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

Referring back to fig. 3, peripheral circuitry 302 may be coupled to memory cell array 301 by bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed signal circuitry for facilitating operation of memory cell array 301 by applying voltage signals and/or current signals to each target memory cell 306 and sensing voltage signals and/or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology. For example, fig. 5 shows some exemplary peripheral circuits, peripheral circuit 302 including page buffer/sense amplifier 504, column decoder/bit line driver 506, row decoder/word line driver 508, voltage generator 510, control logic 512, registers 514, interface 516, and data bus 518. It should be appreciated that in some examples, additional peripheral circuitry not shown in fig. 5 may also be included.

The page buffer/sense amplifier 504 may be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer/sense amplifier 504 may store a page of program data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer/sense amplifier 504 may perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to the selected word line 318. In yet another example, the page buffer/sense amplifier 504 may also sense a low power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to an identifiable logic level in a read operation. The column decoder/bit line driver 506 may be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from a voltage generator 510.

The row decoder/wordline driver 508 may be configured to be controlled by the control logic 512 and to select/deselect the memory blocks 304 of the memory cell array 301 and to select/deselect the wordlines 318 of the memory blocks 304. The row decoder/wordline driver 508 may also be configured to drive the wordlines 318 using the wordline voltage generated from the voltage generator 510. In some implementations, the row decoder/wordline driver 508 may also select/deselect and drive the BSG lines 315 and TSG lines 313. As described in detail below, the row decoder/wordline driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected wordline(s) 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

Control logic 512 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The registers 514 may be coupled to the control logic 512 and include status registers, command registers, and address registers for storing status information, command Operation codes (OP codes), and command addresses for controlling the Operation of each peripheral circuit. Interface 516 may be coupled to control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic 512, and to buffer status information received from control logic 512 and relay them to the host. Interface 516 may also be coupled to column decoder/bit line driver 506 via data bus 518 and acts as a data I/O interface and data buffer to buffer data and relay it to memory cell array 301 or relay or buffer data from memory cell array 301.

Typically, an incremental step pulse programming (ISPP, incremental Step-Pulse Programming) may be used to program a NAND type memory. For NAND-type memories, the programming operation is performed in units of memory pages (pages), each of which includes a plurality of memory cells. Specifically, when performing a program operation of a target state, a first program pulse (program voltage) is applied to a memory cell (target memory cell) of a selected memory page (target memory page) in the memory, and then a verify operation is performed on the target memory cell to verify whether the threshold voltage of each target memory cell in the selected memory page reaches a target threshold voltage. If the number of target memory cells not programmed to the target threshold voltage is greater than the allowable range, a second programming pulse having a higher voltage is reapplied, and a verify operation is performed again after the second programming pulse is applied. The above process of applying the program pulse and performing the verifying operation is repeated until the programming of the entire memory page is ended when the number of target memory cells not programmed to the target threshold voltage is within the allowable range.

To facilitate evaluation of the number of target memory cells in a memory page that have not been programmed to a target threshold voltage after a programming pulse is applied to the memory page, a Fail Bit Count (FBC) is introduced, which refers to the number of bits in the memory page that have not been programmed to the target threshold voltage. In practical applications, when performing the verification operation, whether the verification is passed or not may be determined according to the size of the failed bit count.

The target threshold voltage is used to determine whether the target memory cell reaches the target state. Specifically, a target memory cell reaches a target state when its threshold voltage is greater than a target threshold voltage. When the threshold voltage of the target memory cell is less than or equal to the target threshold voltage, the target memory cell does not reach the target state.

In different programming phases of an ISPP programming operation, in order to optimize the threshold voltage distribution and relatively more intensively distribute the threshold values of the programming units in the threshold voltage areas of the corresponding data states, different bit line voltages are offset to the bit lines of different target memory units, namely, bit line forced operation (forcing operation) is realized, so that even if the programming voltages Vpgm of the gates (applied through the word lines) of the target memory units of different bit lines are the same, the programming effect is different, and the threshold voltage difference of the target memory units with larger current threshold voltage difference is reduced and relatively tends to an ideal threshold voltage area after being programmed.

The present disclosure does not limit the number of bits stored per memory cell. The present disclosure illustrates a TLC with a number of storage bits of 3 as an example, where TLC has 8 states (LV 0-LV 7), where LV0 is the erased state and LV1-LV7 are the programmed states. Here, the target state may be any one of 7 programmed states. As described above, the above programming method requires applying the programming pulse a plurality of times, and after each application of the programming pulse, at least two verify operations are required to verify the programming result of the verify target memory cell to determine the target memory cell for which the bit line forcing operation is required. Therefore, the program verification time is long.

Based on this, in order to improve programming efficiency and shorten program verification time, the embodiments of the present disclosure provide a memory device and an operating method thereof. The memory device comprises a memory cell array, a peripheral circuit and a control circuit, wherein the memory cell array comprises a plurality of memory cells, the peripheral circuit is coupled to the memory cell array and is configured to conduct target state programming operation on target memory cells in the plurality of memory cells, conduct verification operation on the target memory cells which are subjected to the target state programming operation, the verification operation comprises a first verification operation and a second verification operation, the voltage corresponding to the second verification operation is larger than the voltage corresponding to the first verification operation, in the process of conducting the verification operation, the failed bit count of the first verification operation is recorded, and when the failed bit count is determined to be smaller than or equal to a preset value, in the next verification operation of the target state programming operation, only the second verification operation is conducted.

In some embodiments, the peripheral circuit is further configured to perform a first verify operation and a second verify operation in a next verify operation of the program operation of the target state when the fail bit count is determined to be greater than the preset value.

In the disclosed embodiment, for the programming operation of the target state, the verification operation is required for the target memory cell after each application of the programming pulse (programming voltage). During the verification operation, a failed bit count of the first verification operation is recorded to count the number of memory cells that failed the first verification operation. And when the failed bit count of the first verification operation is greater than the preset value, continuing to execute the first verification operation and the second verification operation in the next verification operation of the programming operation of the target state. Here, the preset value may be set with reference to a preset FBC. The predetermined FBC is the maximum number of memory cells in the target page that the memory device is allowed to have not reached the target state. In a specific example, the preset value may be 10.

FIG. 6 is a diagram illustrating a first threshold voltage distribution of a memory cell according to an embodiment of the present disclosure. Referring to fig. 6, in an example embodiment of the present disclosure, memory cells having a threshold voltage greater than the program verify voltage Vvfy may be inhibit cells (Inhibiting Cell). Further programming of memory cells that have reached a target state (i.e., a target threshold voltage) may be inhibited by applying a program-inhibit bit line voltage Vinh (e.g., a supply voltage VDD) on the bit line to which the inhibit cell corresponds. Further, the memory cells having a threshold voltage level smaller than the program verify voltage Vvfy may be program cells (PGM cells). Here, the program verify voltage Vvfy is a voltage corresponding to the second verify operation. In other words, the memory cell passing the second verification operation is the prohibition unit in the target memory cells. The first verifying operation includes a first sub-verifying operation, and a voltage corresponding to the first sub-verifying operation is a first forced sensing voltage Vfc1, in other words, a verifying voltage used by the first sub-verifying operation is the first forced sensing voltage Vfc1. The first forced sensing voltage Vfc1 may be less than the program verify voltage Vvfy. In example embodiments of the present disclosure, a memory cell that fails the first sub-verify operation among the target memory cells is referred to as a 2BL cell, i.e., a threshold voltage of the 2BL cell is less than the first forced sensing voltage Vfc1. A memory cell passing through the first sub-verify operation but not passing through the second verify operation among the target memory cells is referred to as a 3BL cell, i.e., a threshold voltage of the 3BL cell is greater than the first forced sensing voltage Vfc1 and less than the program verify voltage Vvfy.

In some embodiments, the first verify operation includes a first sub-verify operation, the peripheral circuitry is configured to record a first failed bit count for the first sub-verify operation, and to perform only the second verify operation in a next verify operation of the program operation in the target state when the first failed bit count is determined to be less than or equal to a first preset value.

In the disclosed embodiments, after a program pulse is applied to a target memory cell, a verify operation is performed on the target memory cell. The verification operations include a first sub-verification operation and a second verification operation. Referring to fig. 6, performing a first sub-verify operation on a target memory cell includes applying a first forced sensing voltage Vfc1 to the target memory cell, and performing a second verify operation on the target memory cell includes applying a program verify voltage Vvfy to the target memory cell. After the first forced sensing voltage Vfc1 is applied to the target memory cell, a first fail bit count of the first sub-verify operation is recorded to count the number of 2BL cells (memory cells that do not pass the first sub-verify operation). And when the first failure bit count is larger than the first preset value, continuing to execute the first sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state. In a specific example, the first preset value may be 10.

In some embodiments, when the first fail bit count is greater than a first preset value, a bit line forced operation may be performed on the 3BL cells in a subsequent programming process. In addition, the 2BL cell is a normal program cell performing a normal program operation. It should be noted that, the normal program cell is a memory cell in which the bit line forcing operation is not performed in the program cell, and thus, in some embodiments, the normal program cell may also be referred to as a program cell that will not be forced to operate.

In some embodiments, the peripheral circuitry is further configured to apply a first bit line voltage to bit lines of the target memory cells coupled to memory cells that do not pass the first sub-verify operation, apply a second bit line voltage to bit lines of the target memory cells coupled to memory cells that do not pass the first sub-verify operation, and apply a third bit line voltage to bit lines of the target memory cells coupled to memory cells that do pass the second verify operation, wherein the first bit line voltage is less than the second bit line voltage and the second bit line voltage is less than the third bit line voltage.

In the embodiment of the disclosure, a first bit line voltage is applied to a bit line coupled to a 2BL unit, a second bit line voltage is applied to a bit line coupled to a 3BL unit, and a third bit line voltage is applied to a bit line coupled to a forbidden unit, wherein the first bit line voltage is smaller than the second bit line voltage, and the second bit line voltage is smaller than the third bit line voltage. Here, the first bit line voltage is a normal program bit line voltage Vprog (e.g., a ground voltage Vgnd), the third bit line voltage is a program-inhibit bit line voltage Vinh (e.g., a power supply voltage VDD), and the second bit line voltage is a program-forced bit line voltage that is greater than the normal program bit line voltage Vprog and less than the program-inhibit bit line voltage Vinh.

It should be noted that, when the first failed bit count is less than or equal to the first preset value (i.e., in the case where the first sub-verify operation is not performed), the second bit line voltage is applied to the bit lines coupled to the memory cells that do not pass the second verify operation among the target memory cells.

In the embodiment of the present disclosure, when the first fail bit count is less than or equal to the first preset value (i.e., in the case where the first sub-verify operation is not performed), the memory cell (2 BL cell) which does not pass the first sub-verify operation is treated as the 3BL cell in the following programming process, in other words, the same bit line forced operation as the 3BL cell is performed on the 2BL cell in the following programming process. In a specific example, a second bit line voltage is applied to the bit lines to which the 2BL cell and the 3BL cell are coupled in a subsequent programming process.

FIG. 7 is a second threshold voltage distribution diagram of a memory cell according to an embodiment of the disclosure. Referring to fig. 7, in an example embodiment of the present disclosure, memory cells having a threshold voltage greater than the program verify voltage Vvfy may be inhibit cells. Further, memory cells having a threshold voltage level less than the program verify voltage Vvfy may be program cells. Here, the program verify voltage Vvfy is a voltage corresponding to the second verify operation. The first verifying operation includes a first sub-verifying operation and a second sub-verifying operation, and a voltage corresponding to the first sub-verifying operation is a first forced sensing voltage Vfc1. The voltage corresponding to the second sub-verify operation is the second forced sensing voltage Vfc2, in other words, the verify voltage used by the second sub-verify operation is the second forced sensing voltage Vfc2. The first forced sensing voltage Vfc1 may be smaller than the second forced sensing voltage Vfc2, and both the first forced sensing voltage Vfc1 and the second forced sensing voltage Vfc2 are smaller than the program-verify voltage Vvfy. In example embodiments of the present disclosure, a memory cell that fails the first sub-verify operation among the target memory cells is referred to as a 2BL cell, i.e., a threshold voltage of the 2BL cell is less than the first forced sensing voltage Vfc1. A memory cell passing through the first sub-verify operation but not passing through the second sub-verify operation among the target memory cells is referred to as a 3BL cell, i.e., a threshold voltage of the 3BL cell is greater than the first forced sensing voltage Vfc1 and less than the second forced sensing voltage Vfc2. The memory cells of the target memory cells that pass the second sub-verify operation but do not pass the second verify operation are referred to as 4BL cells, i.e., the threshold voltage of the 4BL cells is greater than the second forced sensing voltage Vfc2 and less than the program verify voltage Vvfy.

In some embodiments, the first verify operation includes a first sub-verify operation and a second sub-verify operation, the second sub-verify operation corresponding to a voltage greater than the voltage corresponding to the first sub-verify operation, the peripheral circuit is configured to record a first failed bit count for the first sub-verify operation, to perform only the second sub-verify operation and the second verify operation in a next verify operation of the program operation in the target state when the first failed bit count is determined to be less than or equal to a first preset value, or to record a second failed bit count for the second sub-verify operation when the second failed bit count is determined to be less than or equal to a second preset value, and to perform only the second verify operation in the next verify operation of the program operation in the target state.

In the disclosed embodiments, after a program pulse is applied to a target memory cell, a verify operation is performed on the target memory cell. The verification operations include a first sub-verification operation, a second sub-verification operation, and a second verification operation. Referring to fig. 7, performing a first sub-verify operation on a target memory cell includes applying a first forced sensing voltage Vfc1 to the target memory cell, performing a second sub-verify operation on the target memory cell includes applying a second forced sensing voltage Vfc2 to the target memory cell, and performing a second verify operation on the target memory cell includes applying a program verify voltage Vvfy to the target memory cell.

In some embodiments, after the first forced sensing voltage Vfc1 is applied to the target memory cell, the first fail bit count of the first sub-verify operation is recorded to count the number of 2BL cells (memory cells that do not pass the first sub-verify operation). And when the first failure bit count is larger than the first preset value, continuing to execute the first sub-verification operation, the second sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state.

In other embodiments, after the second forced sensing voltage Vfc2 is applied to the target memory cell, a second fail bit count of the second sub-verify operation is recorded to count the number of 2BL cells and 3BL cells (memory cells that do not pass the second sub-verify operation). And when the second failure bit count is larger than the second preset value, continuing to execute the first sub-verification operation, the second sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state.

In some embodiments, the first preset value and the second preset value may be the same. In other embodiments, the second preset value may be greater than the first preset value. In a specific example, the first preset value may be 10 and the second preset value may be 20.

In some embodiments, when the first fail bit count is greater than a first preset value, a bit line forced operation may be performed on the 3BL cells and the 4BL cells in a subsequent programming process. The bit line forced operation in the embodiment of the present disclosure includes a first bit line forced operation and a second bit line forced operation. And the 3BL cell may be a memory cell to be subjected to a first bit line forced operation and the 4BL cell may be a memory cell to be subjected to a second bit line forced operation.

In some embodiments, the peripheral circuitry is further configured to apply a first bit line voltage to bit lines of the target memory cells coupled to memory cells that do not pass the first sub-verify operation, apply a second bit line voltage to bit lines of the target memory cells coupled to memory cells that do not pass the first sub-verify operation, apply a fourth bit line voltage to bit lines of the target memory cells coupled to memory cells that do not pass the second sub-verify operation, apply a third bit line voltage to bit lines of the target memory cells coupled to memory cells that do not pass the second verify operation, wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, and the fourth bit line voltage is less than the third bit line voltage.

In the embodiment of the disclosure, a first bit line voltage is applied to a bit line coupled to a 2BL unit, a second bit line voltage is applied to a bit line coupled to a 3BL unit, a fourth bit line voltage is applied to a bit line coupled to a 4BL unit, and a third bit line voltage is applied to a bit line coupled to a forbidden unit, wherein the first bit line voltage is smaller than the second bit line voltage, the second bit line voltage is smaller than the fourth bit line voltage, and the fourth bit line voltage is smaller than the third bit line voltage. Here, the first bit line voltage is a normal program bit line voltage Vprog (e.g., a ground voltage Vgnd), the third bit line voltage is a program-inhibit bit line voltage Vinh (e.g., a power supply voltage VDD), and the second and fourth bit line voltages are forced program bit line voltages that are both greater than the normal program bit line voltage Vprog and less than the program-inhibit bit line voltage Vinh. In a specific example, the second bit line voltage is a program-forced bit line voltage applied when the first bit line program operation is performed, and the fourth bit line voltage is a program-forced bit line voltage applied when the second bit line program operation is performed.

It should be noted that, when the first failed bit count is less than or equal to the first preset value (i.e., in the case where the first sub-verify operation is not performed), the second bit line voltage is applied to the bit lines coupled to the memory cells that do not pass the second sub-verify operation among the target memory cells. And applying a fourth bit line voltage to bit lines coupled to memory cells that do not pass the second verify operation among the target memory cells when the second fail bit count is less than or equal to a second preset value (i.e., without performing the first and second sub-verify operations).

In the embodiment of the present disclosure, when the first fail bit count is less than or equal to the first preset value (i.e., in the case where the first sub-verify operation is not performed), the 2BL cells are treated as the 3BL cells in the following programming process, in other words, the same first bit line forced operation as the 3BL cells is performed on the 2BL cells in the following programming process. In a specific example, a second bit line voltage is applied to the bit lines to which the 2BL cell and the 3BL cell are coupled in a subsequent programming process. When the second fail bit count is less than or equal to a second preset value (i.e., in the case where the first sub-verify operation and the second sub-verify operation are not performed), the memory cells (2 BL cells and 3BL cells) that do not pass the second sub-verify operation are handled as 4BL cells in the following programming process, in other words, the 2BL cells and 3BL cells are subjected to the same second bit line forced operation as the 4BL cells in the following programming process. In a specific example, a fourth bit line voltage is applied to the bit lines to which the 2BL cell, the 3BL cell, and the 4BL cell are coupled in a subsequent programming process.

FIG. 8 is a third threshold voltage distribution diagram of a memory cell according to an embodiment of the present disclosure. In an example embodiment of the present disclosure, referring to fig. 8, memory cells having a threshold voltage greater than the program verify voltage Vvfy may be inhibit cells. Further, memory cells having a threshold voltage level less than the program verify voltage Vvfy may be program cells. Here, the program verify voltage Vvfy is a voltage corresponding to the second verify operation. The first verifying operation includes a first sub-verifying operation, a second sub-verifying operation, and a third sub-verifying operation, and a voltage corresponding to the first sub-verifying operation is a first forced sensing voltage Vfc1. The voltage corresponding to the second sub-verify operation is the second forced sensing voltage Vfc2. The voltage corresponding to the third sub-verify operation is the third forced sensing voltage Vfc3, in other words, the verify voltage used by the third sub-verify operation is the third forced sensing voltage Vfc3. The first forced sensing voltage Vfc1 may be smaller than the second forced sensing voltage Vfc2, the second forced sensing voltage Vfc2 may be smaller than the third forced sensing voltage Vfc3, and the first, second, and third forced sensing voltages Vfc1, vfc2, and Vfc3 are each smaller than the program-verify voltage Vvfy. In example embodiments of the present disclosure, a memory cell that fails the first sub-verify operation among the target memory cells is referred to as a 2BL cell, i.e., a threshold voltage of the 2BL cell is less than the first forced sensing voltage Vfc1. A memory cell passing through the first sub-verify operation but not passing through the second sub-verify operation among the target memory cells is referred to as a 3BL cell, i.e., a threshold voltage of the 3BL cell is greater than the first forced sensing voltage Vfc1 and less than the second forced sensing voltage Vfc2. A memory cell passing through the second sub-verify operation but not passing through the third sub-verify operation among the target memory cells is referred to as a 4BL cell, that is, a threshold voltage of the 4BL cell is greater than the second forced sensing voltage Vfc2 and less than the third forced sensing voltage Vfc3. A memory cell passing through the third sub-verify operation but not passing through the second verify operation among the target memory cells is referred to as a 5BL cell, i.e., a threshold voltage of the 5BL cell is greater than the third forced sensing voltage Vfc3 and less than the program-verify voltage Vvfy.

In some embodiments, the first verify operation includes a first sub-verify operation, a second sub-verify operation, and a third sub-verify operation, the third sub-verify operation corresponding to a voltage greater than the second sub-verify operation corresponding to a voltage greater than the first sub-verify operation, the peripheral circuitry is configured to record a first failed bit count for the first sub-verify operation, to perform only the second sub-verify operation, the third sub-verify operation, and the second verify operation in a next verify operation of the program operation of the target state when the first failed bit count is determined to be less than or equal to a first preset value, or to record a second failed bit count for the second sub-verify operation when the second failed bit count is determined to be less than or equal to a second preset value, to perform only the third sub-verify operation and the second verify operation in a next verify operation of the program operation of the target state, or to record a third failed bit count for the third sub-verify operation when the third failed bit count is determined to be less than or equal to a third preset value, to perform only the second verify operation in a next verify operation of the program operation of the target state.

In the disclosed embodiments, after a program pulse is applied to a target memory cell, a verify operation is performed on the target memory cell. The verifying operation includes a first sub-verifying operation, a second sub-verifying operation, a third sub-verifying operation, and a second verifying operation. Referring to fig. 8, performing a first sub-verify operation on a target memory cell includes applying a first forced sensing voltage Vfc1 to the target memory cell, performing a second sub-verify operation on the target memory cell includes applying a second forced sensing voltage Vfc2 to the target memory cell, performing a third sub-verify operation on the target memory cell includes applying a third forced sensing voltage Vfc3 to the target memory cell, and performing a second verify operation on the target memory cell includes applying a program verify voltage Vvfy to the target memory cell.

In some embodiments, after the first forced sensing voltage Vfc1 is applied to the target memory cell, the first fail bit count of the first sub-verify operation is recorded to count the number of 2BL cells (memory cells that do not pass the first sub-verify operation). And when the first failure bit count is larger than the first preset value, continuing to execute the first sub-verification operation, the second sub-verification operation, the third sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state.

In other embodiments, after the second forced sensing voltage Vfc2 is applied to the target memory cell, a second fail bit count of the second sub-verify operation is recorded to count the number of 2BL cells and 3BL cells (memory cells that do not pass the second sub-verify operation). And when the second failure bit count is larger than the second preset value, continuing to execute the first sub-verification operation, the second sub-verification operation, the third sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state.

In still other embodiments, after the third forced sensing voltage Vfc3 is applied to the target memory cell, a third fail bit count of the third sub-verify operation is recorded to count the number of 2BL cells, 3BL cells, and 4BL cells (memory cells that do not pass the third sub-verify operation). And when the third failure bit count is larger than the third preset value, continuing to execute the first sub-verification operation, the second sub-verification operation, the third sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state.

In some embodiments, the first preset value, the second preset value, and the third preset value may be the same. In other embodiments, the second preset value may be greater than the first preset value and the third preset value may be greater than the second preset value. In a specific example, the first preset value may be 10, the second preset value may be 20, and the third preset value may be 30.

In some embodiments, when the first fail bit count is greater than a first preset value, a bit line forced operation may be performed on the 3BL cell, the 4BL cell, and the 5BL cell in a subsequent programming process. The bit line forced operation in the embodiment of the present disclosure includes a first bit line forced operation, a second bit line forced operation, and a third bit line forced operation. And the 3BL cells may be memory cells to be subjected to a first bit line forced operation, the 4BL cells may be memory cells to be subjected to a second bit line forced operation, and the 5BL cells may be memory cells to be subjected to a third bit line forced operation.

In some embodiments, the peripheral circuitry is further configured to apply a first bit line voltage to a bit line coupled to a memory cell of the target memory cells that does not pass the first sub-verify operation, apply a second bit line voltage to a bit line coupled to a memory cell of the target memory cells that does not pass the second sub-verify operation, apply a fourth bit line voltage to a bit line coupled to a memory cell of the target memory cells that does not pass the third sub-verify operation, apply a fifth bit line voltage to a bit line coupled to a memory cell of the target memory cells that does not pass the third sub-verify operation, apply a third bit line voltage to a bit line coupled to a memory cell of the target memory cells that does not pass the second verify operation, wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage, and the fifth bit line voltage is less than the third bit line voltage.

In the embodiment of the disclosure, a first bit line voltage is applied to a bit line coupled with a 2BL unit, a second bit line voltage is applied to a bit line coupled with a 3BL unit, a fourth bit line voltage is applied to a bit line coupled with a 4BL unit, a fifth bit line voltage is applied to a bit line coupled with a 5BL unit, and a third bit line voltage is applied to a bit line coupled with a forbidden unit, wherein the first bit line voltage is smaller than the second bit line voltage, the second bit line voltage is smaller than the fourth bit line voltage, the fourth bit line voltage is smaller than the fifth bit line voltage, and the fifth bit line voltage is smaller than the third bit line voltage. Here, the first bit line voltage is a normal program bit line voltage Vprog (e.g., a ground voltage Vgnd), the third bit line voltage is a program-inhibit bit line voltage Vinh (e.g., a power supply voltage VDD), and the second, fourth, and fifth bit line voltages are forced program bit line voltages that are greater than the normal program bit line voltage Vprog and less than the program-inhibit bit line voltage Vinh. In one specific example, the second bit line voltage is a program-forced bit line voltage applied when the first bit line program operation is performed, the fourth bit line voltage is a program-forced bit line voltage applied when the second bit line program operation is performed, and the fifth bit line voltage is a program-forced bit line voltage applied when the third bit line program operation is performed. The first, second, fourth, fifth, and third bit line voltages are voltages applied to the bit lines during the programming process.

It should be noted that, when the first failed bit count is less than or equal to the first preset value (i.e., in the case where the first sub-verify operation is not performed), the second bit line voltage is applied to the bit lines coupled to the memory cells that do not pass the second sub-verify operation among the target memory cells. And applying a fourth bit line voltage to bit lines coupled to memory cells that do not pass the third sub-verify operation among the target memory cells when the second fail bit count is less than or equal to a second preset value (i.e., without performing the first and second sub-verify operations). And applying a fifth bit line voltage to bit lines coupled to memory cells that do not pass the second verify operation among the target memory cells when the third fail bit count is less than or equal to a third preset value (i.e., without performing the first, second, and third sub-verify operations).

In the embodiment of the present disclosure, when the first fail bit count is less than or equal to the first preset value (i.e., in the case where the first sub-verify operation is not performed), the 2BL cells are treated as the 3BL cells in the following programming process, in other words, the same first bit line forced operation as the 3BL cells is performed on the 2BL cells in the following programming process. In a specific example, a second bit line voltage is applied to the bit lines to which the 2BL cell and the 3BL cell are coupled in a subsequent programming process. When the second fail bit count is less than or equal to a second preset value (i.e., in the case where the first sub-verify operation and the second sub-verify operation are not performed), the memory cells (2 BL cells and 3BL cells) that do not pass the second sub-verify operation are handled as 4BL cells in the following programming process, in other words, the 2BL cells and 3BL cells are subjected to the same second bit line forced operation as the 4BL cells in the following programming process. In a specific example, a fourth bit line voltage is applied to the bit lines to which the 2BL cell, the 3BL cell, and the 4BL cell are coupled in a subsequent programming process. When the third fail bit count is less than or equal to a third preset value (i.e., in the case where the first, second, and third sub-verify operations are not performed), the memory cells (2, 3, and 4BL cells) that do not pass the third sub-verify operation are treated as 5BL cells in the following programming process, in other words, the same third bit line forced operation as the 5BL cells is performed on the 2, 3, and 4BL cells in the following programming process. In a specific example, a fifth bit line voltage is applied to the bit lines to which the 2BL cell, the 3BL cell, the 4BL cell, and the 5BL cell are coupled in the following programming process.

Based on this, in the embodiment of the disclosure, whether the first verification operation needs to be performed can be determined according to the failed bit count of the first verification operation of the target memory cell, so that the number of unnecessary verification operations is reduced, and further, the programming efficiency can be improved, and the programming verification time can be shortened.

The disclosed embodiments also provide a memory system, the memory system comprising:

one or more memory devices as described in any of the above embodiments, and

A memory controller coupled with and controlling the memory device.

Reference may be made herein to the relevant structure and composition of the memory system in fig. 1, 2a, and 2b as to the specific structure and composition of the memory system. For brevity, no further description is provided herein.

In some embodiments, the memory system comprises a memory card or a solid state disk.

Based on the memory device, the embodiment of the disclosure also provides an operation method of the memory device, wherein the memory device comprises a memory cell array comprising a plurality of memory cells, and the operation method comprises the following steps of:

701, performing target state programming operation on a target storage unit in the plurality of storage units;

Step 702, performing verification operation on a target memory cell subjected to the programming operation of the target state, wherein the verification operation comprises a first verification operation and a second verification operation, and the voltage corresponding to the second verification operation is larger than the voltage corresponding to the first verification operation;

Step 703, recording a failure bit count of the first verification operation in the verification operation process;

Step 704, when it is determined that the failed bit count is less than or equal to the preset value, only the second verify operation is performed in a next verify operation of the program operation of the target state.

In some embodiments, the method further comprises:

And when the failure bit count is determined to be larger than the preset value, executing the first verification operation and the second verification operation in the next verification operation of the programming operation of the target state.

In some embodiments, the first verify operation includes a first sub-verify operation, recording a failed bit count for the first verify operation, and when the failed bit count is determined to be less than or equal to the preset value, performing only the second verify operation in a next verify operation of the program operation for the target state, including:

Recording a first failed bit count for the first sub-verify operation;

And when the first failure bit count is determined to be smaller than or equal to the first preset value, only executing the second verification operation in the next verification operation of the programming operation of the target state.

In some embodiments, the first verify operation includes a first sub-verify operation and a second sub-verify operation, the second sub-verify operation corresponding to a voltage greater than the first sub-verify operation, recording a failed bit count for the first verify operation, and when the failed bit count is determined to be less than or equal to the preset value, performing only the second verify operation in a next verify operation of the program operation for the target state, including:

When the first failed bit count is determined to be less than or equal to the first preset value, only executing the second sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state;

or recording a second failed bit count of the second coarse verify operation, and executing only the second verify operation in a next verify operation of the program operation of the target state when the second failed bit count is determined to be less than or equal to the second preset value.

In some embodiments, the first verify operation includes a first sub-verify operation, a second sub-verify operation, and a third sub-verify operation, the third sub-verify operation corresponding to a voltage greater than the second sub-verify operation, the second sub-verify operation corresponding to a voltage greater than the first sub-verify operation, recording a fail bit count for the first verify operation, and performing only the second verify operation in a next verify operation of the program operation of the target state when the fail bit count is determined to be less than or equal to the preset value, including:

when the first failed bit count is determined to be less than or equal to the first preset value, only executing the second sub-verification operation, the third sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state;

when the second failed bit count is determined to be less than or equal to the second preset value, only executing the third sub-verification operation and the second verification operation in the next verification operation of the programming operation of the target state;

or recording a third failed bit count of the third sub-verify operation, and executing only the second verify operation in a next verify operation of the program operation of the target state when the third failed bit count is determined to be less than or equal to the third preset value.

In some embodiments, the method further comprises:

the method comprises the steps of applying a first bit line voltage to bit lines coupled to memory cells which do not pass a first sub-verification operation in the target memory cells, applying a second bit line voltage to bit lines coupled to the memory cells which pass the first sub-verification operation but do not pass a second verification operation in the target memory cells, and applying a third bit line voltage to bit lines coupled to the memory cells which pass the second verification operation in the target memory cells, wherein the first bit line voltage is smaller than the second bit line voltage, and the second bit line voltage is smaller than the third bit line voltage.

In some embodiments, the method further comprises:

The method comprises the steps of applying a first bit line voltage to bit lines coupled to memory cells which do not pass a first sub-verification operation in the target memory cells, applying a second bit line voltage to bit lines coupled to the memory cells which pass the first sub-verification operation but do not pass a second sub-verification operation in the target memory cells, applying a fourth bit line voltage to bit lines coupled to the memory cells which pass the second sub-verification operation but do not pass the second verification operation in the target memory cells, and applying a third bit line voltage to bit lines coupled to the memory cells which pass the second verification operation in the target memory cells, wherein the first bit line voltage is smaller than the second bit line voltage, the second bit line voltage is smaller than the fourth bit line voltage, and the fourth bit line voltage is smaller than the third bit line voltage.

In some embodiments, the method further comprises:

the method includes applying a first bit line voltage to a bit line of the target memory cells coupled to the memory cells that do not pass the first sub-verify operation, applying a second bit line voltage to a bit line of the target memory cells coupled to the memory cells that do not pass the second sub-verify operation, applying a fourth bit line voltage to a bit line of the target memory cells coupled to the memory cells that do not pass the third sub-verify operation, applying a fifth bit line voltage to a bit line of the target memory cells coupled to the memory cells that do not pass the second sub-verify operation, applying a third bit line voltage to a bit line of the target memory cells coupled to the memory cells that do not pass the second sub-verify operation, wherein the first bit line voltage is less than the second bit line voltage, the second bit line voltage is less than the fourth bit line voltage, the fourth bit line voltage is less than the fifth bit line voltage.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.

Claims

1. A memory device, the memory device comprising:

A memory cell array including a plurality of memory cells;

peripheral circuitry coupled to the array of memory cells, the peripheral circuitry configured to:

Performing target state programming operation on a target storage unit in the storage units;

Performing verification operation on a target memory cell subjected to the programming operation of the target state, wherein the verification operation comprises a first verification operation and a second verification operation, and the voltage corresponding to the second verification operation is larger than the voltage corresponding to the first verification operation;

recording a failure bit count of the first verification operation in the verification operation process;

And when the failure bit count is determined to be smaller than or equal to the preset value, only executing the second verification operation in the next verification operation of the programming operation of the target state.

2. The memory device of claim 1, wherein the peripheral circuitry is further configured to:

3. The memory device of claim 1, wherein the first verify operation comprises a first sub-verify operation, the peripheral circuitry configured to:

Recording a first failed bit count for the first sub-verify operation;

4. The memory device of claim 1, wherein the first verify operation comprises a first sub-verify operation and a second sub-verify operation, the second sub-verify operation corresponding to a voltage greater than the first sub-verify operation corresponding to a voltage, the peripheral circuit configured to:

Or recording a second failed bit count of the second sub-verify operation, and executing only the second verify operation in a next verify operation of the program operation of the target state when the second failed bit count is determined to be less than or equal to the second preset value.

5. The memory device of claim 1, wherein the first verify operation comprises a first sub-verify operation, a second sub-verify operation, and a third sub-verify operation, the third sub-verify operation corresponding to a voltage greater than a voltage corresponding to the second sub-verify operation, the second sub-verify operation corresponding to a voltage greater than the first sub-verify operation, the peripheral circuit configured to:

6. The memory device of claim 3, wherein the peripheral circuitry is further configured to:

7. The memory device of claim 4, wherein the peripheral circuitry is further configured to:

8. The memory device of claim 5, wherein the peripheral circuitry is further configured to:

9. A memory system comprising the memory device according to claim 1 to 8, and

The memory device includes a memory controller coupled to the memory device and configured to control the memory device.

10. A method of operating a memory device, the memory device comprising a memory cell array comprising a plurality of memory cells, the method comprising:

11. The method of operation of a memory device of claim 10, wherein the method further comprises:

12. The method of operation of a memory device of claim 10, the first verify operation comprising a first sub-verify operation, recording a failed bit count for the first verify operation, determining that the failed bit count is less than or equal to the preset value, performing only the second verify operation in a next verify operation of the program operation for the target state, comprising:

Recording a first failed bit count for the first sub-verify operation;

13. The method of claim 10, wherein the first verify operation comprises a first sub-verify operation and a second sub-verify operation, the second sub-verify operation corresponding to a voltage greater than the first sub-verify operation, wherein the recording the failed bit count of the first verify operation, and wherein the determining that the failed bit count is less than or equal to the preset value, in a next verify operation of the program operation for the target state, only the second verify operation is performed comprises:

14. The method of claim 10, wherein the first verify operation comprises a first sub-verify operation, a second sub-verify operation, and a third sub-verify operation, the third sub-verify operation corresponding to a voltage greater than the second sub-verify operation, the second sub-verify operation corresponding to a voltage greater than the first sub-verify operation, recording a failed bit count for the first verify operation, and when the failed bit count is determined to be less than or equal to the preset value, performing only the second verify operation in a next verify operation of the program operation for the target state, comprising:

15. The method of operating a memory device of claim 12, wherein the method further comprises:

16. The method of operating a memory device of claim 13, wherein the method further comprises:

17. The method of operation of a memory device of claim 14, wherein the method further comprises: