CN120568856A - Bidirectional ESD protection device and method of manufacturing the same - Google Patents
Bidirectional ESD protection device and method of manufacturing the sameInfo
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- CN120568856A CN120568856A CN202410206435.5A CN202410206435A CN120568856A CN 120568856 A CN120568856 A CN 120568856A CN 202410206435 A CN202410206435 A CN 202410206435A CN 120568856 A CN120568856 A CN 120568856A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
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Abstract
The invention relates to a bidirectional ESD protection device and a manufacturing method thereof, wherein the device comprises a P-type substrate; the semiconductor device comprises an N-type buried layer, a first P-type region, a P-type buried layer, a second P-type region, a first insulating isolation structure and a second insulating isolation structure, wherein a part of the P-type substrate is positioned below the N-type buried layer, the first P-type region is positioned on the N-type buried layer, a part of the P-type substrate is positioned below the P-type buried layer, the second P-type region is positioned on the P-type buried layer, and the first insulating isolation structure is positioned between the first P-type region and the second P-type region and between the N-type buried layer and the P-type buried layer. According to the invention, the current discharge path of the bidirectional ESD protection device is optimized from the transverse direction to the longitudinal direction, so that the area of the device can be saved, and the current discharge capacity of the device in unit area is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a bidirectional ESD protection device and a method for manufacturing the bidirectional ESD protection device.
Background
ESD (Electro-STATIC DISCHARGE, electrostatic discharge) protection is an important element in the design of ICs (INTEGRATED CIRCUIT, integrated circuits), where ESD protection devices function to protect internal circuits from electrostatic damage.
A bi-directional ESD device is an integral part of an ESD protection circuit for circuit applications, which device needs to meet both positive and negative withstand voltages. In the related art, a lateral PNP transistor with a base floating (floating) is used to realize a positive and negative withstand voltage, in which a positive direction is withstand voltage through a CB (collector-base) junction and a negative direction is withstand voltage through an EB (emitter-base) junction.
The electrostatic protection capability is limited by the capability of discharging current per unit area of the ESD protection device, and it is generally considered that the larger the current that can be discharged per unit area of the ESD protection device, the stronger the electrostatic protection capability. The lateral PNP transistor has a weak capability of discharging current per unit area as a bi-directional ESD device.
Disclosure of Invention
Accordingly, it is necessary to provide a bidirectional ESD protection device having a high capability of discharging current per unit area and a method of manufacturing the same.
A bidirectional ESD protection device comprises a P-type substrate, an N-type buried layer, a first P-type region, a second P-type region, a first insulating isolation structure and a second insulating isolation structure, wherein part of the P-type substrate is positioned below the N-type buried layer, the first P-type region is positioned on the N-type buried layer, part of the P-type substrate is positioned below the P-type buried layer, the second P-type region is positioned on the P-type buried layer, and the first insulating isolation structure is positioned between the first P-type region and the second P-type region and between the N-type buried layer and the P-type buried layer.
According to the bidirectional ESD protection device, the current discharge path of the bidirectional ESD protection device is optimized from the transverse direction to the longitudinal direction, so that the device area can be saved, and the current discharge capacity of the device in unit area is improved.
In one embodiment, the top of the first P-type region is used to connect to an ESD port and the top of the second P-type region is used to ground.
In one embodiment, the bottom depth of the first insulating isolation structure is deeper than the bottom depth of the N-type buried layer and the bottom depth of the P-type buried layer.
In one embodiment, the bidirectional ESD protection device further comprises a first P-type doped region at a bottom of the first insulating isolation structure, wherein a doping concentration of the first P-type doped region is greater than a doping concentration of the P-type substrate.
In one embodiment, a second insulating isolation structure is further included on a side of the first P-type region opposite the first insulating isolation structure.
In one embodiment, the bottom depth of the second insulating isolation structure is deeper than the bottom depth of the N-type buried layer and the bottom depth of the P-type buried layer.
In one embodiment, the bidirectional ESD protection device further includes a second P-type doped region at a bottom of the second insulating isolation structure, the second P-type doped region having a doping concentration greater than a doping concentration of the P-type substrate.
In one embodiment, the first insulating isolation structure is a closed surrounding structure in the transverse direction, and the P-type buried layer and the second P-type region are surrounded by the first insulating isolation structure in the transverse direction.
In one embodiment, the second insulating isolation structure is a closed surrounding structure in the transverse direction, and the N-type buried layer and the first P-type region are surrounded by the second insulating isolation structure in the transverse direction and are located between the second insulating isolation structure and the first insulating isolation structure.
In one embodiment, the bidirectional ESD protection device further comprises a third P-type doped region located at the top of the first P-type doped region, wherein the doping concentration of the third P-type doped region is larger than that of the first P-type doped region, and the first P-type doped region is connected with the ESD port through the third P-type doped region.
In one embodiment, the bidirectional ESD protection device further comprises a fourth P-type doped region, wherein the fourth P-type doped region is positioned on the top of the second P-type doped region, the doping concentration of the fourth P-type doped region is larger than that of the second P-type doped region, and the second P-type doped region is grounded through the fourth P-type doped region.
A manufacturing method of a bidirectional ESD protection device comprises the steps of obtaining a wafer with an N-type buried layer, a P-type buried layer and a P-type region formed on a P-type substrate, wherein the P-type region is located on the N-type buried layer and the P-type buried layer, at least part of the P-type substrate is located below the N-type buried layer and below the P-type buried layer, a groove penetrating through the P-type region is formed, a part of the groove is located between the N-type buried layer and the P-type buried layer, a part of the P-type region located above the N-type buried layer and a part of the P-type region located above the P-type buried layer are separated by the groove, and a first insulating isolation structure is formed in the groove.
In one embodiment, the step of obtaining the wafer with the N-type buried layer, the P-type buried layer and the P-type region formed on the P-type substrate comprises the steps of forming the N-type buried layer and the P-type buried layer in the P-type substrate, forming an epitaxial layer on the P-type substrate, and forming the P-type region in the epitaxial layer.
In one embodiment, the step of forming the trench penetrating through the P-type region comprises the steps of forming a shallow trench isolation structure, enabling the bottom of the shallow trench isolation structure to extend into the P-type region, enabling at least part of the top of the P-type region right above the N-type buried layer to be free of the shallow trench isolation structure, enabling at least part of the top of the P-type region right above the P-type buried layer to be free of the shallow trench isolation structure, forming a patterned hard mask layer on the P-type region, using the hard mask layer as an etching barrier layer, etching the shallow trench isolation structure, and continuing etching the P-type region downwards, and enabling the N-type buried layer and/or the P-type buried layer to form the trench.
In one embodiment, the step of forming the first insulating isolation structure in the groove comprises the steps of depositing an oxide layer in the groove, etching the oxide layer at the bottom of the groove to expose a P-type substrate at the bottom of the groove, filling the oxide layer in the groove to form the first insulating isolation structure, wherein after the step of etching the oxide layer at the bottom of the groove and before the step of filling the oxide layer in the groove, the manufacturing method further comprises the step of forming a first P-type doped region in the P-type substrate below the bottom of the groove through ion implantation, and the doping concentration of the first P-type doped region is larger than that of the P-type substrate.
According to the manufacturing method of the bidirectional ESD protection device, the current discharge path of the bidirectional ESD protection device is optimized from the transverse direction to the longitudinal direction, so that the area of the device can be saved, and the current discharge capacity of the device in unit area is improved.
In one embodiment, the step of forming the trench penetrating the P-type region comprises forming a first trench separating the N-type buried layer from the P-type buried layer, and forming a second trench located on the opposite side of the N-type buried layer from the first trench, the N-type buried layer being located between the first trench and the second trench, and the step of forming the first insulating isolation structure in the trench comprises forming the first insulating isolation structure in the first trench, and forming the second insulating isolation structure in the second trench.
In one embodiment, the step of forming the first P-type doped region in the P-type substrate below the bottom of the groove by ion implantation comprises the steps of forming a first P-type doped region in the P-type substrate below the bottom of the first groove and forming a second P-type doped region in the P-type substrate below the bottom of the second groove, wherein the doping concentration of the second P-type doped region is larger than that of the P-type substrate.
Drawings
For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.
Fig. 1 is a schematic diagram of a bidirectional ESD protection device in an embodiment of the application;
Fig. 2 is a flow path of electrons of the bi-directional ESD protection device shown in fig. 1 when reverse withstand voltage is applied;
FIG. 3 is a top view of a first insulating isolation structure 142 and a second insulating isolation structure 144 according to an embodiment of the present application;
fig. 4 is a flow chart of a method of fabricating a bi-directional ESD protection device in an embodiment of the application;
FIG. 5 is a flow chart of the substeps of step S410 in an embodiment of the application;
fig. 6a to 6h are schematic cross-sectional views of a device during the fabrication of a bi-directional ESD protection device using the method shown in fig. 4;
FIG. 7 is a flow chart of the substeps of step S420 in an embodiment of the application;
FIG. 8 is a flow chart of the substeps of step S520 in an embodiment of the application.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
The application provides a novel bidirectional ESD protection device, which can adjust a current discharge path to be longitudinal while meeting positive and negative withstand voltage, effectively reduce the area of the device and improve the current discharge capacity of the ESD device.
Fig. 1 is a schematic diagram of a bidirectional ESD protection device according to an embodiment of the present application. The bi-directional ESD protection device shown in fig. 1 is left-right symmetric, and thus part of the structure is numbered on one side only. In the embodiment shown in fig. 1, the bi-directional ESD protection device comprises a P-type substrate 110, an N-type buried layer (N-Bury) 122, a P-type buried layer (P-Bury) 124, a first P-type region 132, a second P-type region 133, and a first insulating isolation structure 142. A portion of P-type substrate 110 is located below N-type buried layer 122 and a portion of P-type substrate 110 is located below P-type buried layer 124. The first P-type region 132 is located on the N-type buried layer 122. The second P-type region 133 is located on the P-type buried layer 124. A first insulating isolation structure 142 is located between the first P-type region 132 and the second P-type region 133, and between the N-type buried layer 122 and the P-type buried layer 124.
In the embodiment shown in fig. 1, the top of the first P-type region 132 is used to connect to an ESD port, i.e., to connect to an Anode (Anode) electrode, and the top of the second P-type region 133 is used to connect to Ground (GND), i.e., to connect to a Cathode (Cathode) electrode.
The forward withstand voltage of the bidirectional ESD protection device shown in fig. 1 is the turn-on voltage of the longitudinal PMOS, where the first P-type region 132 is the source region of the PMOS, the P-type substrate 110 under the N-type buried layer 122 is the drain region of the PMOS, the P-type buried layer 124 is the gate of the PMOS, the gate is led out through the second P-type region 133 to be grounded, and the first insulating isolation structure 142 is used as the gate dielectric layer. When an ESD port has an incoming electrostatic surge, the voltage of the first P-type region 132 reaches the turn-on voltage of PMOS, the PMOS is turned on, the device discharges current through a path indicated by an arrow in fig. 1, and the first insulating isolation structure 142 plays a role of blocking the lateral movement of the current. The negative direction of the bidirectional ESD protection device shown in fig. 1 is voltage-resistant through the EB junction (the collector includes the second P-type region 133, the P-type buried layer 124, the P-type substrate 110 under the P-type buried layer 124, and the base is the N-type buried layer 122) of the PNP triode. Referring to fig. 2, when an electrostatic surge arrives at the GND port, the voltage of the second P-type region 133 reaches the turn-on voltage of the PNP transistor, and the PNP transistor is turned on, and the movement direction of electrons in the device is shown by the arrow in fig. 2 (the current flow direction is opposite to the movement direction of electrons). Because the current path is longitudinal, the area of the device can be saved, and the current discharging capability of the device in unit area is improved.
In the embodiment shown in fig. 1, the bottom depth of the first insulating isolation structure 142 is deeper than the bottom depth of the N-type buried layer 122 and the bottom depth of the P-type buried layer 124, i.e., the first insulating isolation structure 142 extends deeper into the P-type substrate 110 than the N-type buried layer 122/P-type buried layer 124 extends into the P-type substrate 110.
In the embodiment shown in fig. 1, the bi-directional ESD protection device further comprises a first P-type doped region 136 at the bottom of the first insulating isolation structure 142. The doping concentration of the first P-type doped region 136 is greater than the doping concentration of the P-type substrate 110. The first P-type doped region 136 can reduce the resistance on the conduction path during the ESD current leakage, and enhance the current leakage capability.
In the embodiment shown in fig. 1, the bi-directional ESD protection device further comprises a second insulating isolation structure 144 located on the opposite side of the first P-type region 132 from the first insulating isolation structure 142.
In one embodiment of the present application, the first insulating isolation structure 142 is a closed surrounding structure in the lateral direction, and the P-type buried layer 124 and the second P-type region 133 are surrounded by the first insulating isolation structure 142 in the lateral direction.
In one embodiment of the present application, the second insulating isolation structure 144 is a closed surrounding structure in the lateral direction, and the N-type buried layer 122 and the first P-type region 132 are surrounded by the second insulating isolation structure 144 in the lateral direction and are located between the second insulating isolation structure 144 and the first insulating isolation structure 142. The second insulating isolation structure 144 functions to electrically isolate the N-type buried layer 122 and the first P-type region 132 from the device structure outside (outside the second insulating isolation structure 144).
Fig. 3 is a top view of a first insulating isolation structure 142 and a second insulating isolation structure 144 according to an embodiment of the present application. In this embodiment, the first insulating isolation structure 142 and the second insulating isolation structure 144 are square frame type, and in other embodiments, the first insulating isolation structure 142/the second insulating isolation structure 144 may be a closed surrounding structure with other shapes, such as a circular ring, an elliptical ring, a racetrack type, etc.
In the embodiment shown in fig. 1, the bottom depth of the second insulating isolation structure 144 is deeper than the bottom depth of the N-type buried layer 122 and the bottom depth of the P-type buried layer 124, i.e., the second insulating isolation structure 144 extends deeper into the P-type substrate 110 than the N-type buried layer 122/P-type buried layer 124 extends into the P-type substrate 110.
In the embodiment shown in fig. 1, the bi-directional ESD protection device further comprises a second P-type doped region 138 at the bottom of a second insulating isolation structure 144. The doping concentration of the second P-type doped region 138 is greater than the doping concentration of the P-type substrate 110. The second P-type doped region 138 serves as an electrical isolation to prevent the N-type buried layer 122 from penetrating the outer device structure (e.g., other N-type region).
In the embodiment shown in fig. 1, the bi-directional ESD protection device further comprises a third P-type doped region 134 located on top of the first P-type region 132. The third P-type doped region 134 has a doping concentration greater than that of the first P-type region 132, and functions to reduce contact resistance. The first P-type region 132 is connected to the ESD port through a third P-type doped region 134.
In the embodiment shown in fig. 1, the bi-directional ESD protection device further comprises a fourth P-type doped region 135 located on top of the second P-type region 133. The doping concentration of the fourth P-type doped region 135 is greater than that of the second P-type region 133, and functions to reduce contact resistance. The second P-type region 133 is grounded through the fourth P-type doped region 135.
In one embodiment of the present application, the material of the first insulating isolation structure 142 is silicon oxide, such as silicon dioxide. In one embodiment of the present application, the material of the second insulating isolation structure 144 is silicon oxide, such as silicon dioxide.
The application correspondingly provides a manufacturing method of the bidirectional ESD protection device, which is used for manufacturing the ESD protection device in any embodiment. Fig. 4 is a flowchart of a method of manufacturing a bi-directional ESD protection device in an embodiment of the application, comprising the steps of:
S410, obtaining a wafer with an N-type buried layer, a P-type buried layer and a P-type region formed on a P-type substrate.
P-type region 130 is situated over N-type buried layer 122 and over P-type buried layer 124, and at least a portion of P-type substrate 110 is situated under N-type buried layer 122 and under P-type buried layer 124.
Referring to fig. 5, in one embodiment of the present application, step S410 includes:
S412, forming an N-type buried layer and a P-type buried layer in the P-type substrate.
Referring to fig. 6a, in one embodiment of the present application, a PAD Oxide layer (PAD Oxide) 141 may be formed on the surface of the P-type substrate 110 of the wafer by thermal oxidation, and then an N-type buried layer 122 and a P-type buried layer 124 may be formed in the P-type substrate 110 after well pushing by patterning (e.g., photolithography) and ion implantation, respectively.
And S414, forming an epitaxial layer on the P-type substrate.
In one embodiment of the present application, after liner oxide 141 is removed, an epitaxial layer is grown on P-type substrate 110, N-type buried layer 122, and P-type buried layer 124.
And S416, forming a P-type region in the epitaxial layer.
Referring to fig. 6b, P-type regions 130 are formed in the epitaxial layer over the N-type buried layer 122 and the P-type buried layer 124 by patterning (e.g., photolithography) and ion implantation (implantation of P-type ions) on the epitaxial layer.
To this end, step S410 is completed, and the process proceeds to step S420.
S420, forming a groove penetrating through the P-type region.
In one embodiment of the application, the bottom of the trench is deeper than the bottoms of the N-type buried layer 122 and the P-type buried layer 124.
Referring to fig. 7, in one embodiment of the present application, step S420 includes:
S422, forming a shallow trench isolation structure.
Patterning (e.g., photolithography and etching) is performed on the front side of the wafer to form shallow trenches, and then an oxide layer is deposited to form shallow trench isolation structures 146. Referring to fig. 6c, the bottom of the shallow trench isolation structure 146 extends into the P-type region 130, at least a portion of the top of the P-type region 130 directly above the N-type buried layer 122 is not formed with the shallow trench isolation structure 146, and at least a portion of the top of the P-type region 130 directly above the P-type buried layer 124 is not formed with the shallow trench isolation structure 146, so that the P-type region 130 is exposed on the front surface of the wafer. In one embodiment of the present application, at least a portion of the shallow trench isolation structure 146 is formed at a location where a Deep Trench Isolation (DTI) structure is desired to be formed in a subsequent step S430.
And S424, forming a patterned hard mask layer on the P-type region.
In one embodiment of the present application, silicon nitride is deposited on the front side of the wafer and then the hard mask layer 152 is formed by patterning (photolithography and etching), see fig. 6d. The exposed window of the hard mask layer 152 is located over the shallow trench isolation structure 146. In one embodiment of the present application, prior to depositing the silicon nitride, a step of forming a PAD Oxide (not labeled in fig. 6 d) on the front side of the wafer is further included, on which the silicon nitride is deposited.
S426, etching to form a groove by taking the hard mask layer as an etching barrier layer.
After etching through shallow trench isolation structure 146, P-type region 130, and N-type buried layer 122 and/or P-type buried layer 124 continue to be etched downward to form trench 131, see fig. 6e. In the embodiment shown in fig. 6e, the trenches 131 include a first trench 131a separating the N-type buried layer 122 from the P-type buried layer 124, and a second trench 131b located outside the N-type buried layer 122 (i.e., on the opposite side of the N-type buried layer 122 from the first trench 131 a). The first trench 131a separates the P-type region 130 into a first P-type region 132 on the N-type buried layer 122 and a second P-type region 133 on the P-type buried layer 124.
In one embodiment of the present application, the bottom depth of trench 131 is deeper than the bottom depth of N-type buried layer 122 and the bottom depth of P-type buried layer 124.
Thus, step S420 is completed, and the process proceeds to step S430.
And S430, forming a first insulating isolation structure in the groove.
Referring to fig. 8, in one embodiment of the present application, step S430 includes:
S432, depositing an oxide layer into the groove.
In one embodiment of the present application, an oxide layer 143 is deposited into the first trench 131a and the second trench 131b, see fig. 6f.
S434, etching the oxide layer at the bottom of the groove to expose the P-type substrate at the bottom of the groove.
In one embodiment of the present application, the bottom P-type substrate 110 is exposed by removing the oxide layer 143 at the bottom of the trench first trench 131a and the trench second trench 131b by etching.
In one embodiment of the present application, after exposing the P-type substrate 110 at the bottom of the trench 131, a first P-type doped region 136 is formed in the P-type substrate 110 below the bottom of the first trench 131a by ion implantation (implanting P-type ions), and a second P-type doped region 138 is formed in the P-type substrate 110 below the bottom of the second trench 131b, as shown in fig. 6g. The doping concentration of the first P-type doped region 136 and the second P-type doped region 138 is greater than the doping concentration of the P-type substrate 110.
And S436, filling an oxide layer into the groove to form a first insulating isolation structure.
In one embodiment of the application, the oxide layer is filled into the trench and etched back. Further, the top surface of the oxide layer after the etching back may be slightly higher than the top surface of the shallow trench isolation structure 146.
In the embodiment shown in fig. 6h, the first trench 131a is filled with an oxide layer to form the first insulating isolation structure 142, and the second trench 131b is filled with an oxide layer to form the second insulating isolation structure 144. The first insulating isolation structure 142 separates the first P-type region 132 from the second P-type region 133, and separates the N-type buried layer 122 from the P-type buried layer 124.
According to the manufacturing method of the bidirectional ESD protection device, the current discharge path of the bidirectional ESD protection device is optimized from the transverse direction to the longitudinal direction, so that the area of the device can be saved, and the current discharge capacity of the device in unit area is improved.
In one embodiment of the present application, a step of removing the hard mask layer 152 is further included after step S436. In particular by etching. In one embodiment of the present application, after the step of removing the hard mask layer 152, a third P-type doped region 134 is formed on top of the first P-type region 132 and a fourth P-type doped region 135 is formed on top of the second P-type region 133 by patterning (e.g., photolithography) and ion implantation (P-type ion implantation). The device structure after this step is completed can be seen in fig. 1. The doping concentration of the third P-type doped region 134 is greater than the doping concentration of the first P-type region 132, and the doping concentration of the fourth P-type doped region 135 is greater than the doping concentration of the second P-type region 133.
The method for manufacturing a bidirectional ESD protection device according to the present application is based on the same inventive concept as the bidirectional ESD protection device, and the description of the bidirectional ESD protection device is referred to above without specific explanation in the method for manufacturing the bidirectional ESD protection device.
It should be understood that, although the steps in the flowcharts of the present application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of this application may include a plurality of steps or stages that are not necessarily performed at the same time but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternately with at least a portion of the steps or stages in other steps or others.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (12)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410206435.5A CN120568856A (en) | 2024-02-23 | 2024-02-23 | Bidirectional ESD protection device and method of manufacturing the same |
| PCT/CN2024/133072 WO2025175846A1 (en) | 2024-02-23 | 2024-11-20 | Bidirectional esd protection device and manufacturing method therefor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410206435.5A CN120568856A (en) | 2024-02-23 | 2024-02-23 | Bidirectional ESD protection device and method of manufacturing the same |
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| CN120568856A true CN120568856A (en) | 2025-08-29 |
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| CN202410206435.5A Pending CN120568856A (en) | 2024-02-23 | 2024-02-23 | Bidirectional ESD protection device and method of manufacturing the same |
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| Country | Link |
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| CN (1) | CN120568856A (en) |
| WO (1) | WO2025175846A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119943745A (en) * | 2025-01-06 | 2025-05-06 | 上海华虹宏力半导体制造有限公司 | Isolation structure and method for forming the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10002861B2 (en) * | 2016-06-23 | 2018-06-19 | Nxp Usa, Inc. | ESD protection structure |
| CN108933131B (en) * | 2018-07-18 | 2021-05-04 | 深圳市海纳微传感器技术有限公司 | Interface protection device and manufacturing method thereof |
| CN117116968A (en) * | 2023-06-26 | 2023-11-24 | 上海维安半导体有限公司 | A low capacitance transient voltage suppressor and its manufacturing method |
-
2024
- 2024-02-23 CN CN202410206435.5A patent/CN120568856A/en active Pending
- 2024-11-20 WO PCT/CN2024/133072 patent/WO2025175846A1/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119943745A (en) * | 2025-01-06 | 2025-05-06 | 上海华虹宏力半导体制造有限公司 | Isolation structure and method for forming the same |
| CN119943745B (en) * | 2025-01-06 | 2025-11-14 | 上海华虹宏力半导体制造有限公司 | Isolation Structure and Its Formation Method |
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|---|---|
| WO2025175846A1 (en) | 2025-08-28 |
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