CN120526817A - A single-power storage and computing integrated data selector with scalable data selection - Google Patents
A single-power storage and computing integrated data selector with scalable data selectionInfo
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- CN120526817A CN120526817A CN202510445359.8A CN202510445359A CN120526817A CN 120526817 A CN120526817 A CN 120526817A CN 202510445359 A CN202510445359 A CN 202510445359A CN 120526817 A CN120526817 A CN 120526817A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
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Abstract
本发明公开了一种选择数据可扩展的单电源存算一体数据选择器，其包括：预充电路，其输入端连接至电源信号输入端、控制端接入预充控制信号、输出端与输出驱动电路的输入端连接；至少两个基本数据输入电路，每个基本数据输入电路由一个铁电晶体管、一个nMOS晶体管和一个pMOS晶体管组成，铁电晶体管的漏极与输出驱动电路的输入端连接、源极分别与nMOS晶体管和pMOS晶体管的漏极连接、栅极接入数据选择控制信号，nMOS晶体管的源极接入数据输入信号、栅极接入数据选择控制信号，pMOS晶体管的源极接至电源信号输入端、栅极接入数据选择控制信号；优点是采用单电源供电方式，降低了外部电源电路的复杂性，同时可以方便实现输入端的扩展，进而实现多选一数据选择功能。
The present invention discloses a single-power storage and computing integrated data selector with expandable data selection, comprising: a precharging circuit, an input end of which is connected to a power signal input end, a control end connected to a precharging control signal, and an output end connected to an input end of an output driving circuit; at least two basic data input circuits, each of which is composed of a ferroelectric transistor, an nMOS transistor, and a pMOS transistor, the drain of the ferroelectric transistor being connected to the input end of the output driving circuit, the source being connected to the drains of the nMOS transistor and the pMOS transistor respectively, and the gate being connected to a data selection control signal, the source of the nMOS transistor being connected to the data input signal and the gate being connected to the data selection control signal, and the source of the pMOS transistor being connected to the power signal input end and the gate being connected to the data selection control signal; the advantage is that a single-power supply mode is adopted, which reduces the complexity of the external power supply circuit, and at the same time can easily realize the expansion of the input end, thereby realizing a multiple-selection data selection function.
Description
Technical Field
The invention relates to a memory integrated logic circuit, in particular to a single power memory integrated data selector with extensible selection data.
Background
The advent of computers marks the entrance of humans into the information age, while the earliest proposed von neumann computer architecture is classical, the disadvantage is gradually revealed in the big data and artificial intelligence age due to the proliferation of data processing capacity. In von neumann computer architecture, the cpu is separated from the memory storage unit, and as the cpu performance increases, the execution speed of the cpu exceeds the memory access speed, resulting in a "memory wall" bottleneck, limiting the increase in system performance. In addition, the frequent transfer of data between the memory and the central processor not only increases the delay, but also consumes a lot of energy, creating a "power wall" problem. According to intel research, when the semiconductor process reaches 7nm, the proportion of data carrying power consumption to total power consumption is up to 63.7%, and it can be seen that the traditional von neumann computer architecture can cause a great amount of energy waste under the prior manufacturing process. Therefore, developing a storage and computing integrated architecture is an effective approach to solve the two technical problems.
The integrated architecture of memory and calculation fundamentally eliminates the data transmission path, minimizes delay, eliminates the data transmission power consumption and solves the problem that the data transmission frequency is not matched with the data receiving frequency by physically integrating the memory unit and the calculation unit. The integrated architecture enables the computing unit to directly access the data in the storage unit, avoids the process of frequent transmission of the data between the memory and the central processor in the architecture of the traditional von Neumann computer architecture, and improves the computing efficiency. By integrating the calculation and storage functions, the integrated architecture reduces the number and complexity of chip components and reduces the production cost. Because the data is calculated and stored in the chip, the possibility that the data is intercepted or tampered in the transmission process is reduced, and the data security is improved.
The implementation devices of the integrated circuit are divided into volatile devices and nonvolatile devices. Volatile devices such as SRAM, DRAM, etc. based on conventional MOS transistor designs, and nonvolatile devices store data in the form of physical quantities using physical effects, rather than volatile electrical signals. Novel nonvolatile memory devices include memristors, spin transfer torque magnetic memory devices, phase change memory devices, ferroelectric transistors (FeFETs), and the like. The FeFET has advantages of low power consumption and high on-off ratio due to research of hafnium oxide material and its combined structure of MOS substrate and gate capacitor compatible with mature CMOS process, and has become one of the technological development trends of integrated architecture and circuit design.
The data selector is a widely used circuit in digital logic circuits, and has a plurality of data inputs, a plurality of data selects, and a data output. The data selection function is completed by controlling the logic combination of input signals of the data selection terminals and selecting the selected data output of the corresponding data input terminals. In modern circuit design, the application of the data selector is wide, namely the data selector is used for address decoding in a memory and a register, converting an address signal into a control signal to access a specific storage position, is used for switching a plurality of user signal shared channels in a wireless communication system, is used for selecting different processing modules to operate according to different image processing requirements in an image processing system, is used for configuring and outputting different data in an FPGA structure to complete interaction among different modules, and is used for translating, mapping and optimizing circuit logic functions in the form of binary decision diagrams in a logic synthesis technology.
However, the present integrated data selector based on FeFET design has two problems, namely, a plurality of power supplies are generally used, such as a high-amplitude voltage source is used in the FeFET polarization writing stage, and a logic signal is generated by a low-amplitude voltage source, so that the complexity of circuit design is increased due to the use of multiple power supplies, and the level value of performing a writing operation on the FeFET by adopting the integrated FeFET memory circuit with multiple power supplies is different from the level value representing the logic signal, so that the logic output signal of the circuit cannot be directly used for the writing operation on the FeFET, and further the complexity of implementing the integrated logic function is increased.
Disclosure of Invention
The invention aims to provide a single power supply and calculation integrated data selector with extensible selection data, which adopts a single power supply mode to enable a level value for executing writing operation on a ferroelectric transistor to have the same size as a level value representing a logic signal, and can realize data selection operation and simultaneously store a data selection result in a nonvolatile way.
The technical scheme adopted by the invention for solving the technical problems is that the single power source storage and calculation integrated data selector with expandable selection data is characterized by comprising the following components:
the input end of the pre-charging circuit is connected to the input end of the power supply signal, the control end of the pre-charging circuit is connected with the pre-charging control signal, and the output end of the pre-charging circuit is connected with the input end of the output driving circuit and is used for charging the input end of the output driving circuit to a high level under the action of the pre-charging control signal so as to provide stable initial conditions for data selection and calculation operation;
The system comprises at least two basic data input circuits, wherein each basic data input circuit consists of a ferroelectric transistor, an nMOS transistor and a pMOS transistor, the drain electrode of the ferroelectric transistor is connected with the input end of the output driving circuit, the source electrode of the ferroelectric transistor is connected with the drain electrodes of the nMOS transistor and the pMOS transistor respectively, the grid electrode of the ferroelectric transistor is connected with a data selection control signal and is used for selecting the data input signal according to the data selection control signal, the source electrode of the nMOS transistor is connected with the data input signal and the grid electrode of the nMOS transistor is connected with the data selection control signal and is used for controlling the transmission of the data input signal under the action of the data selection control signal, the source electrode of the pMOS transistor is connected with the power signal input end and the grid electrode of the data selection control signal and is used for transmitting a high-level signal under the action of the data selection control signal, the polarization state of a ferroelectric layer of the ferroelectric transistor is used for storing data selection results, the complexity of the circuit can be effectively reduced by utilizing the complementary working characteristics of the nMOS transistor and the pMOS transistor, the complexity of the circuit can be simultaneously transmitted by the MOS transistor, the power signal is not only enhanced, and the signal integrity of the circuit is improved.
And the output driving circuit is used for outputting a data selection result after nonvolatile storage according to the level state after the pre-charging and the storage state of the ferroelectric transistor.
In addition, to ensure that the nMOS transistor, pMOS transistor and ferroelectric transistor are functioning properly, the substrates of all nMOS transistor and ferroelectric transistor in the data selector are grounded, and the substrate of pMOS transistor is grounded high. Normally, the grounding or power supply of the substrates of the nMOS transistor, the ferroelectric transistor, and the pMOS transistor is default, and is not specifically shown in the circuit diagram, and therefore, in the circuit diagram of the present invention, the grounding or power supply of the substrates of the nMOS transistor, the pMOS transistor, and the ferroelectric transistor is not shown.
The data selector has:
The m data input ends are used for accessing different data input signals, wherein m is more than or equal to 2;
One of the power signal inputs for providing a stable power supply voltage to the precharge circuit, the basic data input circuit, and the output driver circuit, and a power supply voltage to the substrates of all pMOS transistors in the data selector;
A ground signal input terminal providing a stable ground for the output driver circuit and a ground for the substrates of all nMOS transistors and ferroelectric transistors in the data selector;
the precharge control signal input end is used for accessing a precharge control signal;
the m data selection control signal input ends are used for accessing different data selection control signals;
the data output end is used for outputting the data selection result after nonvolatile storage;
The number of the basic data input circuits is m, and m is one data selector.
When the data selector is designed as a chip or an integrated module, the data input end, the power supply signal input end, the grounding signal input end, the pre-charge control signal input end, the data selection control signal input end and the data output end can be designed as external pins, and the number of basic data input circuits is 2 or more generally, so that the two-in-one data selector or the one-out-of-more data selector is formed.
The pre-charging circuit is composed of a pre-charging pMOS transistor, wherein the source electrode of the pre-charging pMOS transistor is used as the input end of the pre-charging circuit, the grid electrode of the pre-charging pMOS transistor is used as the control end of the pre-charging circuit and is used for being connected with the pre-charging control signal input end, and the drain electrode of the pre-charging pMOS transistor is used as the output end of the pre-charging circuit. When the precharge control signal (CTRL) is at a low level, the precharge pMOS transistor is turned on to charge the input terminal of the output drive circuit to a high level, and when the precharge control signal (CTRL) is at a high level, the precharge pMOS transistor is turned off to stop the charging operation.
The output driving circuit is composed of a first inverter and a second inverter, wherein the input end of the first inverter is used as the input end of the output driving circuit, the input end of the second inverter is connected with the output end of the first inverter, and the output end of the second inverter is used as the output end of the output driving circuit and is connected with the data output end. Two inverters are used to buffer and stabilize the output signal.
In the ith basic data input circuit, the gate of the ferroelectric transistor, the gate of the nMOS transistor, and the gate of the pMOS transistor are all connected to the ith data selection control signal input terminal, the source of the nMOS transistor is connected to the ith data input terminal, where i=1, 2, m, the drain of the nMOS transistor is connected to the source of the ferroelectric transistor, the drain of the pMOS transistor is connected to the source of the ferroelectric transistor, the source of the pMOS transistor is connected to the power signal input, and the drain of the ferroelectric transistor is connected to the output of the precharge circuit.
Compared with the prior art, the invention has the advantages that:
1) The invention adopts a single power supply mode, the precharge circuit, the basic data input circuit and the output drive circuit are all powered by the same power supply, the design obviously reduces the complexity of an external power supply circuit, reduces the design difficulty and cost of a power management module, and ensures that the level value for executing the write operation on the ferroelectric transistor has the same size as the level value for representing the logic signal, thereby ensuring that the implementation of the logic function of the memory integration is simpler.
2) The invention realizes the storage of the data selection result through the ferroelectric transistor, ensures that the data can still be kept stable after power failure, solves the problem of volatile output of the data selector in the prior art, and improves the safety and reliability of the data.
3) The invention supports the expansion of the one-out-of-multiple data selector, can flexibly adapt to different data selection demands by increasing the number of the basic data input circuits, and has good universality and expandability.
4) The invention reduces unnecessary signal transmission and level conversion in the process of data selection and calculation by the cooperative work of the precharge circuit and the ferroelectric transistor, thereby reducing the power consumption.
5) The precharge circuit charges the input end of the output drive circuit to a high level under the action of the precharge control signal, and provides stable initial conditions for data selection and calculation operation.
Drawings
FIG. 1 is a schematic symbol diagram of a pMOS transistor;
fig. 2 is a schematic symbol diagram of an nMOS transistor;
FIG. 3 is a schematic diagram of a symbol of an n-type ferroelectric transistor (FeFET);
FIG. 4 is a schematic diagram of an inverter;
FIG. 5 is a schematic circuit diagram of an alternative data selector according to the first embodiment;
FIG. 6 is a schematic circuit diagram of an alternative data selector according to the second embodiment;
Fig. 7 is a schematic diagram of simulation results of the circuit shown in fig. 6, wherein A, B, C is a selected data input signal, G A、GB、GC is a data selection control signal, CTRL is a precharge control signal, OUT is a data selection result, and P 1、P2、P3 is the polarization states (ON/OFF) of the ferroelectric layers of the three n-type ferroelectric transistors, respectively.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown.
The invention provides a single-power-supply calculation integrated data selector capable of expanding selection data, which utilizes a pMOS transistor as a precharge pMOS transistor to form a precharge circuit, utilizes a ferroelectric transistor, an nMOS transistor and a pMOS transistor to form a basic data input circuit, utilizes two inverters to form an output driving circuit, and then connects the precharge circuit, the output driving circuit and a plurality of basic data input circuits according to a certain rule, so that the single-power-supply calculation integrated data selector with a plurality of data input signals can be realized, namely the number of data input ends can be expanded, and the signal for realizing 'writing' operation on FeFEFETs is the same as the level value of a logic '1' signal, so that the whole circuit only needs one power supply. The ferroelectric transistor in the invention is an n-type ferroelectric transistor. The power supply voltage used in the present invention is 5V, the ground voltage is 0V, and the voltage signal is in a logic "1" state when the voltage signal quantity is more than 3.5V and in a logic "0" state when the voltage signal quantity is less than 1.5V in the following description.
Fig. 1 shows a schematic symbol of a pMOS transistor, g pm denotes the gate of the pMOS transistor, d pm denotes the drain of the pMOS transistor, s pm denotes the source of the pMOS transistor, the conduction between d pm and s pm of the pMOS transistor depends on whether the voltage difference between g pm and s pm is smaller than the threshold voltage of the pMOS transistor, d pm and s pm being in the on state if the voltage difference between g pm and s pm is smaller than the threshold voltage of the pMOS transistor, and conversely, d pm and s pm being in the off state if the voltage difference between g pm and s pm is larger than the threshold voltage of the pMOS transistor.
Fig. 2 shows a schematic symbol of an nMOS transistor, g nm denotes a gate of the nMOS transistor, d nm denotes a drain of the nMOS transistor, s nm denotes a source of the nMOS transistor, the conduction between d nm and s nm of the nMOS transistor depends on whether the voltage difference between g nm and s nm is larger than the threshold voltage of the nMOS transistor, d nm and s nm are in an on state if the voltage difference between g nm and s nm is larger than the threshold voltage of the nMOS transistor, and conversely, d nm and s nm are in an off state if the voltage difference between g nm and s nm is smaller than the threshold voltage of the nMOS transistor.
Fig. 3 shows a schematic symbol of an n-type FeFET, g f denotes the gate of the FeFET, d f denotes the drain of the FeFET, s f denotes the source of the FeFET, P denotes the ferroelectric layer polarization state of the FeFET, whether P is ON or OFF depends ON the last voltage difference applied between g f and s f, P is set ON when the voltage between g f and s f is greater than the threshold for polarization switching to low resistance, P is set to ON, this state is held at this time, d f and s f is set to low resistance ON, and P is set OFF when the voltage between g f and s f is less than the threshold for polarization switching to high resistance, this state is held at this time, P is set to OFF, this state is set to high resistance OFF between d f and s f, and the state P of the FeFET will remain unchanged after the voltages of g f、df and s f are removed.
In order to ensure that the nMOS transistor, the pMOS transistor and the ferroelectric transistor work normally, the substrates of the nMOS transistor and the ferroelectric transistor are grounded, and the substrate of the pMOS transistor is connected with a high level.
Fig. 4 shows a schematic diagram of an inverter, in is an input terminal of the inverter, out is an output terminal of the inverter, and out is an inverse of in, when the power voltage is 5V, in general, when the voltage of in is greater than 3.5V, it indicates that the logic represented by in is logic "1", where out is logic "0", corresponding to the voltage of about 0V, and when the voltage of in is less than 1.5V, it indicates that the logic represented by in is logic "0", where out is logic "1", corresponding to the voltage of about 5V.
Embodiment one:
The single power source integrated two-in-one data selector with expandable selection data provided by the embodiment is shown in fig. 5, and comprises a pre-charging circuit 1, wherein the input end of the pre-charging circuit 1 is connected to the input end of a power source signal, the control end of the pre-charging circuit is connected with a pre-charging control signal CTRL, and the output end of the pre-charging circuit is connected with the input end of an output driving circuit 3, so that the input end of the output driving circuit 3 is charged to a high level under the action of the pre-charging control signal CTRL, and stable initial conditions are provided for data selection and calculation operation. Two basic data input circuits, respectively defined as a first basic data input circuit 21 and a second basic data input circuit 22, the first basic data input circuit 21 is composed of a first ferroelectric transistor f 1, a first nMOS transistor nm 1 and a first pMOS transistor pm 1, and the second basic data input circuit 22 is composed of a second ferroelectric transistor f 2, The second nMOS transistor nm 2 and the second pMOS transistor pm 2, the drains of the first ferroelectric transistor f 1 and the second ferroelectric transistor f 2 are connected with the input end of the output driving circuit 3, the source electrode of the first ferroelectric transistor f 1 is connected with the drain electrodes of the first nMOS transistor nm 1 and the first pMOS transistor pm 1 respectively, the gate electrode of the first ferroelectric transistor f 1 is connected with a first data selection control signal G A for selecting a first data input signal A according to the first data selection control signal G A, the source electrode of the second ferroelectric transistor f 2 is connected with the drain electrodes of the second nMOS transistor nm 2 and the second pMOS transistor pm 2 respectively, the gate electrode of the second ferroelectric transistor f 2 is connected with a second data selection control signal G B for selecting a second data input signal B according to the second data selection control signal G B, the source electrode of the first ferroelectric transistor nm 1 is connected with a first data selection control signal G A, the source electrode of the first nMOS transistor f 1 is connected with a second data selection signal A, the source electrode of the second ferroelectric transistor f A is connected with the second data selection control signal A, the source electrode of the second ferroelectric transistor f 3938 is connected with the second data selection signal G A, the source electrode of the second pMOS transistor pm 2 is connected to the power signal input terminal, and the gate electrode of the second pMOS transistor pm 2 is connected to the second data selection control signal G B, for transmitting the high level signal under the action of the second data selection control signal G B. And an output driving circuit 3 for outputting a data selection result OUT after nonvolatile storage according to the level state after the precharge and the storage states of the first ferroelectric transistor f 1 and the second ferroelectric transistor f 2. the ferroelectric layer polarization state P 1 of the first ferroelectric transistor f 1 and the ferroelectric layer polarization state P 2 of the second ferroelectric transistor f 2 are used for storing logic states of data selection results, so that a nonvolatile memory function is realized, the complexity of a circuit can be effectively reduced by utilizing the complementary working characteristics of an nMOS transistor and a pMOS transistor, and meanwhile, the pMOS transistor transmits a power supply signal, so that the driving capability of the circuit is enhanced, and the signal integrity is improved.
In addition, to ensure that the nMOS transistors, pMOS transistors and ferroelectric transistors operate normally, the substrates of all nMOS transistors and ferroelectric transistors in the data selector are grounded, i.e., connected to the ground signal input terminal, and the substrates of the pMOS transistors are high, i.e., connected to the power signal input terminal. Normally, the grounding or power supply of the substrates of the nMOS transistor, the ferroelectric transistor, and the pMOS transistor is default, and is not specifically shown in the circuit diagram, and therefore, in the circuit diagram 5 of the present invention, the grounding or power supply of the substrates of the nMOS transistor, the pMOS transistor, and the ferroelectric transistor is not shown.
It is further defined that the data selector has two data inputs, namely a first data input and a second data input for accessing different data input signals, namely a first data input signal a and a second data input signal B, one power supply signal input for providing the precharge circuit 1, the first basic data input circuit 21, the second basic data input circuit 22 and the output drive circuit 3 with a stable power supply voltage VDD and the substrates of all pMOS transistors in the data selector, one ground signal input for providing the output drive circuit 3 with a stable ground and the substrates of all nMOS transistors and ferroelectric transistors in the data selector with a precharge control signal input for accessing the precharge control signal CTRL, two data selection control signal inputs, namely a first data selection control signal input and a second data selection control signal input for accessing different data selection control signals, namely a first data selection control signal G A and a second data selection control signal G B, and one output for outputting the data selection result after the nonvolatile storage. The data selector is designed as a chip or an integrated module, and the data input end, the power supply signal input end, the grounding signal input end, the pre-charge control signal input end, the data selection control signal input end and the data output end can be designed as external pins.
Further defined, the pre-charge circuit 1 is composed of a pre-charge pMOS transistor pm 0, the source of the pre-charge pMOS transistor pm 0 being the input of the pre-charge circuit 1 and being connected to the power signal input, the gate being the control terminal of the pre-charge circuit 1 and being connected to the pre-charge control signal input, and the drain being the output of the pre-charge circuit 1. When the precharge control signal CTRL is at a low level, the precharge pMOS transistor pm 0 is turned on to charge the input terminal of the output driving circuit 3 to a high level, and when the precharge control signal CTRL is at a high level, the precharge pMOS transistor pm 0 is turned off to stop the charging operation.
Further defined, the output driving circuit 3 is composed of a first inverter INV1 and a second inverter INV2, the input end of the first inverter INV1 is used as the input end of the output driving circuit 3 and is connected with the output end of the precharge circuit 1, the input end of the second inverter INV2 is connected with the output end of the first inverter INV1, and the output end of the second inverter INV2 is used as the output end of the output driving circuit 3 and is used for being connected with the data output end. Two inverters are used to buffer and stabilize the output signal.
Further defined, the gates of the first ferroelectric transistor f 1, the first nMOS transistor nm 1, and the first pMOS transistor pm 1 are each connected to a first data selection control signal input, the source of the first nMOS transistor nm 1 is connected to a first data input, the gates of the second ferroelectric transistor f 2, the second nMOS transistor nm 2, and the second pMOS transistor pm 2 are each connected to a second data selection control signal input, and the source of the second nMOS transistor nm 2 is connected to a second data input.
Embodiment two:
In the single power source integrated three-one data selector with expandable selection data provided in this embodiment, as shown in fig. 6, compared with the two-one data selector shown in fig. 5, the three-one data selector shown in fig. 6 has one additional basic data input circuit, i.e. the three-one data selector can be implemented by adding one basic data input circuit to the two-one data selector. The added basic data input circuit is defined as a third basic data input circuit 23, the third basic data input circuit 23 being formed by a third ferroelectric transistor f 3, The third nMOS transistor nm 3 and the third pMOS transistor pm 3, the drain electrode of the third ferroelectric transistor f 3 is connected with the input end of the output driving circuit 3, the source electrode of the third ferroelectric transistor f 3 is respectively connected with the drain electrodes of the third nMOS transistor nm 3 and the third pMOS transistor pm 3, the grid electrode of the third ferroelectric transistor f 3 is connected with the third data selection control signal G C for selecting the third data input signal C according to the third data selection control signal G C, the source electrode of the third nMOS transistor nm 3 is connected with the third data input signal C, the grid electrode of the third nMOS transistor nm 3 is connected with the third data selection control signal G C for controlling the transmission of the third data input signal C under the action of the third data selection control signal G C, the source electrode of the third ferroelectric transistor pm 3 is connected with the power supply signal input end, and the grid electrode of the third pMOS transistor pm 3 is connected with the third data selection control signal G C for transmitting the high-level signal under the action of the third data selection control signal G C. The output driving circuit 3 is configured to output the data selection result OUT after nonvolatile storage according to the level state after the precharge and the storage states of the first ferroelectric transistor f 1, the second ferroelectric transistor f 2, and the third ferroelectric transistor f 3. Here, the ferroelectric layer polarization state P 3 of the third ferroelectric transistor f 3 is also used to store a part of the logic states of the data selection result, and the nonvolatile memory function is realized.
Further defined, the data input and the data selection control signal input of the data selector are each extended by two to three, the extended data input being the third data input, and the extended data selection control signal input being the third data selection control signal input.
Further defined, gates of the third ferroelectric transistor f 3, the third nMOS transistor nm 3, and the third pMOS transistor pm 3 are all connected to a third data selection control signal input terminal, and a source of the third nMOS transistor nm 3 is connected to a third data input terminal.
To further illustrate the feasibility and effectiveness of the present invention, a simulation experiment was performed on the one-out-of-three data selector shown in fig. 6.
Fig. 7 is a simulation result of the one-out-of-three data selector shown in fig. 6, where the name of each signal waveform in fig. 7 is listed at the leftmost side and corresponds to one-to-one in fig. 6, where P 1、P2 and P 3 correspond to the ferroelectric layer polarization states of the first ferroelectric transistor f 1, the second ferroelectric transistor f 2, and the third ferroelectric transistor f 3. In fig. 7, from the period T1 to the period T16, each period corresponds to one high level period or one low level period of CTRL, and 16 periods are divided into 8 operation periods in a group of every two periods, and each operation period has a period of the even number and the precharge and write 0 steps, and the calculation and output steps are completed in the following period.
The first operation period includes a T1 period and a T2 period. In the T1 period, A is 5V, B is 5V, C is 5V, G A is 0V, G B is 0V, G C is 0V, and therefore the first and second and third pMOS transistors pm 1, pm 2, pm 3 are both on, the first and second nMOS transistors nm 1, nm 2, and nm 3 are both off, the first ferroelectric transistor f 1, A second ferroelectric transistor f 2, The source voltage of the third ferroelectric transistor f 3 is the power supply voltage VDD, namely 5V, at this time, the voltage difference between the grid and the source of each ferroelectric transistor is-5V, so that the polarization state of the ferroelectric layers of the three ferroelectric transistors is in the OFF state, the three ferroelectric transistors are in the high-resistance state, the voltage of CTRL is 0V, thus the pre-charge pMOS transistor pm 0 is conducted, VDD charges the input end of the first inverter INV1, the voltage of OUT obtained after the output of the two inverters is 5V, CTRL is switched to 5V in the period of T2, the pre-charge pMOS transistor pm 0 is turned OFF, VDD does not charge the input end of the first inverter INV1 any more, A, The voltages of B and C are kept 5V, the voltage of G A is switched to 5V (a is selected as OUT for output), the voltage of G B and G C are kept 0V, so that the first pMOS transistor pm 1 is turned off, the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are both turned on, the first nMOS transistor nm 1 is turned on, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are both turned off, the voltage difference between the gate and source of the first ferroelectric transistor f 1 is close to 0V, and the ferroelectric layer polarization state P 1 of the first ferroelectric transistor f 1 is kept in the previous state, i.e., the high-resistance state; in addition, the source voltage of the second ferroelectric transistor f 2 and the source voltage of the third ferroelectric transistor f 3 are both 5V, so the voltage difference between the gates and the sources of the second ferroelectric transistor f 2 and the third ferroelectric transistor f 3 is-5V, and the two ferroelectric transistors are in a high-resistance state, and the three ferroelectric transistors are in a high-resistance state, so the charge at the input end of the first inverter INV1 is kept at a level after being precharged for a period of T1, the voltage of OUT is kept at 5V and is consistent with the voltage of the selected A, and the operation of A, OUT is completed, and B and C are one-out-of-three data selection function of A.
The second operation period includes a T3 period and a T4 period. In the period of T3, the voltage of A is 5V, the voltage of B is 5V, the voltage of C is 0V, the voltage of G A is 0V, the voltage of G B is 0V, the voltage of G C is 0V, therefore, the first pMOS transistor pm 1, the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are all on, the first nMOS transistor nm 1, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are all OFF, the source voltage of the three ferroelectric transistors is the power supply voltage VDD, namely 5V, at this time, the voltage difference between the grid and the source of each ferroelectric transistor is 5V, the polarization state of the ferroelectric layers of the three ferroelectric transistors is in the OFF state, and meanwhile, in the period of T3, the voltage of CTRL is 0V, therefore, the pre-charge pMOS transistor pm 0 is on, the input end of the first inverter INV1 is charged, and the output voltage of VDD is 5V after two OUT is obtained; in the period T4, CTRL is switched to 5V, the precharge pMOS transistor pm 0 is turned OFF, VDD does not charge the input terminal of the first inverter INV1 any more, the voltage of A is 5V, the voltage of B is 5V, the voltage of C is 0V, the voltage of G A is 0V, the voltage of G B is 0V, the voltage of G C is 5V (C is selected as OUT to be output), therefore, the first pMOS transistor pm 1 and the second pMOS transistor pm 2 are both turned on, the third pMOS transistor pm 3 is turned OFF, the first nMOS transistor nm 1 and the second nMOS transistor nm 2 are both turned OFF, the third nMOS transistor nm 3 is turned on, the source voltage of the first ferroelectric transistor f 1 and the source voltage of the second ferroelectric transistor f 2 are both 5V, so that the gate sources of the two ferroelectric transistors are both-5V, therefore, the first ferroelectric transistor f 1 and the second ferroelectric transistor f 2 are in a high-resistance state, and the source voltage of the third ferroelectric transistor f 3 is 0V, so the gate-source voltage difference of the third ferroelectric transistor f 3 is 5V, resulting in the ferroelectric layer polarization state P 3 of the third ferroelectric transistor f 3 being in an ON state, so the third ferroelectric transistor f 3 being in an ON state, thereby resulting in the charge of the input end of the first inverter INV1 being released, eventually resulting in OUT being 0V, consistent with the voltage of the selected C, thereby realizing the effect of selecting from a, And selecting one of the data selection functions of B and C.
The third operation period includes a period T5 and a period T6. In the period of T5, the voltage of a is 5V, the voltage of B is 0V, the voltage of c is 5V, the voltage of G A is 0V, the voltage of G B is 0V, the voltage of G C is 0V, so that the first pMOS transistor pm 1, the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are all on, the first nMOS transistor nm 1, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are all OFF, the source voltages of the three ferroelectric transistors are all 5V, at this time, since the voltage difference between the gate and the source of each ferroelectric transistor is-5V, the polarization states of the ferroelectric layers of the three ferroelectric transistors are all in the OFF state, and therefore the three ferroelectric transistors are all in the high-resistance state; meanwhile, in the time period T5, the voltage of CTRL is 0V, thus the pre-charge pMOS transistor pm 0 is conducted, VDD charges the input end of the first inverter INV1, the voltage obtained after the output of the two inverters is 5V, in the time period T6, CTRL is switched to 5V, the pre-charge pMOS transistor pm 0 is turned OFF, VDD does not charge the input end of the first inverter INV1 any more, A is 5V, B is 0V, C is 5V, G A is 0V, G B is 5V (B is selected as OUT to be output), G C is 0V, thus the first pMOS transistor pm 1 and the third pMOS transistor pm 3 are both conducted, the second pMOS transistor pm 2 is turned OFF, the first nMOS transistor nm 1 and the third nMOS transistor nm 3 are both turned OFF, the second nMOS transistor nm 2 is turned on, the voltage of the first ferroelectric transistor f 1 and the third nMOS transistor f 26 are both sources of ferroelectric 5V and 35V, the voltage of the source of the two ferroelectric transistors f5 and 35V are both sources, therefore, the first ferroelectric transistor f 1 and the third ferroelectric transistor f 3 are in a high-resistance state, and the source voltage of the second ferroelectric transistor f 2 is 0V, so that the gate-source voltage difference of the second ferroelectric transistor f 2 is 5V, resulting in the ferroelectric layer polarization state P 2 of the second ferroelectric transistor f 2 being in an ON state, and thus the second ferroelectric transistor f 2 being in an ON state, the charge at the input end of the first inverter INV1 is released to 0, resulting in OUT being 0V, consistent with the voltage of the selected B, thereby completing the operation from A, B, and B and C are one-out-of-three data selection function of B.
The fourth operation period includes a T7 period and a T8 period. In the period of T7, the voltage of a is 5V, the voltage of b is 0V, the voltage of c is 0V, the voltage of G A is 0V, the voltage of G B is 0V, the voltage of G C is 0V, therefore, the first pMOS transistor pm 1, the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are all on, the first nMOS transistor nm 1, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are all OFF, the source voltages of the three ferroelectric transistors are all 5V, at this time, the voltage difference between the gate and the source of each ferroelectric transistor is-5V, so that the polarization state of the ferroelectric layers of the three ferroelectric transistors is in the OFF state, the three ferroelectric transistors are all in the high-resistance state, and the voltage of CTRL is 0V, so that the pre-charge pMOS transistor pm 0 is on, the input terminal of the first inverter 1 is charged, and the voltage of the output from two inverters is 5V OUT; in the period of T8, CTRL is switched to 5V, the precharge pMOS transistor pm 0 is turned OFF, VDD does not charge the input terminal of the first inverter INV1 any more, A is 5V, B is 0V, C is 0V, G A is 5V (A is selected as OUT for output), G B is 0V, and G C is 0V, so that the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are both turned on, the first pMOS transistor pm 1 is turned OFF, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are both turned OFF, the first nMOS transistor nm 1 is turned on, the source voltage of the second ferroelectric transistor f 2 and the source voltage of the third ferroelectric transistor f 3 are both 5V, the gate-source voltage difference of both ferroelectric transistors is-5V, therefore, the second ferroelectric transistor f 2 and the third ferroelectric transistor f 3 are in a high-resistance state, and the gate-source voltage difference of the first ferroelectric transistor f 1 is close to 0V, so that the ferroelectric layer polarization state P 1 of the first ferroelectric transistor f 1 keeps the last written state, i.e. the high-resistance state, and the charges at the input end of the first inverter INV1 keep on keeping the level after the precharge for the T7 period of time because the three ferroelectric transistors are all in the high-resistance state, so that the voltage for the T8 period OUT keeps 5V, consistent with the voltage of the selected a, and the operation from a, a, And B and C, selecting one-out-of-three data selection function of A.
The fifth operation period includes a T9 period and a T10 period. In the period T9, the voltage of a is 0V, the voltage of b is 5V, the voltage of c is 5V, the voltage of G A is 0V, the voltage of G B is 0V, the voltage of G C is 0V, therefore, the first pMOS transistor pm 1, the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are all on, the first nMOS transistor nm 1, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are all OFF, the source voltages of the three ferroelectric transistors are all 5V, at this time, since the voltage difference between the gate and the source of each ferroelectric transistor is-5V, the polarization states of the ferroelectric layers of the three ferroelectric transistors are in the OFF state, and therefore, the three ferroelectric transistors are all in the high-resistance state; at the same time, CTRL is at 0V, so that the pre-charge pMOS transistor pm 0 is on, VDD charges the input of the first inverter INV1, the voltage of OUT obtained after output by the two inverters is 5V, CTRL is switched to 5V in the T10 period, the pre-charge pMOS transistor pm 0 is OFF, VDD does not charge the input of the first inverter INV1 any more, A is at 0V, B is at 5V, C is at 5V, G A is at 5V (A is selected as OUT for output), G B is at 0V, G C is at 0V, so that the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are both on, the first pMOS transistor pm 1 is OFF, the second nMOS transistor nm 2 and the third nMOS transistor nm 42 are both OFF, the first nMOS transistor nm 1 is on, the source of the second ferroelectric transistor f 2 and the third nMOS transistor f 26 are both at 5V voltage difference, the second ferroelectric transistor f 2 and the third ferroelectric transistor f 3 are therefore in a high-resistance state; the source voltage of the first ferroelectric transistor f 1 is 0V, the gate-source voltage difference of the first ferroelectric transistor f 1 is 5V, the ferroelectric layer polarization state P 1 of the first ferroelectric transistor f 1 is in an ON state, and therefore the first ferroelectric transistor f 1 is in an ON state, so that the charge at the input end of the first inverter INV1 is released to 0, OUT is 0V after passing through the two inverters, and the voltage is consistent with the voltage of the selected A, thereby completing the operation from A, and B and C are one-out-of-three data selection function of A.
The sixth operation period includes a T11 period and a T12 period. In the period of T11, the voltage of a is 0V, the voltage of B is 5V, the voltage of c is 0V, the voltage of G A is 0V, the voltage of G B is 0V, the voltage of G C is 0V, therefore, the first pMOS transistor pm 1, the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are all on, the first nMOS transistor nm 1, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are all OFF, the source voltages of the three ferroelectric transistors are all 5V, at this time, the voltage difference between the gate and the source of each ferroelectric transistor is-5V, so that the polarization state of the ferroelectric layers of the three ferroelectric transistors is in the OFF state, the three ferroelectric transistors are all in the high-resistance state, and the voltage of CTRL is 0V, so that the pre-charge pMOS transistor pm 0 is on, the input terminal of the first inverter 1 is charged, and the voltage of the output from two inverters is 5V; in the period of T12, CTRL is switched to 5V, the precharge pMOS transistor pm 0 is turned OFF, VDD does not charge the input terminal of the first inverter INV1 any more, A is 0V, B is 5V, C is 0V, G A is 0V, G B is 5V (B is selected as OUT to be output), and G C is 0V, so that the first pMOS transistor pm 1 and the third pMOS transistor pm 3 are both on, the second pMOS transistor pm 2 is turned OFF, the first nMOS transistor nm 1 and the third nMOS transistor nm 3 are both OFF, the second nMOS transistor nm 2 is turned on, the source voltage of the first ferroelectric transistor f 1 and the source voltage of the third ferroelectric transistor f 3 are both 5V, the gate sources of these two ferroelectric transistors are both-5V, therefore, the first ferroelectric transistor f 1 and the third ferroelectric transistor f 3 are in a high-resistance state, and the gate-source voltage difference of the second ferroelectric transistor f 2 is close to 0V, so the second ferroelectric transistor f 2 keeps the last written state, namely, the high-resistance state, so the charges at the input end of the first inverter INV1 keep on keeping the level after the precharge for the T11 period of time because the three ferroelectric transistors are all in the high-resistance state, so the voltage of the T12 period OUT keeps 5V, consistent with the voltage of the selected B, and the operation from a, B is completed, And B and C are one-out-of-three data selection function of B.
The seventh operation period includes a T13 period and a T14 period. In the period of T13, the voltage of a is 0V, the voltage of b is 0V, the voltage of C is 5V, the voltage of g A is 0V, the voltage of g B is 0V, the voltage of g C is 0V, therefore, the first pMOS transistor pm 1, the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are all on, the first nMOS transistor nm 1, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are all OFF, the source voltages of the three ferroelectric transistors are all 5V, at this time, the voltage difference between the gate and the source of each ferroelectric transistor is-5V, so that the polarization state of the ferroelectric layers of the three ferroelectric transistors is in the OFF state, the three ferroelectric transistors are all in the high-impedance state, and the voltage of CTRL is 0V, so that the pre-charge pMOS transistor pm 0 is on, the input terminal of the first inverter 1 is charged, and the voltage of the output from two inverters is 5V; in the period of T14, CTRL is switched to 5V, the precharge pMOS transistor pm 0 is turned OFF, VDD does not charge the input terminal of the first inverter INV1 any more, A is 0V, B is 0V, C is 5V, G A is 0V, G B is 0V, G C is 5V (C is selected as OUT to be output), so that the first pMOS transistor pm 1 and the second pMOS transistor pm 2 are both on, the third pMOS transistor pm 3 is turned OFF, the first nMOS transistor nm 1 and the second nMOS transistor nm 2 are both OFF, the third nMOS transistor nm 3 is turned on, the source voltage of the first ferroelectric transistor f 1 and the source voltage of the second ferroelectric transistor f 2 are both 5V, the gate-source voltage difference of these two ferroelectric transistors is-5V, therefore, the first ferroelectric transistor f 1 and the second ferroelectric transistor f 2 are both in the high-resistance state, and the gate-source voltage difference of the third ferroelectric transistor f 3 is close to 0V, so that the last state, i.e., the high-resistance state, is maintained, and the charge at the input end of the first inverter INV1 is kept at the level after the precharge for the T13 period because the three ferroelectric transistors are all in the high-resistance state, so that the voltage of the T14 period OUT is kept at 5V, consistent with the voltage of the selected C, and the operation from a, a, and B and C, selecting one of the three data selection functions of C.
The eighth operation period includes a T15 period and a T16 period. In the period of T15, the voltage of a is 0V, the voltage of B is 0V, the voltage of c is 0V, the voltage of G A is 0V, the voltage of G B is 0V, the voltage of G C is 0V, therefore, the first pMOS transistor pm 1, the second pMOS transistor pm 2 and the third pMOS transistor pm 3 are all on, the first nMOS transistor nm 1, the second nMOS transistor nm 2 and the third nMOS transistor nm 3 are all OFF, the source voltages of the three ferroelectric transistors are all 5V, at this time, the voltage difference between the gate and the source of each ferroelectric transistor is-5V, so that the polarization state of the ferroelectric layers of the three ferroelectric transistors is in the OFF state, the three ferroelectric transistors are all in the high-resistance state, and the voltage of CTRL is 0V, so that the pre-charge pMOS transistor pm 0 is on, the input terminal of the first inverter 1 is charged, and the voltage of the output OUT is 5V after two inverters are output; in the period of T16, CTRL is switched to 5V, the precharge pMOS transistor pm 0 is turned OFF, VDD does not charge the input terminal of the first inverter INV1 any more, A is 0V, B is 0V, C is 0V, G A is 0V, G B is 5V (B is selected as OUT to be output), G C is 0V, so that the first pMOS transistor pm 1 and the third pMOS transistor pm 3 are both on, the second pMOS transistor pm 2 is turned OFF, the first nMOS transistor nm 1 and the third nMOS transistor nm 3 are both OFF, the second nMOS transistor nm 2 is turned on, the source voltage of the first ferroelectric transistor f 1 and the source voltage of the third ferroelectric transistor f 3 are both 5V, the gate-source voltage difference of these two ferroelectric transistors is-5V, therefore, the first ferroelectric transistor f 1 and the third ferroelectric transistor f 3 are both in high resistance state, the source voltage of the second ferroelectric transistor f 2 is 0V, the gate-source voltage difference of the second ferroelectric transistor f 2 is 5V, the ferroelectric layer polarization state P 2 of the second ferroelectric transistor f 2 is in ON state, the second ferroelectric transistor f 2 is in ON state, the charge of the input end of the first inverter INV1 is released to 0, OUT is 0V after passing through the two inverters, and the voltage is consistent with the voltage of the selected B, thereby completing the operation of A, B, and B and C are one-out-of-three data selection function of B.
Claims (5)
1. A single power source integrated data selector with expandable selection data, comprising:
the input end of the pre-charging circuit is connected to the input end of the power supply signal, the control end of the pre-charging circuit is connected with the pre-charging control signal, and the output end of the pre-charging circuit is connected with the input end of the output driving circuit and is used for charging the input end of the output driving circuit to a high level under the action of the pre-charging control signal so as to provide stable initial conditions for data selection and calculation operation;
The system comprises at least two basic data input circuits, wherein each basic data input circuit consists of a ferroelectric transistor, an nMOS transistor and a pMOS transistor, wherein the drain electrode of the ferroelectric transistor is connected with the input end of the output driving circuit, the source electrode of the ferroelectric transistor is respectively connected with the drain electrodes of the nMOS transistor and the pMOS transistor, and the grid electrode of the ferroelectric transistor is connected with a data selection control signal and is used for selecting the data input signal according to the data selection control signal;
And the output driving circuit is used for outputting a data selection result after nonvolatile storage according to the level state after the pre-charging and the storage state of the ferroelectric transistor.
2. A single power store data selector with extensible select data according to claim 1, wherein said data selector comprises:
The m data input ends are used for accessing different data input signals, wherein m is more than or equal to 2;
One of the power signal inputs for providing a stable power supply voltage to the precharge circuit, the basic data input circuit, and the output driver circuit, and a power supply voltage to the substrates of all pMOS transistors in the data selector;
A ground signal input terminal providing a stable ground for the output driver circuit and a ground for the substrates of all nMOS transistors and ferroelectric transistors in the data selector;
the precharge control signal input end is used for accessing a precharge control signal;
the m data selection control signal input ends are used for accessing different data selection control signals;
the data output end is used for outputting the data selection result after nonvolatile storage;
The number of the basic data input circuits is m, and m is one data selector.
3. A single power source integrated data selector with expandable selection data according to claim 2, characterized in that the pre-charge circuit is composed of a pre-charge pMOS transistor, the source of which is used as the input terminal of the pre-charge circuit, the gate is used as the control terminal of the pre-charge circuit and is used for being connected with the pre-charge control signal input terminal, and the drain is used as the output terminal of the pre-charge circuit.
4. A single power source integrated data selector with expandable selection data according to claim 2 or 3, wherein the output driving circuit is composed of a first inverter and a second inverter, the input end of the first inverter is used as the input end of the output driving circuit, the input end of the second inverter is connected with the output end of the first inverter, and the output end of the second inverter is used as the output end of the output driving circuit and is connected with the data output end.
5. A single-power-source-store-integrated data selector with scalable selection data according to claim 2, characterized in that in the ith said basic data input circuit, the gates of the ferroelectric transistor, the nMOS transistor and the pMOS transistor are all connected to the ith said data selection control signal input terminal, and the source of the nMOS transistor is connected to the ith said data input terminal, where i = 1, 2.
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