CN120507945B - Calibration method, device, electronic device and storage medium for photolithography model - Google Patents
Calibration method, device, electronic device and storage medium for photolithography modelInfo
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/705—Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
- G03F7/70504—Optical system modelling, e.g. lens heating models
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
- G03F7/70516—Calibration of components of the microlithographic apparatus, e.g. light sources, addressable masks or detectors
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/706843—Metrology apparatus
- G03F7/706845—Calibration, e.g. tool-to-tool calibration, beam alignment, spot position or focus
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Abstract
本申请实施例公开了一种光刻模型的校准方法、装置、电子设备及存储介质。该方案可以在掩模版上选取不同种类的标准图形及测试图形，以作为初始采样点，对光学模型中的参数进行调整，并根据调整后的光学模型对所述初始采样点进行光学模拟，得到模拟尺寸，将所述模拟尺寸与设计尺寸进行对比，根据对比结果对所述初始采样点进行筛选，以得到目标采样点，对所述目标采样点进行晶圆量测得到第一量测结果，并根据第一量测结果对所述光学模型和光刻胶模型进行校准。本申请实施例可以对采样点进行模拟并筛选，从而减少大量的无效采样点，缩短了采样点数据量测时间，同时提高了采样点质量和最终建模效率。
The embodiments of the present application disclose a method, device, electronic device, and storage medium for calibrating a photolithography model. This solution can select different types of standard patterns and test patterns on a mask as initial sampling points, adjust the parameters in the optical model, and perform optical simulation on the initial sampling points based on the adjusted optical model to obtain simulated dimensions. The simulated dimensions are compared with the designed dimensions, and the initial sampling points are screened based on the comparison results to obtain target sampling points. The target sampling points are subjected to wafer measurement to obtain a first measurement result, and the optical model and photoresist model are calibrated based on the first measurement result. The embodiments of the present application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the sampling point data measurement time, and improving the sampling point quality and final modeling efficiency.
Description
Technical Field
The present application relates to the field of chip manufacturing technologies, and in particular, to a method and apparatus for calibrating a lithography model, an electronic device, and a storage medium.
Background
Along with the continuous improvement of chip design density and complexity, the industry has put higher demands on the prediction accuracy of the lithography model and the coverage pattern type and size range thereof. In this case, it is critical to collect a large number of sample points to train and calibrate a complex lithography model. Particularly when the logic chip process is advanced to 28nm and below, the lithography model establishment of many complex lithography layers usually requires tens of thousands or even more than one hundred thousand sampling points, for example, the lithography model using the negative development technique often requires more than one hundred thousand sampling points.
Currently, conventional sampling point selection methods rely on design rules to mechanically cover various patterns on a test reticle, and often include a large number of sub-design rule size patterns, for example, less than 50% of the design rule size, to ensure model coverage. However, in actual exposure, the patterns exceed the limit of the lithography process window, so that a part of sampling points cannot be imaged or the imaging quality does not reach the standard, and the precision and modeling efficiency of the lithography model are seriously affected.
Disclosure of Invention
The application provides a calibration method, a device, electronic equipment and a storage medium of a photoetching model, which can simulate and screen sampling points, so that a large number of invalid sampling points are reduced, the data measurement time of the sampling points is shortened, and meanwhile, the quality of the sampling points and the final modeling efficiency are improved.
The application provides a calibration method of a photoetching model, which comprises the following steps:
Selecting different types of standard patterns and test patterns on the mask plate to serve as initial sampling points;
Adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulation size;
comparing the simulation size with the design size, and screening the initial sampling point according to a comparison result to obtain a target sampling point;
and carrying out wafer measurement on the target sampling point to obtain a first measurement result, and calibrating the optical model and the photoresist model according to the first measurement result.
Optionally, the adjusting the parameters in the optical model includes:
the optical model is symmetrical to a preset graphic focus by adjusting focus parameters;
And calibrating a threshold parameter according to the anchor point, so that the simulation value of the optical model is consistent with the target value.
Optionally, the calibrating the threshold parameter according to the anchor point includes:
Selecting an anchor point graph matched with the design size from the initial sampling points;
and iteratively adjusting the threshold parameters of the optical model until the error between the simulated size of the optical model in the anchor point pattern and the actual measured size of the wafer is smaller than a preset tolerance.
Optionally, the screening the initial sampling point according to the comparison result to obtain a target sampling point includes:
removing sampling points with the simulation size smaller than the preset percentage of the design rule size;
And determining a target size interval which is not covered by the initial sampling point set in the design rule so as to supplement the sampling points corresponding to the target size interval and obtain target sampling points.
Optionally, after calibrating the optical model and the photoresist model according to the first measurement result, the method further comprises:
Adding a supplementary sampling point, and performing optical simulation on the supplementary sampling point according to the calibrated optical model so as to screen the supplementary sampling point;
Performing wafer measurement on the screened supplementary sampling points to obtain a second measurement result;
and fusing the first measurement result and the second measurement result, and calibrating the optical model and the photoresist model according to the fusion result.
Optionally, the acquiring process of the supplementary sampling point includes:
when the initial sampling points are screened, a graph with the similarity of the simulation size and the design size reaching a preset value in the removed sampling points is obtained, or,
And selecting a pattern on the mask plate according to the calibration residual errors of the optical model and the photoresist model.
Optionally, the fusing the first measurement result and the second measurement result includes:
determining repeated sampling points in the first measurement result and the second measurement result, and calculating a measurement average value of the repeated sampling points;
and carrying out weighting processing on the first measurement result and the second measurement result according to the position information of the initial sampling point and the supplementary sampling point on the wafer, and fusing the weighted data.
The application also provides a calibration device of the photoetching model, which comprises:
the selecting module is used for selecting different types of standard patterns and test patterns on the mask plate to serve as initial sampling points;
the simulation module is used for adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulation size;
the screening module is used for comparing the simulation size with the design size, and screening the initial sampling point according to a comparison result to obtain a target sampling point;
And the calibration module is used for carrying out wafer measurement on the target sampling point to obtain a first measurement result, and calibrating the optical model and the photoresist model according to the first measurement result.
The application also provides an electronic device, which is characterized in that the electronic device comprises a memory and a processor, wherein the memory stores a computer program, and the processor executes the steps in the method for calibrating the lithography model according to any one of the application by calling the computer program stored in the memory.
The application also provides a storage medium storing a computer program adapted to be loaded by a processor for performing the steps of the method of calibrating a lithography model according to any of the claims provided herein.
According to the calibration method of the photoetching model, different types of standard patterns and test patterns can be selected on a mask plate to serve as initial sampling points, parameters in an optical model are adjusted, the initial sampling points are subjected to optical simulation according to the adjusted optical model to obtain simulation sizes, the simulation sizes are compared with design sizes, the initial sampling points are screened according to comparison results to obtain target sampling points, wafer measurement is conducted on the target sampling points to obtain first measurement results, and the optical model and the photoresist model are calibrated according to the first measurement results. The embodiment of the application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the data measurement time of the sampling points, and improving the quality of the sampling points and the final modeling efficiency.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for calibrating a lithography model according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of another method for calibrating a lithography model according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a calibration apparatus for a lithographic model according to an embodiment of the present application;
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element(s) defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other like elements in different embodiments of the application having the same meaning as may be defined by the same meaning as they are explained in this particular embodiment or by further reference to the context of this particular embodiment.
It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily occurring in sequence, but may be performed alternately or alternately with other steps or at least a portion of the other steps or stages.
It should be noted that, in this document, step numbers such as 101 and 102 are used for the purpose of more clearly and briefly describing the corresponding contents, and not to constitute a substantial limitation on the sequence, and those skilled in the art may execute 102 first and then execute 101 when they are implemented, which is within the scope of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The execution body of the calibration method of the lithography model can be the calibration device of the lithography model provided by the embodiment of the application or a server integrated with the calibration device of the lithography model, wherein the calibration device of the lithography model can be realized in a hardware or software mode.
As shown in fig. 1, fig. 1 is a first flow chart of a calibration method of a lithography model according to an embodiment of the present application, where a specific flow of the calibration method of the lithography model may be as follows:
101. And selecting different types of standard patterns and test patterns on the mask plate to serve as initial sampling points.
In one embodiment, the standard pattern and the test pattern may be selected on the test reticle according to a design rule of the photolithography layer, where the design rule may include a minimum feature size, an allowable size range, a pattern type, and the like. The standard pattern may include industry-wide test structures such as isolated lines (ISO lines), dense line arrays (DENSE LINES), contact holes (contact holes), or corner structures (corner structures). These patterns overlay basic lithographic behavior for evaluating the versatility of the model. The test pattern may then comprise a pattern simulating an actual chip design, such as a complex pattern (e.g., an L-shape, T-shape, or curved structure) in a similar logic cell, or a pattern of varying dimensions generated based on design rules, such as varying in 10% steps from a minimum design dimension to a maximum allowable dimension, to obtain an initial sample point.
In an embodiment, a specific sampling manner may be used to construct an initial sampling matrix, for example, with a design rule size (e.g. 28 nm) as a center, and the initial sampling matrix is distributed to small sizes (10 nm-20 nm) and large sizes (30 nm-50 nm) according to logarithmic intervals, and is sampled in layers according to pattern density and duty ratio in each size interval, so as to ensure uniform coverage of sampling points in a feature space.
The pattern selected in this embodiment covers all critical pattern types to capture different optical effects during photolithography, including minimum, typical and larger dimensions allowed by design rules, and some dimensions beyond the design rules to test the boundary behavior of the model. The initial sampling points may include coordinates, types, design dimensions, reticle position information, etc. of all selected patterns.
102. And adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulation size.
In one embodiment, the optical model may be built based on lithographic conditions, which may include parameters such as light source wavelength, numerical aperture, illumination pattern, etc. And then adjusting parameters in the optical model to improve model accuracy, wherein the step of adjusting the parameters in the optical model can comprise the steps of enabling the optical model to be symmetrical to a preset graph focus by adjusting focus parameters, and enabling simulation values of the optical model to be consistent with target values according to anchor point calibration threshold parameters. Specifically, the focus parameter, i.e., focus parameter, represents the focus position of the lithography machine. An ISO pattern (e.g. isolated lines or holes) can be chosen because it is sensitive to focus variations. And then, iteratively adjusting the focus parameter to ensure that the model keeps symmetrical to the simulation behavior of the ISO graph when the focus is shifted (defocus), namely the dimensional change under the positive and negative focus shifts is consistent. For example, if the simulated size difference is too large at focus shifts +100nm and-100 nm, the focus parameter in the model is adjusted until the difference is less than a threshold (e.g., 5%).
In an embodiment, the step of calibrating the threshold parameter according to the anchor point may include selecting an anchor point pattern matching the design size from the initial sampling points, and iteratively adjusting the threshold parameter of the optical model until an error between a simulated size of the optical model in the anchor point pattern and an actual measured size of the wafer is smaller than a preset tolerance. Specifically, a threshold parameter of the optical model, i.e., threshold, represents threshold energy during photolithography, affecting the imaging dimension of the pattern. Calibration is performed using an anchor pattern matching the design dimensions as a key reference point, for example, a standard dimension pattern in the design rule, whose target value is known. The threshold value is adjusted by comparing the simulated size of the model at the key reference point to the actual target value (or historical measurement value) so that the simulated size coincides with the target value (e.g., the error is less than 1%). For example, if the design size of the key reference point is 50nm, but the model simulation value is 52nm, the threshold value is reduced until the simulation value converges to 50nm. After adjustment, an accurate pure optical lithography model can be obtained.
Next, each initial sampling point may be simulated using the adjusted optical model. The simulation process calculates the predicted dimension, i.e., the simulated dimension, of each point on the wafer based on the lithography conditions (e.g., light source wavelength, numerical aperture) and mask pattern, and the simulation tool outputs simulated dimension data for each sample point.
103. And comparing the simulation size with the design size, and screening the initial sampling point according to the comparison result to obtain a target sampling point.
In one embodiment, the analog size is compared to the design size for each initial sample point. The design dimension is the intended dimension of the pattern on the reticle, for example, a line width of 40nm. The percentage deviation of the simulated dimension from the design dimension can then be calculated, e.g., simulated dimension = design dimension x (1 + percentage deviation). And then screening the initial sampling points according to the comparison result.
In one embodiment, the step of filtering the initial sampling points may include removing invalid points and supplementing missing points. Specifically, based on the comparison result, a pattern having a simulated size of less than 30% of the design rule size, for example, a design rule minimum size of 40nm, may be identified and removed, and a pattern having a simulated size of less than 28nm may be removed. These patterns may not be imaged (e.g., the pattern disappears) or imaged with poor quality (e.g., the edge blur) in actual lithography, resulting in wafer metrology inefficiency. The rejection criteria ensure that the sampling points are focused on a measurable active area. Next, during the screening process, it may be further checked whether the initial sampling points cover all critical dimension intervals and types. These sampling points may be added in addition if some design size intervals (e.g., around the minimum size of the design rule) or pattern types (e.g., complex corner structures) are not adequately covered. The supplementary principle is based on design rules, so that the sampling points are uniformly distributed. The step of screening the initial sampling points according to the comparison result to obtain target sampling points may include removing sampling points with analog sizes smaller than a preset percentage of the design rule size, determining a target size interval in the design rule which is not covered by the initial sampling point set, and supplementing sampling points corresponding to the target size interval to obtain the target sampling points. It should be noted that, the simulation size is less than 30% of the design rule size and is not a standard, and an implementer may adjust the standard according to different situations, for example, the photolithography condition satisfies a resolution smaller than the design rule size, or for some 2D patterns, may also reject patterns with a simulation size less than 40% -50% of the design rule size.
Further, after the initial sampling points are screened, the comprehensiveness of the target sampling points can be verified. For example, size distribution (from minimum design size to larger size), type coverage (standard and test patterns each account for a reduction in size after screening, invalid points reduced by 10-20%, but total points still sufficient for modeling), and the like are checked.
104. And carrying out wafer measurement on the target sampling point to obtain a first measurement result, and calibrating the optical model and the photoresist model according to the first measurement result.
In one embodiment, a test reticle may be used to expose a wafer to create an actual lithographic pattern. Then, physical measurement is performed on the target sampling point. The measuring tool may measure the actual size on the wafer according to the position of each target sampling point by using a Scanning Electron Microscope (SEM) or an optical measuring device. The measurement process is to build a measurement automation script and define the coordinates of measurement points, the measurement times (such as 3 times of averaging for each point measurement) and conditions (such as acceleration voltage). During metrology, invalid data points, such as points where imaging fails, points where the metrology size is abnormally small or large, or points where the signal-to-noise ratio is low, are removed. After all of the metrology values are collected, data cleaning may also be performed, such as removing invalid points, calculating mean and standard deviation, and sorting into structured data sets. As a first measurement result.
The first metrology result may then be used to calibrate a lithography model, wherein the lithography model includes two parts, an optical model and a photoresist model, the photoresist model being used to simulate the chemical processes of the photoresist, such as development and baking. For the optical model, the optical model parameters (e.g., focus or threshold) may be fine-tuned based on the metrology data. The method is to minimize errors of the simulation size and the measurement size by an optimization algorithm such as a least square method. For example, if the measurement shows that some of the pattern dimensions are larger, the threshold value is adjusted to reduce the bias. For the photoresist model, parameters such as diffusion coefficient or sensitivity are mainly adjusted, and measured data can be specifically used, especially for a photoresist sensitive graph, and model prediction is consistent with a measured value through iterative fitting. For example, the diffusion parameters are adjusted to match the edge roughness in the metrology. In one embodiment, after the calibration, the model accuracy may also be verified with partial data, and if the error is large, such as more than 5%, the parameters may be readjusted until the model converges, such as less than 2%.
According to the method, invalid sampling points are screened in advance, the wafer measurement time and data arrangement cost are reduced, the photoetching modeling efficiency is improved, an accurate optical model is built for simulation screening, measurement of a large number of invalid points in a traditional method is avoided, and high-quality data is provided for subsequent modeling.
In view of the foregoing, the calibration method for a lithography model provided by the embodiment of the present application may select different types of standard patterns and test patterns on a mask plate as initial sampling points, adjust parameters in an optical model, perform optical simulation on the initial sampling points according to the adjusted optical model to obtain a simulation size, compare the simulation size with a design size, screen the initial sampling points according to a comparison result to obtain target sampling points, perform wafer measurement on the target sampling points to obtain a first measurement result, and calibrate the optical model and the photoresist model according to the first measurement result. The embodiment of the application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the data measurement time of the sampling points, and improving the quality of the sampling points and the final modeling efficiency.
The method according to the previous embodiments will be described in further detail below.
Referring to fig. 2, fig. 2 is a schematic flow chart of a second method for calibrating a lithography model according to an embodiment of the application. The method comprises the following steps:
201. And selecting different types of standard patterns and test patterns on the mask plate to serve as initial sampling points.
Specifically, according to the design rule of the photolithography layer, a plurality of standard patterns with different types and sizes and test patterns similar to the design patterns can be selected on the test mask. These patterns cover various features that the photolithographic layer may involve, such as different shapes, different line widths, different spacings, etc. By selecting rich and various patterns, the initial sampling points can cover various conditions required by the photoetching model, and comprehensive basic data is provided for subsequent model training and calibration.
202. And adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulation size.
Establishing an initial optical model, then adjusting a focus parameter in the model to enable the model to be focus symmetrical to an ISO graph, then taking a key graph point with a known accurate target value or an actual measurement value as an anchor point, and adjusting a threshold parameter to enable a simulation value of the optical model at the anchor point to be consistent with the target value (such as the actual wafer measurement value). By means of the series of parameter adjustment, a relatively accurate pure optical lithography model is obtained.
The optical simulation can be carried out on the selected initial sampling points by utilizing the adjusted optical model, and the imaging condition of the patterns in the photoetching process is simulated, so that the simulation size of each initial sampling point is obtained.
203. And comparing the simulation size with the design size, and screening the initial sampling point according to the comparison result to obtain a target sampling point.
Comparing the simulated size of each initial sampling point obtained in step 202 with the design size of the photoetching layer, and eliminating the patterns with the simulated sizes less than 30% of the design rule size. At the same time, it is checked whether there are uncovered target size sample points, and if so, these uncovered target size sample points are supplemented. Through the screening and supplementing operation, the target sampling point is finally obtained.
204. And carrying out wafer measurement on the target sampling point to obtain a first measurement result, and calibrating the optical model and the photoresist model according to the first measurement result.
And measuring target sampling points on the wafer subjected to the exposure of the test mask, collecting measurement values to obtain a first measurement result, sorting the measured data, removing invalid measurement data, such as that the sampling points are not imaged, the imaging quality is poor, the measurement size is far smaller than the latest design rule, and the like, and calibrating the optical model and the photoresist model by utilizing the sorted effective data so that the model can reflect the actual photoetching process more accurately.
205. And adding the supplementary sampling points, and performing optical simulation on the supplementary sampling points according to the calibrated optical model so as to screen the supplementary sampling points.
In one embodiment, the process of obtaining the complementary sampling points may include obtaining a pattern with similarity between the simulated size and the design size of the removed sampling points reaching a predetermined value when the initial sampling points are screened, or selecting a pattern on the mask according to calibration residuals of the optical model and the photoresist model. Specifically, when the initial sampling points are screened, a graph with similarity between the simulation size and the design size of the removed sampling points reaching a preset value can be obtained. These patterns, while culled in the initial screening, may help in calibration and verification of the model. In addition, a pattern can be selected on the mask according to the calibration residual errors of the optical model and the photoresist model, namely, the difference between the model predicted value and the actual measured value. And determining the area with poor model performance by analyzing the residual error, and selecting the supplementary sampling points in a targeted manner.
The obtained complementary sampling points can then be optically simulated using the calibrated optical model to obtain simulated dimensions. And comparing the simulation size with the design size, removing sampling points with the simulation size less than 30% of the design rule size, and screening out supplementary sampling points meeting the requirements.
206. And carrying out wafer measurement on the screened supplementary sampling points to obtain a second measurement result.
For the screened supplementary sampling points, measurement can be performed on the wafer according to the measurement method which is the same as the above steps, and a measurement record is established and a measurement value is collected to obtain a second measurement result. And (5) sorting the measurement data to remove invalid data.
207. And fusing the first measurement result and the second measurement result, and calibrating the optical model and the photoresist model according to the fusion result.
In one embodiment, the step of fusing the first measurement result and the second measurement result may include determining a repeated sampling point in the first measurement result and the second measurement result, calculating a measurement average value of the repeated sampling point, weighting the first measurement result and the second measurement result according to position information of the initial sampling point and the supplementary sampling point on the wafer, and fusing the weighted data. Since the additional sampling points may include the initial sampling points removed in step 203, such as a graph with similarity between the analog size and the design size reaching a preset value, the sampling point identifiers of the two sets of data need to be compared, and sampling points that exist in the two sets of results simultaneously are screened out, where the sampling point identifiers may include information such as a graph type, a size, and coordinates on the mask. Specifically, a data comparison table can be established, the unique identification of the sampling point is used as a key field, the first measurement result and the second measurement result are traversed, and the repeated sampling point is marked. The multiple measurements (the value in the first measurement and the value in the second measurement) for each of the repeated sampling points are then arithmetically averaged.
The position information of the initial sampling point and the supplementary sampling point on the wafer is the physical coordinates of the sampling point on the mask plate or the corresponding exposure position on the wafer. Specifically, the wafer can be divided into a plurality of areas, and the position of each sampling point corresponds to the unique area coordinate. For adjacent sampling points, the spatial distance is calculated, and the closer the distance is, the higher the position correlation is. The closer the sampling points are, the more similar the lithography process conditions are, the stronger the correlation of the metrology data, and thus the higher the weighting can be given. And then calculating the weight relation between the non-repeated sampling points in the first measurement result and the second measurement result and surrounding sampling points according to the positions of the non-repeated sampling points on the wafer. And finally, merging the measurement data of all sampling points (repeated point average value taking and non-repeated point weighted fusion) to form a unified fusion data set. The fused data set contains measurement information of the initial sampling point and the supplementary sampling point, so that the conventional design size can be covered, and details of a model residual region can be supplemented, thereby more accurately calibrating the optical model and the photoresist model and shortening the modeling period.
In the above-mentioned, the calibration method of the lithography model provided by the embodiment of the application may select different types of standard patterns and test patterns on the mask plate as initial sampling points, adjust parameters in the optical model, perform optical simulation on the initial sampling points according to the adjusted optical model to obtain a simulation size, compare the simulation size with a design size, screen the initial sampling points according to a comparison result to obtain a target sampling point, perform wafer measurement on the target sampling point to obtain a first measurement result, calibrate the optical model and the photoresist model according to the first measurement result, add additional sampling points, perform optical simulation on the additional sampling points according to the calibrated optical model to screen the additional sampling points, perform wafer measurement on the screened additional sampling points to obtain a second measurement result, fuse the first measurement result with the second measurement result, and calibrate the optical model and the photoresist model according to the fusion result. The embodiment of the application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the data measurement time of the sampling points, and improving the quality of the sampling points and the final modeling efficiency.
In order to implement the above method, the embodiment of the application also provides a calibration device of the lithography model, which can be integrated in terminal equipment such as a mobile phone, a tablet personal computer and the like.
For example, as shown in fig. 3, a schematic structural diagram of a calibration device for a lithography model according to an embodiment of the present application is shown. The calibration device of the lithography model may include:
The selecting module 301 is configured to select different types of standard patterns and test patterns on the mask plate, so as to serve as initial sampling points;
The simulation module 302 is configured to adjust parameters in the optical model, and perform optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulation size;
the screening module 303 is configured to compare the simulated size with the design size, and screen the initial sampling point according to a comparison result to obtain a target sampling point;
And the calibration module 304 is configured to perform wafer measurement on the target sampling point to obtain a first measurement result, and calibrate the optical model and the photoresist model according to the first measurement result.
As can be seen from the foregoing, the calibration device for a lithography model provided by the embodiment of the present application may select different types of standard patterns and test patterns on a mask as initial sampling points, adjust parameters in an optical model, perform optical simulation on the initial sampling points according to the adjusted optical model to obtain a simulation size, compare the simulation size with a design size, screen the initial sampling points according to a comparison result to obtain target sampling points, perform wafer measurement on the target sampling points to obtain a first measurement result, and calibrate the optical model and the photoresist model according to the first measurement result. The embodiment of the application can simulate and screen the sampling points, thereby reducing a large number of invalid sampling points, shortening the data measurement time of the sampling points, and improving the quality of the sampling points and the final modeling efficiency.
All the above technical solutions may be combined to form an optional embodiment of the present application, and will not be described in detail herein.
Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be performed by instructions, or by instructions controlling associated hardware, which may be stored in a computer-readable storage medium and loaded and executed by a processor.
To this end, an embodiment of the present application provides a computer readable storage medium having stored therein a plurality of computer programs that can be loaded by a processor to perform the steps of any of the methods for calibrating a lithography model provided by the embodiment of the present application. For example, the computer program may perform the steps of:
Selecting different types of standard patterns and test patterns on the mask plate to serve as initial sampling points;
Adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulation size;
comparing the simulation size with the design size, and screening the initial sampling point according to a comparison result to obtain a target sampling point;
and carrying out wafer measurement on the target sampling point to obtain a first measurement result, and calibrating the optical model and the photoresist model according to the first measurement result.
The specific implementation of each operation above may be referred to the previous embodiments, and will not be described herein.
The storage medium may include a Read Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or the like.
The steps in any of the methods for calibrating a lithography model provided by the embodiments of the present application may be executed by the computer program stored in the storage medium, so that the beneficial effects that any of the methods for calibrating a lithography model provided by the embodiments of the present application may be achieved, which are detailed in the previous embodiments and will not be described herein.
The embodiment of the application also provides an electronic device, which comprises a memory and a processor, wherein the memory is used for storing a computer program, and the processor is used for calling and running the computer program from the memory, so that the device provided with the chip executes the method in the various possible implementation modes.
For example, the computer device may be a terminal device having a corresponding function, such as a mobile phone, a tablet computer, a personal computer, a cloud computer, or the like. Referring to fig. 4, fig. 4 is a schematic structural diagram of a computer according to an embodiment of the application.
The computer device 400 may include a memory 401, a processor 402, and the like. Those skilled in the art will appreciate that the computer device structure shown in FIG. 4 is not limiting of the computer device and may include more or fewer components than shown, or may be combined with certain components, or a different arrangement of components.
Memory 401 may be used to store applications and data. The memory 401 stores an application program including executable code. Applications may constitute various functional modules. The processor 402 executes various functional applications and data processing by running application programs stored in the memory 401.
The processor 402 is a control center of the computer device, connects various parts of the entire computer device using various interfaces and lines, and performs various functions of the computer device and processes data by running or executing application programs stored in the memory 401, and calling data stored in the memory 401, thereby performing overall monitoring of the computer device.
In this embodiment, the processor 402 in the computer device loads executable codes corresponding to the processes of one or more application programs into the memory 401 according to the following instructions, and the processor 402 executes the application programs stored in the memory 401, so as to execute:
Selecting different types of standard patterns and test patterns on the mask plate to serve as initial sampling points;
Adjusting parameters in the optical model, and performing optical simulation on the initial sampling point according to the adjusted optical model to obtain a simulation size;
comparing the simulation size with the design size, and screening the initial sampling point according to a comparison result to obtain a target sampling point;
and carrying out wafer measurement on the target sampling point to obtain a first measurement result, and calibrating the optical model and the photoresist model according to the first measurement result.
It can be understood that the above scenario is merely an example, and does not constitute a limitation on the application scenario of the technical solution provided by the embodiment of the present application, and the technical solution of the present application may also be applied to other scenarios. For example, as one of ordinary skill in the art can know, with the evolution of the system architecture and the appearance of new service scenarios, the technical solution provided by the embodiment of the present application is also applicable to similar technical problems.
The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs. The modules in the device of the embodiment of the application can be combined, divided and deleted according to actual needs.
In the present application, the same or similar term concept, technical solution and/or application scenario description will be described in detail only when first appearing, and when repeated later, for brevity, description will not be generally repeated, and when the technical solution and the like of the present application are understood, the same or similar term concept, technical solution and/or application scenario description and the like which are not described in detail later may be referred to in the previous related detailed description thereof.
In the present application, the descriptions of the embodiments are emphasized, and the details or descriptions of the other embodiments may be referred to.
The technical features of the technical scheme of the application can be arbitrarily combined, and all possible combinations of the technical features in the above embodiment are not described for the sake of brevity, however, as long as there is no contradiction between the combinations of the technical features, the application shall be considered as the scope of the description of the application.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. Usable media may be magnetic media (e.g., floppy disk, storage disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid state storage disk Solid STATE DISK), etc.
The foregoing describes a method, apparatus, electronic device and storage medium for calibrating a lithography model according to embodiments of the present application in detail, and specific examples are set forth herein to illustrate the principles and embodiments of the present application, and the above description of the embodiments is only for aiding in understanding the method and core concept of the present application, and meanwhile, for those skilled in the art, according to the concept of the present application, there are variations in the specific embodiments and application ranges, so the disclosure should not be construed as limiting the application.
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