CN120471006A

CN120471006A - A method for realizing a standardized interconnection substrate for an on-wafer system and an interconnection structure

Info

Publication number: CN120471006A
Application number: CN202510971355.3A
Authority: CN
Inventors: 王梦雅; 朱旻琦; 宋刚杰; 魏敬和
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2025-07-15
Filing date: 2025-07-15
Publication date: 2025-08-12
Anticipated expiration: 2045-07-15
Also published as: CN120471006B

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a method for realizing a system-on-chip standardized interconnection substrate and an interconnection structure. The chip integrated circuit comprises a plurality of different functional units formed by arranging and combining core particles integrated in a system on a chip, different micro-module-level interconnection substrates with standardized PAD distribution at the bottoms are respectively attached to corresponding core particles according to the different functional units to form a plurality of different functional unit micro-modules, a wafer-level interconnection substrate with a standardized PAD distribution array at the tops is provided, wiring design shaping of the wafer-level interconnection substrate is completed according to interconnection communication requirements, external communication requirements and power supply requirements, and the different functional unit micro-modules are attached to the wafer-level interconnection substrate to realize standardized interconnection. The method can break through the customized architecture of the system on a chip, reduce the design and processing of the wafer-level interconnection substrate which is complicated and time-consuming due to the modification of the core particle selection, and improve the design efficiency.

Description

Method for realizing standardized interconnection substrate of system on chip and interconnection structure

Technical Field

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a method for realizing a standardized interconnection substrate of a system-on-chip and an interconnection structure.

Background

High performance computing (HPC, high Performance Computing) has been rapidly developed in recent years, and has been widely used in the fields of internet of things, big data, blockchain, artificial intelligence, etc., but its assembly mode and system architecture have not been able to meet the morphological requirements of the new generation of miniaturized and portable electronic systems, and development of miniaturized, lightweight, high performance HPC systems facing the new generation of electronic systems is urgent. However, with the trend toward moore's law, semiconductor feature sizes approach physical limits, and performance doubling through feature size scaling is a major issue under the dual pressures of technical difficulty and economic cost.

The advent of System on chip (SoW) opens a very innovative and viable technological route for the development of high performance computing. The on-chip system is a wafer-level high-density integrated computing system which is recently raised at home and abroad, is mainly oriented to the application requirements of high computing power and miniaturization in certain industry specific fields, performs high-density interconnection on a large number of cores which are designed in advance and have various functions based on a 2.5D/3D wafer-level advanced packaging process, is provided with an intelligent software system, and realizes a wafer-level extremely high-density computing system through soft and hard cooperation.

The on-chip system is required to complete integration of tens or even hundreds of core grains in a limited space, the design difficulty of an interconnection substrate is increased in multiple levels compared with that of a traditional multi-core grain integrated system, the on-chip system at present mainly realizes multi-core grain integration based on a customized architecture, and the design of the customized substrate is required to be carried out again for different chip types, so that the design and verification of the substrate which is complex and time-consuming are required to be carried out once, and the sustainable development of the on-chip system is seriously restricted. In order to break the integration barriers of different manufacturers, accelerate the design period and improve the one-time design success rate of the system-on-chip interconnection substrate, development of a standardized wafer interconnection substrate implementation method suitable for the system-on-chip is urgently needed.

Disclosure of Invention

The invention aims to provide a method for realizing a standardized interconnection substrate of a system on a chip, which can break through the customized design of the interconnection substrate of the system on the chip, so as to meet the requirement of random replacement of master control core particles, storage core particles and the like in various application scenes by using a generalized and standardized wafer interconnection substrate design, and greatly reduce the time and value cost brought by redesign of the wafer interconnection substrate due to the selection and change of the core particles.

In order to solve the technical problems, the invention provides a method for realizing a standardized interconnection substrate of a system-on-chip, which comprises the following steps:

Firstly, arranging and combining core grains integrated in a crystal upper system to form a plurality of different functional units;

step two, providing different micro-module-level interconnection substrates with standardized PAD distribution at the bottoms;

Step three, different micro-module-level interconnection substrates with standardized PAD distribution at the bottoms are respectively attached to corresponding core particles according to the different functional units to form a plurality of different functional unit micro-modules;

step four, providing a wafer-level interconnection substrate with a standardized PAD distributed array at the top, and completing wiring design shaping of the wafer-level interconnection substrate according to interconnection communication requirements, external communication requirements and power supply requirements;

And fifthly, attaching different kinds and different numbers of functional unit micro-modules to the wafer-level interconnection substrate according to application requirements so as to realize standardized interconnection.

Preferably, in the first step, the functional unit is composed of a master core granule and a storage core granule, wherein the master core granule comprises CPU, FPGA, DSP and AI, and the storage core granule comprises DDRx and FLASH.

Preferably, in the second step, the standardized PAD distribution includes a standardized signal pin array, a standardized power pin array, and a standardized ground pin array.

Preferably, the standardized signal pin array is used for merging the intra-die interconnection communication requirements and the extra-die communication requirements among a plurality of different functional units to provide the maximized communication quantity, and the standardized power pin array is used for merging the power supply requirements of a plurality of different functional units to provide the maximized power rail quantity.

Preferably, in the second step, the micro-module-level interconnection substrate interconnects the corresponding master core particle and the memory core particle in the substrate.

Preferably, in the third step, different functional unit micro-modules are provided with the micro-module level interconnection substrate with standardized PAD distribution at the bottom thereof, so as to realize compatibility of pin definition among different functional units.

Preferably, in the fourth step, the mode of the standardized PAD distribution array on top of the wafer-level interconnection substrate is determined according to the wafer size and the application requirement.

In the fourth step, the communication paths in the wafer-level interconnection substrate are all required to be subjected to signal integrity simulation optimization according to the highest communication speed so as to ensure the communication requirements of all the functional units, and the power supply planes in the wafer-level interconnection substrate are all required to be subjected to power integrity simulation optimization according to the maximum power supply level and current so as to ensure the power supply requirements of all the functional units.

Preferably, in the fifth step, the type and number of the mounted functional units are arbitrarily selected according to the application requirements, and different functional units can be mounted on any one of the standardized PAD distributions on the wafer interconnection substrate.

The invention also provides a system-on-chip standardized interconnection structure, which adopts the method for realizing the system-on-chip standardized interconnection substrate, comprising the following steps:

Each functional unit micro-module comprises a functional unit and a micro-module-level interconnection substrate, wherein the functional units are attached to the micro-module-level interconnection substrate, each functional unit consists of a main control core particle and a storage core particle, and the main control core particle comprises CPU, FPGA, DSP and AI;

the wafer-level interconnection substrate is provided with one, and is attached with a plurality of different functional unit micro-modules.

Compared with the prior art, the invention has the following beneficial effects:

The invention provides a method for realizing standardized interconnection substrates of system on chip, which comprises the steps of combining various main control core particles with various storage core particles to form various functional units, fully analyzing intra-crystal signal interconnection requirements, extra-crystal communication requirements and maximum power supply requirements among all the functional units, defining standard PAD distribution in a merging mode to form a group of functional unit micro-modules with standard PAD distribution, selecting any kind and number of functional unit micro-modules according to application requirements, and attaching the functional unit micro-modules to wafer-level interconnection substrates with standard PAD distribution arrays to form the system on chip. The implementation method of the standardized interconnection substrate of the system on a chip can break a customized framework, carry out multi-level classification on core particles to form a functional unit micro-module design library with standard PAD distribution, randomly select micro-modules according to application requirements to be attached to the wafer-level standard interconnection substrate, only need to increase the design of the micro-module-level interconnection substrate even if the chip type is selected to exceed the design library, greatly reduce design difficulty and design period, improve design efficiency and one-time design success rate, and promote the construction of the ecology of the system on a chip design.

Drawings

Fig. 1 is a flowchart of a method for implementing a standardized interconnection substrate of a system on a chip in an embodiment of the present invention.

FIG. 2 is a schematic diagram of a system-on-chip standardized interconnect structure in accordance with an embodiment of the present invention.

FIG. 3 is a simplified schematic diagram of PAD distribution [ A ] in an embodiment of the present invention.

Fig. 4 is a schematic diagram illustrating distribution of PAD on top of a wafer level interconnect substrate in accordance with an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

As shown in fig. 1, an embodiment of the present invention provides a method for implementing a standardized interconnection substrate of a system on a chip, including the following steps:

firstly, arranging and combining core particles integrated in a crystal upper system to form a plurality of functional units;

respectively designing micro-module-level interconnection substrates with the same PAD distribution at the bottoms aiming at different functional units to form standardized PAD distribution;

thirdly, different micro-module-level interconnection substrates with standardized PAD distribution at the bottoms are respectively attached with corresponding core particles according to the different functional units to form a plurality of functional unit micro-modules;

Designing a wafer-level interconnection substrate with a standardized PAD distributed array at the top, and completing wiring design shaping according to interconnection communication requirements, external communication requirements and power supply requirements in the wafer-level interconnection substrate;

and fifthly, attaching different types and different numbers of functional unit micro-modules to the wafer-level interconnection substrate according to application requirements to realize standardized interconnection.

As shown in fig. 2, the embodiment of the present invention provides a standardized interconnection structure of a system on chip, which can be specifically divided into three levels, a first level is a plurality of functional units composed of a master control core and a storage core, a second level is a plurality of micro-module level interconnection substrates, and a third level is a wafer level interconnection substrate, wherein the master control core includes but is not limited to CPU, FPGA, DSP, AI, the storage core includes but is not limited to DDRx and FLASH, and the first level and the second level constitute a plurality of functional unit micro-modules.

With continued reference to fig. 2, the first layer is a functional unit group consisting of a main control core particle and a storage core particle, such as a functional unit a [ cpu+ddrx+flash ], a functional unit B [ fpga+ddrx+flash ], a functional unit C [ ai+ddrx+flash ], and a functional unit D [ dsp+ddrx+flash ], the second layer is a micro-module-level interconnection substrate with the same PAD distribution [ a ] at the bottom, each functional unit realizes intra-substrate interconnection, external communication and standardized leading-out of power supply signals through the micro-module-level interconnection substrate to form a standardized micro-module group, the third layer is a wafer-level interconnection substrate with a standardized PAD distribution [ a ] array at the top, a standard intra-wafer interconnection communication path, a standard external wafer communication path and a standard power supply path are designed in the wafer interconnection substrate, and various micro-modules can be attached to any PAD distribution [ a ] of the wafer-level interconnection substrate, and realize intra-wafer interconnection, external communication and power supply requirements through the wafer-level interconnection substrate.

With continued reference to FIG. 3, a simplified diagram of a PAD distribution [ A ] according to an embodiment of the present invention is shown. Firstly, the requirements of the four functional units of the functional unit A, the functional unit B, the functional unit C and the functional unit D, such as intra-crystal interconnection communication, off-crystal communication and the like, are combined and reasonably distributed to form a standard signal pin array, and secondly, the requirements of the four functional units of the functional unit A, the functional unit B, the functional unit C and the functional unit D, such as power supply requirements are combined and reasonably distributed to provide the maximum power supply rail number considering the communication requirements of all the functional units. Finally, PAD distribution [ A ] formed by three standardized pin arrays of a signal, a power supply and a ground is formed.

With continued reference to fig. 4, a schematic diagram of a top PAD distribution of a wafer level interconnect substrate according to an embodiment of the present invention is shown. According to the size of the wafer-level interconnection substrate and the size of each functional unit micro-module, a plurality of PADs (personal data access) A are arranged on the top of the wafer-level interconnection substrate, each functional unit micro-module can be attached to any PAD A of the wafer interconnection substrate, and the requirements of intra-die interconnection communication, out-of-die communication and power supply are met.

In summary, the method combines a plurality of main control core grains and storage core grains integrated in an on-chip system under various application scenes into a plurality of functional units in a multi-mode, and defines standard PAD distribution [ A ] by respectively merging and reasonably distributing the intra-chip signal interconnection requirements, the off-chip communication requirements and the power supply requirements of all the functional units, wherein the standard PAD distribution [ A ] can provide the maximized number of power supply rails while simultaneously maximizing the communication requirements, thereby forming a group of functional unit micro-module groups with the standard PAD distribution [ A ]. A plurality of PADs (personal digital Association) are arranged on the top of the wafer-level interconnection substrate, and functional unit micro-modules of any kind and number can be selected according to application requirements and can be attached to the wafer-level interconnection substrate with a standard PAD distribution array to form a system on a wafer. The method can break the customized architecture of the system on the chip, reduce the design and processing of the wafer-level interconnection substrate which is once complicated and time-consuming due to the modification of the core particle selection, improve the design efficiency and the once design success rate, break the integration barriers of different manufacturers and promote the ecological construction of the system on the chip design.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. A method for implementing a standardized interconnect substrate for an on-wafer system, comprising:

Step 1: Arrange and combine the core particles integrated in the on-wafer system to form a variety of different functional units;

Step 2: providing different micro-module-level interconnect substrates with standardized PAD distribution on the bottom;

Step 3: Attach different micro-module-level interconnect substrates with standardized PAD distribution on the bottom to the corresponding core particles according to the above-mentioned different functional units to form a variety of different functional unit micro-modules;

Step 4: Provide a wafer-level interconnect substrate with a standardized PAD distribution array on the top, and complete the wiring design of the wafer-level interconnect substrate based on the interconnection communication requirements, external communication requirements, and power supply requirements;

Step 5: Based on application requirements, different types and quantities of functional unit micromodules are mounted on the wafer-level interconnect substrate to achieve standardized interconnection.

2. A method for implementing a standardized interconnection substrate for a system on a die as described in claim 1, characterized in that in step 1, the functional unit is composed of a main control chip and a storage chip, the main control chip includes a CPU, FPGA, DSP and AI; the storage chip includes DDRx and FLASH.

3. The method for implementing a standardized interconnect substrate for an on-wafer system as described in claim 1, wherein in step 2, the standardized PAD distribution includes a standardized signal pin array, a standardized power pin array, and a standardized ground pin array.

4. A method for implementing a standardized interconnect substrate for an on-chip system as described in claim 3, characterized in that, through the standardized signal pin array, the intra-chip interconnect communication requirements and the extra-chip communication requirements between multiple different functional units are combined to provide a maximized communication quantity; and through the standardized power pin array, the power supply requirements of multiple different functional units are combined to provide a maximized power rail quantity.

5. The method for implementing a standardized interconnection substrate for an on-chip system according to claim 1, wherein in step 2, the micro-module-level interconnection substrate interconnects corresponding master control cores and storage cores within the substrate.

6. A method for implementing a standardized interconnection substrate for an on-chip system as described in claim 1, characterized in that in step three, different functional unit micromodules are interconnected through a micromodule-level substrate with a standardized PAD distribution at the bottom of each of the micromodules to achieve compatibility of pin definitions between different functional units.

7. The method for implementing a standardized interconnect substrate for an on-wafer system as described in claim 1, characterized in that in the step 4, the manner of distributing the standardized PAD array on the top of the wafer-level interconnect substrate is determined according to the wafer size and application requirements.

8. A method for implementing a standardized interconnect substrate for wafer-level systems as described in claim 1, characterized in that in step 4, the communication paths in the wafer-level interconnect substrate are required to undergo signal integrity simulation optimization according to the maximum communication rate to ensure the communication requirements of all functional units; and the power supply planes in the wafer-level interconnect substrate are required to undergo power integrity simulation optimization according to the maximum power supply level and current to ensure the power supply requirements of all functional units.

9. A method for implementing a standardized interconnection substrate for an on-wafer system as described in claim 1, characterized in that, in the step five, the type and quantity of the functional units to be mounted are arbitrarily selected according to application requirements, and different functional units can be mounted to any standardized PAD distribution on the wafer interconnection substrate.

10. A standardized interconnect structure for a system on a wafer, comprising:

There are multiple functional unit micromodules; each of the functional unit micromodules includes a functional unit and a micromodule-level interconnect substrate, on which the functional unit is mounted; each of the functional units is composed of a main control chip and a storage chip, the main control chip includes a CPU, FPGA, DSP and AI; the storage chip includes DDRx and FLASH;

A wafer-level interconnect substrate is provided, wherein a plurality of different functional unit micromodules are mounted on the wafer-level interconnect substrate.