CN120431988A - A Design Method for Online Non-Destructive Test of SRAM - Google Patents

Abstract

The invention relates to the technical field of SRAM fault detection, and discloses a Online Non Destructive Test design method for SRAM, wherein a CPU configures an NDT controller through an APB bus and reads information, and meanwhile, the CPU or other Master accesses the SRAM through an AXI after Arbit; the Arbit module completes the access of AXI to SRAM and the arbitration of NDT controller to SRAM. The Online Non Destructive Test design method for the SRAM can flexibly execute an Online NDT test, has configurable mode, supports the test by utilizing an AXI bus to access the gap of the SRAM, does not influence the performance at all, supports the completion of the Online NDT test by forcing to occupy part of the bandwidth if the AXI bus is accessed by the SRAM densely, and simultaneously supports the periodic automatic Online NDT. The whole scheme can not influence the access of system transactions to the SRAM completely, supports automatic periodic test, realizes online, real-time and automatic non-destructive test of the SRAM, and meets the safety requirement of vehicle rule functions.

Description

Online Non Destructive Test design method for SRAM

Technical Field

The invention relates to the technical field of SRAM fault detection, in particular to a Online Non Destructive Test design method for an SRAM.

Background

Non-Destructive Test SRAM, namely Non-destructive test of SRAM, is a method for detecting functions, performance, reliability and the like of SRAM under the premise of not damaging an SRAM chip or changing physical structure and performance of the SRAM chip.

The detecting content comprises the following steps:

(1) The functional test, namely writing various data modes such as all 0, all 1, alternate 01 and the like into a memory unit of the SRAM, then reading out data, comparing the data with the written data, checking whether the data can be correctly read and written, if the read data is inconsistent with the written data, indicating that the memory unit has functional faults, testing an address decoding circuit, a data input/output buffer and the like, and checking whether the data can be correctly responded to address signals and data transmission;

(2) The built-in self test (MBIST) is that a test circuit and an algorithm are integrated in an SRAM chip, external complex test equipment is not needed during test, read-write operation and data comparison are carried out on a storage unit through internal test logic, a test process is completed, for example, a March test algorithm is commonly used for the MBIST, and various faults in the SRAM are detected through a specific read-write sequence;

(3) The Online MBIST generally adopts a time slicing or virtual machine mode to perform testing, and a test controller can insert a test operation in a gap of normal operation of a chip, such as a system idle period, an idle period of instruction execution, and the like.

The MBIST can only be used before data initialization, and the test can destroy the original data of the SRAM. When time slicing test is adopted, a processor is required to be responsible for realizing test management, system load is increased, automatic periodic test cannot be realized, and in order to realize efficient and flexible Online NDT design, the application provides a Online Non Destructive Test design method for SRAM to solve the problems.

Disclosure of Invention

(One) solving the technical problems

Aiming at the defects of the prior art, the invention provides a Online Non Destructive Test design method for SRAM, which can support online, real-time and automatic non-destructive test of SRAM, and does not need continuous intervention of a processor or influence the running of the prior program.

(II) technical scheme

The technical scheme is that the method for designing the Online Non Destructive Test of the SRAM comprises the steps that a CPU is configured with an NDT controller through an APB bus and reads information, meanwhile, the CPU or other Master accesses the SRAM after the CPU or other Master passes Arbit through an AXI, the NDT controller completes an Online test on an SRAM space, and a Arbit module completes access of the AXI to the SRAM and arbitration of access of the NDT controller to the SRAM.

Preferably, the NDT controller supports three modes:

(1) Single address NDT mode;

(2) An address range NDT mode;

(3) Periodic address range NDT mode.

Preferably, the working mechanism of the single address NDT mode is as follows:

the CPU configures the address x to be tested to the NDT controller, starts the test, and the test steps are as follows:

S1, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, reading data of an address x from the SRAM by the NDT controller through Arbit, and registering the data into the NDT controller;

S2, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing the data into an address x of the SRAM after the data is inverted by the NDT controller, comparing the data with the original data after the data is read again, and recording a test result;

S3, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data in 0 to address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

s4, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 1 into an address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

s5, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 0x5555 (the data depends on the data width of the SRAM) into the address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

S6, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 0xAAAA (the data depends on the data width of the SRAM) into the address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

S7, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing original data into an address x of the SRAM by the NDT controller, and setting a test completion flag of the NDT controller.

Preferably, the working mechanism of the address range NDT mode is as follows:

The CPU configures the address space range to be tested to the NDT controller and starts the test, and the test steps are as follows, all addresses are polled according to a single address NDT test method, and finally the NDT controller test completion flag is set.

Preferably, the working mechanism of the periodic address interval range NDT mode is as follows:

the CPU configures the address space range and time interval to be tested to the NDT controller, and starts the test, and the test steps are as follows:

s1, all addresses are polled according to a single address NDT test method, and finally a NDT controller test completion flag is set;

s2, starting the NDT again after waiting for the interval time until the CPU sets the NDT to stop.

Preferably, when there is an access request from the AXI bus and NDT controller, the Arbit module is responsible for arbitrating and completing data transfer, and the Arbit module supports two modes:

(1) A scheduling mode;

(2) AXI accesses priority mode.

Preferably, the working mechanism of the scheduling mode is as follows:

A. When the AXI bus access and the NDT controller access arrive at the same time, scheduling according to a preset weight, deciding to suspend a request of the NDT controller or a request of the AXI bus access, and responding to another request;

B. When an AXI bus accesses the SRAM, if an NDT access request comes, suspending the NDT access request temporarily, and not starting to process the NDT access request until the current AXI access is completed, so that a new AXI access request happens to come, and scheduling according to configuration weights;

C. when the NDT is testing and accessing the SRAM, if an AXI access request comes, scheduling according to the configuration weight in the next clock period;

D. when the address of the data accessed by the AXI bus is the same as the address being NDT tested, the data is returned by the NDT controller (read operation) or saved to the NDT controller's data cache (write operation).

Preferably, the working mechanism of the AXI access priority mode is as follows:

A. When the AXI bus access and the NDT controller access arrive at the same time, suspending the request of the NDT controller, preferentially processing the access from the AXI bus, and when the AXI bus access is finished, giving the access authority to the NDT controller;

B. When the NDT is in test access to the SRAM, if an AXI bus access arrives, suspending the NDT test in the next clock period, directly processing the AXI bus access, and after the AXI bus access is ended, carrying out the next step of the NDT test of the address;

C. When the address of the data accessed by the AXI bus is the same as the address being NDT tested, the data is returned by the NDT controller.

(III) beneficial effects

Compared with the prior art, the invention has the following beneficial effects:

the invention can flexibly execute the Online NDT test, has configurable mode, supports small granularity test and large area test, can select to utilize a system bus to access a small gap of the SRAM for test without influencing performance, can select to occupy part of bandwidth forcefully to complete the Online NDT test when the AXI bus accesses the SRAM densely, ensures that the test can be executed, supports periodic automatic starting of the Online NDT, completely does not need a CPU for scheduling and arranging, ensures that the Online NDT adopts backup data to ensure that the test does not influence the normal access of the bus to a tested unit, also ensures that the data is consistent before and after the test and cannot be destroyed.

Drawings

Fig. 1 is a schematic diagram of an architecture of the technical scheme of the present invention.

Detailed Description

The technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, in order to implement efficient and flexible Online NDT design, the present invention proposes a Online Non Destructive Test design method for SRAM, in which a CPU configures an NDT controller via an APB bus and reads information, and at the same time, the CPU or other masters access the SRAM via an AXI via Arbit, the NDT controller completes Online test on the SRAM space, and a Arbit module completes access of the AXI to the SRAM and arbitration of access of the NDT controller to the SRAM, where the NDT controller supports three modes:

(1) Single address NDT mode;

(2) An address range NDT mode;

(3) Periodic address range NDT mode.

The working mechanism of the single address NDT mode is as follows:

the CPU configures the address x to be tested to the NDT controller, starts the test, and the test steps are as follows:

S1, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, reading data of an address x from the SRAM by the NDT controller through Arbit, and registering the data into the NDT controller;

S2, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing the data into an address x of the SRAM after the data is inverted by the NDT controller, comparing the data with the original data after the data is read again, and recording a test result;

S3, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data in 0 to address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

s4, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 1 into an address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

s5, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 0x5555 (the data depends on the data width of the SRAM) into the address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

S6, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 0xAAAA (the data depends on the data width of the SRAM) into the address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

S7, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing original data into an address x of the SRAM by the NDT controller, and setting a test completion flag of the NDT controller.

The working mechanism of the address interval range NDT mode is as follows:

The CPU configures the address space range to be tested to the NDT controller and starts the test, and the test steps are as follows, all addresses are polled according to a single address NDT test method, and finally the NDT controller test completion flag is set.

The working mechanism of the periodic address interval range NDT mode is as follows:

the CPU configures the address space range and time interval to be tested to the NDT controller, and starts the test, and the test steps are as follows:

s1, all addresses are polled according to a single address NDT test method, and finally a NDT controller test completion flag is set;

s2, starting the NDT again after waiting for the interval time until the CPU sets the NDT to stop.

When there is an access request from the AXI bus and NDT controller, the Arbit module is responsible for arbitrating and completing data transfer, arbit module supports two modes:

(1) A scheduling mode;

(2) AXI accesses priority mode.

The working mechanism of the scheduling mode is as follows:

A. When the AXI bus access and the NDT controller access arrive at the same time, scheduling according to a preset weight, deciding to suspend a request of the NDT controller or a request of the AXI bus access, and responding to another request;

B. When an AXI bus accesses the SRAM, if an NDT access request comes, suspending the NDT access request temporarily, and not starting to process the NDT access request until the current AXI access is completed, so that a new AXI access request happens to come, and scheduling according to configuration weights;

C. when the NDT is testing and accessing the SRAM, if an AXI access request comes, scheduling according to the configuration weight in the next clock period;

D. when the address of the data accessed by the AXI bus is the same as the address being NDT tested, the data is returned by the NDT controller (read operation) or saved to the NDT controller's data cache (write operation).

It should be noted that, the AXI bus access SRAM refers to a complete transaction access SRAM, and includes reading or writing for a plurality of clock cycles (typically 1-16 if the SRAM width and the bus data size are the same).

The working mechanism of the AXI access priority mode is as follows:

A. When the AXI bus access and the NDT controller access arrive at the same time, suspending the request of the NDT controller, preferentially processing the access from the AXI bus, and when the AXI bus access is finished, giving the access authority to the NDT controller;

B. When the NDT is in test access to the SRAM, if an AXI bus access arrives, suspending the NDT test in the next clock period, directly processing the AXI bus access, and after the AXI bus access is ended, carrying out the next step of the NDT test of the address;

C. When the address of the data accessed by the AXI bus is the same as the address being NDT tested, the data is returned by the NDT controller.

The invention can flexibly execute the Online NDT test, has configurable mode, supports small granularity test and large area test, can select to utilize a system bus to access a small gap of the SRAM for test without influencing performance, can select to occupy part of bandwidth forcefully to complete the Online NDT test when the AXI bus accesses the SRAM densely, ensures that the test can be executed, supports periodic automatic starting of the Online NDT, completely does not need a CPU for scheduling and arranging, ensures that the Online NDT adopts backup data to ensure that the test does not influence the normal access of the bus to a tested unit, also ensures that the data is consistent before and after the test and cannot be destroyed.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (8)

1. A design method for Online Non Destructive Test of SRAM, characterized by:

The CPU configures an NDT controller through an APB bus and reads information, and meanwhile, the CPU or other Master accesses the SRAM through an AXI after Arbit;

the NDT controller completes the Online test of the SRAM space;

The Arbit module completes the access of the AXI to the SRAM and the arbitration of the access of the NDT controller to the SRAM.

2. The design method for Online Non Destructive Test of claim 1, wherein said NDT controller supports three modes:

(1) Single address NDT mode;

(2) An address range NDT mode;

(3) Periodic address range NDT mode.

3. The method for designing Online Non Destructive Test of SRAM according to claim 2, wherein the single address NDT mode is operated by the following mechanism:

the CPU configures the address x to be tested to the NDT controller, starts the test, and the test steps are as follows:

S1, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, reading data of an address x from the SRAM by the NDT controller through Arbit, and registering the data into the NDT controller;

S2, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing the data into an address x of the SRAM after the data is inverted by the NDT controller, comparing the data with the original data after the data is read again, and recording a test result;

S3, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data in 0 to address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

s4, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 1 into an address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

s5, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 0x5555 (the data depends on the data width of the SRAM) into the address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

S6, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing data 0xAAAA (the data depends on the data width of the SRAM) into the address x of the SRAM by the NDT controller, reading again, comparing, and recording a test result;

S7, sending an access request to Arbit, if Arbit is not answered, waiting, otherwise, writing original data into an address x of the SRAM by the NDT controller, and setting a test completion flag of the NDT controller.

4. The method for designing Online Non Destructive Test of SRAM according to claim 2, wherein the operation mechanism of the address range NDT mode is:

The CPU configures the address space range to be tested to the NDT controller and starts the test, and the test steps are as follows, all addresses are polled according to a single address NDT test method, and finally the NDT controller test completion flag is set.

5. The method for designing an SRAM Online Non Destructive Test according to claim 2, wherein the periodic address range NDT mode is operated by:

the CPU configures the address space range and time interval to be tested to the NDT controller, and starts the test, and the test steps are as follows:

s1, all addresses are polled according to a single address NDT test method, and finally a NDT controller test completion flag is set;

s2, starting the NDT again after waiting for the interval time until the CPU sets the NDT to stop.

6. A method of designing Online Non Destructive Test for an SRAM according to any one of claims 3-5, wherein when there is an access request from the AXI bus and NDT controller, the Arbit module is responsible for arbitrating and completing data transfer, and the Arbit module supports two modes:

(1) A scheduling mode;

(2) AXI accesses priority mode.

7. The method of claim 6, wherein the scheduling mode is implemented by the following mechanism:

A. When the AXI bus access and the NDT controller access arrive at the same time, scheduling according to a preset weight, deciding to suspend a request of the NDT controller or a request of the AXI bus access, and responding to another request;

B. When an AXI bus accesses the SRAM, if an NDT access request comes, suspending the NDT access request temporarily, and not starting to process the NDT access request until the current AXI access is completed, so that a new AXI access request happens to come, and scheduling according to configuration weights;

C. when the NDT is testing and accessing the SRAM, if an AXI access request comes, scheduling according to the configuration weight in the next clock period;

D. When the address of the data accessed by the AXI bus is the same as the address being NDT tested, the data is returned by the NDT controller.

8. The method of claim 6, wherein the AXI access priority mode is implemented by the following mechanism:

A. When the AXI bus access and the NDT controller access arrive at the same time, suspending the request of the NDT controller, preferentially processing the access from the AXI bus, and when the AXI bus access is finished, giving the access authority to the NDT controller;

B. When the NDT is in test access to the SRAM, if an AXI bus access arrives, suspending the NDT test in the next clock period, directly processing the AXI bus access, and after the AXI bus access is ended, carrying out the next step of the NDT test of the address;

C. When the address of the data accessed by the AXI bus is the same as the address being NDT tested, the data is returned by the NDT controller.