CN120407108A - Data synchronization scheduling method, data synchronization scheduling system and processor - Google Patents
Data synchronization scheduling method, data synchronization scheduling system and processorInfo
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- CN120407108A CN120407108A CN202510490623.XA CN202510490623A CN120407108A CN 120407108 A CN120407108 A CN 120407108A CN 202510490623 A CN202510490623 A CN 202510490623A CN 120407108 A CN120407108 A CN 120407108A
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Abstract
The application discloses a data synchronous scheduling method, a data synchronous scheduling system and a processor. According to the scheme, target data and a data writing address to be written into an FPGA are obtained, data interaction is conducted between the FPGA and an application program through a JTAG interface, corresponding data in an intermediate data file is updated based on the target data and the data writing address, the numerical value of a counter in the intermediate data file is increased to obtain an updated intermediate data file, the numerical value of the counter in the updated intermediate data file is used for indicating the FPGA to execute data synchronous scheduling with the application program, and the data synchronous scheduling with the FPGA is executed based on the updated intermediate data file. The technical scheme of the application solves the technical problem that effective data synchronous scheduling is difficult to realize due to the limitation of the JTAG interface when the data interaction is carried out between the prior FPGA and the application program through the JTAG interface, and improves the reliability of the data synchronous scheduling.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a data synchronization scheduling method, a data synchronization scheduling system, and a processor.
Background
Currently, embedded systems based on FPGA (collectively referred to as Field-Programmable GATE ARRAY, i.e., field Programmable gate array) are widely used in the fields of industrial control, autopilot, etc., where efficient synchronous scheduling between software (e.g., GCKontrol, i.e., system design and simulation software) and FPGA hardware becomes a key constraint factor for system performance.
Conventional synchronous scheduling mechanisms typically rely on interactions such as external triggers (e.g., interrupts, polling equivalent scheduling mechanisms), etc. However, when the software and the FPGA realize loop communication through a specific interface (e.g., a JTAG interface), due to inherent serial transmission characteristics of the specific interface and limited debug resources (e.g., issues such as timing constraint conflict, bandwidth bottleneck, protocol rigidification, etc.), the conventional synchronous scheduling mechanism is easy to fail, so that problems of data transmission delay, data error or loss occur, and thus it is difficult to effectively realize data synchronous scheduling between the software and the FPGA.
Disclosure of Invention
Based on the above problems, the application provides a data synchronous scheduling method, a data synchronous scheduling system and a processor, which aim to solve the technical problem that effective data synchronous scheduling is difficult to realize due to the limitation of JTAG interface when the data interaction is carried out between the prior FPGA and the application program through the JTAG interface, and improve the reliability of the data synchronous scheduling.
The embodiment of the application discloses the following technical scheme:
in a first aspect of the present application, a data synchronization scheduling method is provided, and is applied to an application program, where an operation of the application program is executed on a main thread, and the method includes:
the method comprises the steps of obtaining target data and a data writing address to be written into an FPGA, wherein the operation of the FPGA is executed on a sub-thread created by an application program, and the FPGA and the application program interact data through a JTAG interface;
Updating corresponding data in an intermediate data file based on the target data and the data writing address, and increasing the numerical value of a counter in the intermediate data file to obtain an updated intermediate data file;
and executing data synchronous scheduling with the FPGA based on the updated intermediate data file.
In an optional implementation manner, the performing data synchronization scheduling with the FPGA based on the updated intermediate data file includes:
The FPGA is used for reading data in the updated intermediate data file from the preset storage area, writing the target data into a memory area of the FPGA based on the data writing address when the value of the counter is determined to be larger than a historical value, wherein the historical value is the value of the counter which is read from the intermediate data file by the FPGA last time.
In an optional implementation manner, the intermediate data file further includes a data synchronization state of a counter, where the data synchronization state is used to characterize whether the target data is synchronized to the FPGA, and the data synchronization scheduling method further includes:
detecting whether the current moment is a first target moment or not, wherein the first target moment is the detection moment of the data synchronization state;
if the current time is the first target time, judging whether the target data is synchronized to the FPGA or not based on the data synchronization state;
If the target data is synchronized to the FPGA, allowing a data updating operation to be executed, wherein the data updating operation is used for updating the data in the intermediate data file;
And if the target data is not synchronized to the FPGA, prohibiting the execution of the data updating operation.
In a second aspect of the present application, a data synchronization scheduling method is provided, and the method is applied to an FPGA, where operation of the FPGA is performed on a sub-thread created by an application program, operation of the application program is performed on a main thread, and the FPGA is configured to perform data interaction with the application program through a JTAG interface, and the method includes:
Detecting whether the current time is a second target time or not, wherein the second target time is the time when the FPGA detects whether to execute data synchronous scheduling with the application program or not;
If the current time is the second target time, running a TCL script to read data in an intermediate data file from a preset storage area of the application program, wherein the data comprises target data to be written into an FPGA, a data writing address and a numerical value of a counter, and the numerical value of the counter is used for indicating whether the FPGA executes data synchronous scheduling with the application program or not;
And if the numerical value of the counter is larger than the historical numerical value, executing data synchronous scheduling with the application program, wherein the historical numerical value is the numerical value of the counter read from the intermediate data file by the FPGA last time.
In an alternative implementation, the performing the data synchronization scheduling with the application program includes:
And calling a data writing function based on the target data and the data writing address, and writing the target data into a memory area matched with the data writing address.
In an alternative implementation manner, after the target data is written into the memory area matched with the data writing address, the data synchronous scheduling method further includes:
Generating feedback information based on the target data to be written into the FPGA and the data writing address, wherein the feedback information is used for representing that the target data is synchronized to the FPGA;
The application program is used for updating the data synchronization state of the counter in the intermediate data file based on the feedback information, determining whether to execute a data updating operation or not based on the data synchronization state, wherein the data updating operation is used for updating the data in the intermediate data file.
The application provides a data synchronous scheduling system, which comprises an application program and an FPGA, wherein the operation of the application program is executed on a main thread, the operation of the FPGA is executed on a sub-thread created by the application program, and the data interaction is carried out between the FPGA and the application program through a JTAG interface;
The application program is used for acquiring target data and a data writing address to be written into the FPGA, updating corresponding data in an intermediate data file based on the target data and the data writing address, and increasing the numerical value of a counter in the intermediate data file to obtain an updated intermediate data file;
The FPGA is used for detecting whether the current time is a second target time, if the current time is the second target time, a TCL script is operated to read data in the intermediate data file from the preset storage area, the second target time is the time when the FPGA detects whether to execute data synchronous scheduling with the application program, the data comprises target data to be written into the FPGA, a data writing address and a numerical value of a counter, the numerical value of the counter is used for indicating whether the FPGA executes data synchronous scheduling with the application program, and if the numerical value of the counter is determined to be larger than a historical numerical value, the FPGA is used for executing data synchronous scheduling with the application program, and the historical numerical value is the numerical value of the counter read from the intermediate data file by the FPGA last time.
In an alternative implementation manner, the FPGA is further configured to invoke a data write function based on the target data and the data write address, and write the target data into a memory area that matches the data write address.
In a fourth aspect of the present application, a computer readable storage medium is provided, in which a computer program is stored, which when executed by a processor, implements the above-mentioned data synchronization scheduling method.
In a fifth aspect of the present application, a processor is provided for running a computer program, where the computer program executes the data synchronization scheduling method described above.
Compared with the prior art, the application has the following beneficial effects:
According to the technical scheme, the operation of the application program is executed on the main thread, the operation of the FPGA is executed on the sub-thread created by the application program, the data interaction is carried out between the FPGA and the application program through the JTAG interface sharing intermediate data file, the parallel execution and mutual noninterference of the operation of the FPGA and the operation of the application program are realized, the target data and the data writing address to be written into the FPGA are obtained, the corresponding data in the intermediate data file is updated based on the target data and the data writing address, the numerical value of the counter in the intermediate data file is increased, the updated intermediate data file is obtained, the data synchronous scheduling between the FPGA and the application program can be timely instructed based on the update mechanism of the intermediate data file, and therefore, the data synchronous scheduling between the FPGA and the target data to be written into the FPGA can be effectively executed based on the updated intermediate data file, the problem of data transmission delay, data error or loss caused by limitation of the JTAG interface is avoided, the problem of the data transmission is difficult to be caused by limitation of the prior art when the JTAG interface is used for carrying out the data synchronous scheduling through the JTAG interface, and the problem of the data synchronous scheduling is difficult to realize due to the fact that the data is subjected to the data synchronous scheduling by the interface is scheduled.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a flowchart of a data synchronization scheduling method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an intermediate data file according to an embodiment of the present application;
FIG. 3 is a flowchart illustrating a data update operation according to an embodiment of the present application;
FIG. 4 is a flowchart of another method for data synchronization scheduling according to an embodiment of the present application;
FIG. 5 is a flowchart of a feedback information generation process according to an embodiment of the present application;
Fig. 6 is a schematic structural diagram of a data synchronous scheduling system according to an embodiment of the present application.
Detailed Description
As described above, conventional synchronous scheduling mechanisms typically rely on interactions such as external triggers (e.g., interrupts, polling-equivalent scheduling mechanisms), etc. However, when the software and the FPGA realize loop communication through a specific interface (e.g., a JTAG interface), due to inherent serial transmission characteristics of the specific interface and limited debug resources (e.g., issues such as timing constraint conflict, bandwidth bottleneck, protocol rigidification, etc.), the conventional synchronous scheduling mechanism is easy to fail, so that problems of data transmission delay, data error or loss occur, and thus it is difficult to effectively realize data synchronous scheduling between the software and the FPGA.
The inventor has studied and put forward a high-efficient data synchronous scheduling method, in this scheme, through making the operation of the application program carry out on the main thread, the operation of FPGA carries out on the sub-thread that the application program creates, the data interaction is carried on through JTAG interface shared intermediate data file between FPGA and the application program, have realized the operation of FPGA and operation parallel execution of the application program, mutual noninterference; the method comprises the steps of obtaining target data and a data writing address to be written into an FPGA, updating corresponding data in an intermediate data file based on the target data and the data writing address, and increasing the numerical value of a counter in the intermediate data file to obtain an updated intermediate data file, so that the data synchronous scheduling between the FPGA execution and an application program can be timely instructed through the numerical value of the updated counter (namely the numerical value of the counter in the updated intermediate data file) based on an updating mechanism of the intermediate data file; therefore, based on the updated intermediate data file, the data synchronous scheduling with the FPGA can be efficiently executed, so that target data and data writing addresses to be written into the FPGA are synchronized to the FPGA, the problems of data transmission delay, data errors or loss caused by the limitation of a JTAG interface are avoided, the technical problem that effective data synchronous scheduling is difficult to realize due to the limitation of the JTAG interface when the data interaction is carried out between the existing FPGA and an application program through the JTAG interface is solved, and the reliability of the data synchronous scheduling is improved.
In order to make the present application better understood by those skilled in the art, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Keyword definition:
FPGA is an abbreviation of Field-Programmable GATE ARRAY, chinese is a Field Programmable gate array. The integrated circuit chip is a hardware reconfigurable integrated circuit chip, and is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs). FPGAs are a product of further development on the basis of programmable devices such as programmable array logic, general-purpose array logic, erasable programmable logic devices, and the like. It can be designed into different circuits, allowing the circuit designer to define its functions by writing hardware description languages (such as VHDL or Verilog) as needed, and then "burn" these designs onto the FPGA, performing specific hardware functions in practical applications.
JTAG interface is called Joint Test Action Group interface, which is used to test and debug Integrated Circuits (ICs) with pins, such as microprocessor, FPGA, etc. It defines a standard test interface called IEEE 1149.1 that allows Boundary-scan testing (Boundary-SCAN TESTING) of components on a circuit board, even though the components have been soldered to the circuit board.
TCL script TCL (totally called ToolCommand Language, tool command language) is a script language and is widely applied to the fields of software development, automatic test, prototype design, GUI development, network management and the like. Which is well known for its simplicity, flexibility and ease of embedding in other applications.
Method embodiment one
The embodiments of the present application provide an embodiment of a data synchronization scheduling method, it should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
Referring to fig. 1, a flowchart of a data synchronization scheduling method according to an embodiment of the present application is provided, where the method is applied to an application program (e.g. GCKontrol, i.e. system design and simulation software). Wherein the operation of the application program is executed on the main thread. The data synchronous scheduling method comprises the following steps:
step S101, obtaining target data to be written into the FPGA and a data writing address.
In step S101, the operation of the FPGA is performed on the sub-thread created by the application program, and data interaction is performed between the FPGA and the application program through the JTAG interface.
In the embodiment of the application, the target data to be written into the FPGA may be related data or simulation data input by a user, and the data writing address may be an address of a memory area in the FPGA. The application program can provide a data basis for corresponding data in the intermediate data file to be updated later by acquiring target data to be written into the FPGA and a data writing address.
By executing the operation of the application program on the main thread, the operation of the FPGA is executed on the sub-thread created by the application program, and the data interaction between the FPGA and the application program is performed through the JTAG interface, so that the parallel execution and mutual noninterference of the operation of the FPGA and the operation of the application program are realized through the independent thread mode.
Step S102, updating corresponding data in the intermediate data file based on the target data and the data writing address, and increasing the numerical value of the counter in the intermediate data file to obtain the updated intermediate data file.
In step S102, the value of the counter in the updated intermediate data file is used to indicate the data synchronization scheduling between the FPGA execution and the application. In the embodiment of the application, the value of the counter is accumulated once (for example, one is added on the basis of the original value) every time the corresponding data in the intermediate data file is updated, so as to increase the value of the counter in the intermediate data file, and the data synchronous scheduling between the FPGA execution and the application program is realized through the updated value of the counter in the intermediate data file. For example, the value of the counter in the updated intermediate data file is 10, and when the FPGA reads the value of the counter in the updated intermediate data file and determines that the value is greater than the value 9 before updating (i.e., the historical value), the FPGA may execute data synchronous scheduling with the application program, and write the target data and the data write address in the updated intermediate data file into the memory area.
In the embodiment of the present application, the operation of the application program is driven by C/c++, the intermediate data file is a file created during the initialization of the application program, and the data format of the intermediate data file may be shown in fig. 2, where 0x 000000000000 is a data writing address (i.e. an address of a memory area of the FPGA), 0x00000005 is target data to be written into the FPGA, and 101 is a value of the counter. Alternatively, when the application program is initialized, a thread of Vivado can be created and started, so that the FPGA runs independently according to its TCL script.
The code for initializing the application program is as follows:
In the embodiment of the application, the intermediate data file can be used as a bridge for data interaction between the application program and the FPGA, so that the FPGA can determine whether to execute data synchronous scheduling with the application program by reading the numerical value of the counter in the intermediate data file. The application program updates the corresponding data in the intermediate data file based on the target data and the data writing address, and increases the numerical value of the counter in the intermediate data file to obtain the updated intermediate data file, so that the data synchronous scheduling between the FPGA execution and the application program can be timely instructed through the numerical value of the updated counter (namely the numerical value of the counter in the updated intermediate data file) based on the updating mechanism of the intermediate data file, thereby enabling the JTAG interface to realize high-efficiency data synchronous scheduling without depending on a traditional synchronous signal or an external trigger, avoiding the problem of data transmission delay, ensuring the consistency of the data, and further improving the reliability of the data synchronous scheduling.
Optionally, the code of the application program for updating the intermediate data file is as follows:
Optionally, the intermediate data file can be expanded according to the requirement, that is, the design of the file format and the counter can be flexibly expanded, and the more complex data interaction and synchronous scheduling requirement can be adapted. For example, the writing of large amounts of data such as 0x00000005, 0x00000006, and 0x00000007 shown in fig. 2.
It should be noted that the intermediate data file in the application can use standard text format, thereby facilitating debugging, viewing and modification, and meanwhile, the file format of the intermediate data file is simple, thus being applicable to various operating system environments. By taking the intermediate data file as a bridge, high-efficiency data synchronous scheduling can be realized without depending on complex hardware signals or additional hardware interfaces, so that even if the problem of interface limitation exists, the data synchronous scheduling between the FPGA and the application program can be realized.
And step S103, based on the updated intermediate data file, performing data synchronous scheduling with the FPGA.
In the embodiment of the application, the application program can store the updated intermediate data file into a preset storage area to execute data synchronous scheduling with the FPGA, wherein the FPGA can be used for reading the data in the updated intermediate data file from the preset storage area and writing target data into the memory area of the FPGA based on a data writing address when the value of the counter is determined to be larger than a historical value, wherein the historical value is the value of the counter read from the intermediate data file last time by the FPGA. The FPGA is used for detecting whether the current time is a second target time, wherein the second target time is the time when the FPGA detects whether data synchronous scheduling with the application program is executed, if the current time is the second target time, the TCL script is operated to read data in an intermediate data file from a preset storage area of the application program, judge whether the numerical value of a counter in the intermediate data file is larger than a historical numerical value, and if the numerical value of the counter is larger than the historical numerical value, execute the data synchronous scheduling with the application program, and write target data and data in the intermediate data file into a memory area.
In an embodiment of the present application, the counter may be a handshake counter. By taking the counter as a synchronous handshake signal, the FPGA is guaranteed to perform data reading operation only when the numerical value of the counter is updated, and the application program is guaranteed to perform next updating operation of the intermediate data file after the FPGA synchronizes the data. After the FPGA performs a data reading operation and synchronizes the target data to be written into the FPGA and the data writing address to the memory area, the FPGA may be configured to generate feedback information indicating that the target data is synchronized to the FPGA and send the feedback information to the application program, and the application program may update the data synchronization state of the counter in the intermediate data file based on the feedback information and determine whether to perform a data updating operation based on the data synchronization state, so as to update the data in the intermediate data file again. The data synchronization state is used for representing whether the target data are synchronized to the FPGA or not, for example, when the data synchronization state of the counter is 0, the target data are not synchronized to the FPGA, and when the data synchronization state of the counter is 1, the target data are synchronized to the FPGA.
Specifically, referring to fig. 3, the flowchart of a process for performing a data update operation according to an embodiment of the present application includes the following steps:
in step S301, it is detected whether the current time is the first target time.
In step S301, the detection timing of the data synchronization state set in advance at the first target timing.
And step S302, if the current time is the first target time, judging whether the target data is synchronized to the FPGA or not based on the data synchronization state.
In step S303, if the target data is synchronized to the FPGA, the data updating operation is allowed to be executed, and the data updating operation is used for updating the data in the intermediate data file.
In step S304, if the target data is not synchronized to the FPGA, the data update operation is prohibited.
It should be noted that, whether to execute the data updating operation is determined by detecting whether the current moment is the detection moment of the data synchronization state, so that the next data updating operation is performed after the FPGA synchronizes the data, the problem of data loss caused by the next data updating operation performed before the FPGA synchronizes the data is avoided, and the reliability of the data synchronization scheduling is further improved.
According to the data synchronous scheduling method provided by the embodiment of the application, the operation of the application program is executed on the main thread, the operation of the FPGA is executed on the independent sub-thread, the data interaction is carried out between the application program and the FPGA through the JTAG interface sharing intermediate data file, the parallel execution and the mutual noninterference of the operation of the FPGA and the operation of the application program are realized, the direct synchronous dependence of the FPGA and the application program is avoided, the data synchronous scheduling between the FPGA execution and the application program is timely instructed through the numerical value of the updated counter (namely the numerical value of the counter in the updated intermediate data file) by an updating mechanism based on the intermediate data file, so that the JTAG interface can realize efficient data synchronous scheduling without depending on a traditional synchronizing signal or an external trigger, the data synchronous scheduling between the JTAG interface can be efficiently executed based on the updated intermediate data file, the target data and the data writing address to be synchronized to the FPGA, the problem of data transmission delay, data error or loss caused by the JTAG interface limitation is avoided, the problem that the data is difficult to realize the efficient synchronous scheduling due to the JTAG interface when the data interaction is carried out between the FPGA and the application program is realized, and the problem of difficult data synchronous scheduling due to the JTAG interface is solved.
In addition, the data synchronous scheduling method provided by the embodiment of the application enables the FPGA and the application program to maintain flexible and efficient operation among a plurality of threads and a plurality of tasks through an updating mechanism of the intermediate data file under the condition that the FPGA and the application program are executed asynchronously.
Method embodiment II
The embodiment of the application provides another embodiment of a data synchronous scheduling method, which is applied to an FPGA, wherein the operation of the FPGA is executed on a sub-thread created by an application program, the operation of the application program is executed on a main thread, and the FPGA is used for carrying out data interaction with the application program through a JTAG interface.
In the embodiment of the application, the operation of the FPGA is driven by the TCL script, the operation of the FPGA is executed on an independent sub-thread, the operation of the application program is executed on a main thread, and the data interaction between the FPGA and the application program is carried out through a JTAG interface, so that the parallel execution and mutual noninterference of the operation of the FPGA and the operation of the application program are realized.
Alternatively, the FPGA may perform hardware initialization by running TCL scripts before data interaction with the application. Specifically, the FPGA is connected to the Vivado hardware server by running the TCL script, matched hardware equipment is selected to establish hardware communication connection, and then the FPGA can refresh the equipment state of the hardware equipment to ensure the correct configuration of hardware. The hardware initialized TCL code is as follows:
# hardware initialization
set device xc7z045_1
open_hw
connect_hw_server
open_hw_target
current_hw_device[get_hw_devices Sdevice]
refresh_hw_device[lindex[get_hw_devices Sdevice]0]
set hw_axi_1[get_hw_axis hw_axi_1]
puts"Vivado Hardware Init Done\n"
It should be noted that, by means of hardware initialization, it is ensured that the hardware resources of the FPGA can be loaded and connected correctly, so as to prepare for subsequent data interaction.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order different than that herein.
Referring to fig. 4, the flowchart of another data synchronization scheduling method according to an embodiment of the present application includes the following steps:
in step S401, it is detected whether the current time is the second target time.
In step S401, the second target time is a time when the FPGA that is set in advance detects whether to execute data synchronization scheduling with the application program.
In order to solve the technical problem that effective data synchronization scheduling is difficult to realize due to the limitation of JTAG interfaces when data interaction is performed between the existing FPGA and the application program through the JTAG interfaces, the reliability of the data synchronization scheduling is improved, in the embodiment of the application, the FPGA can determine whether to read the data in the intermediate data file from the preset storage area of the application program by detecting whether the current time is the time (i.e., the second target time) of performing data synchronization scheduling with the application program, so that the JTAG interface can implement efficient data synchronization scheduling without relying on a conventional synchronization signal or an external trigger.
In step S402, if the current time is the second target time, the TCL script is run to read the data in the intermediate data file from the preset storage area of the application program, where the data includes the value of the counter.
In step S402, the data further includes target data to be written into the FPGA and a data writing address, and the value of the counter is used to indicate whether the FPGA performs data synchronous scheduling with the application program.
In the embodiment of the application, when the current time is the second target time, the FPGA runs the TCL script to read the data in the intermediate data file from the preset storage area of the application program, and provides data preparation for subsequent data synchronous scheduling. And when the current time is the second target time, the FPGA prohibits reading the data in the intermediate data file from the preset storage area of the application program until the current time is the second target time.
In the embodiment of the present application, the intermediate data file is a file created during application program initialization, and the data format thereof may be shown in fig. 2, where 0x00000000 is a data writing address (i.e. an address of a memory area of the FPGA), 0x00000005 is target data to be written into the FPGA, and 101 is a value of a counter.
It should be noted that, the intermediate data file may be used as a bridge for data interaction between the application program and the FPGA, and by making the FPGA determine whether to execute data synchronous scheduling with the application program by reading the value of the counter in the intermediate data file, efficient data synchronous scheduling can be implemented without depending on a complex hardware signal or an additional hardware interface, so that even if there is a problem of limited interface, data synchronous scheduling between the FPGA and the application program may be implemented.
In step S403, if the value of the counter is greater than the historical value, the data synchronization scheduling with the application program is executed.
In step S403, the historical value is the value of the counter that the FPGA last read from the intermediate data file.
In the embodiment of the application, the FPGA can determine whether to execute the data synchronous scheduling with the application program by judging whether the numerical value of the counter is larger than the historical numerical value, and when the numerical value of the counter is larger than the historical numerical value, the FPGA can determine that the numerical value of the counter is updated, the data synchronous scheduling with the application program is executed, and when the numerical value of the counter is equal to the historical numerical value, the FPGA can determine that the numerical value of the counter is not updated, and the data synchronous scheduling with the application program is forbidden until the numerical value of the counter is updated.
In the embodiment of the application, the FPGA can call the data writing function based on the target data to be written into the FPGA and the data writing address, and the target data is written into the memory area matched with the data writing address. The data writing function may be WriteReg functions, through which the FPGA may perform a writing operation of data, and the operation may interact with FPGA hardware through the Vivado platform, so as to ensure that a state in the hardware is updated.
Optionally, the FPGA may further perform a data read operation based on a data read function (e.g., readReg x) to read the data write address from the memory region.
Alternatively, the FPGA may read data from the intermediate data file and the TCL code performing the data sync schedule may be as follows:
It should be noted that, the intermediate data file is shared between the FPGA and the application program through the JTAG interface for data interaction, so that the JTAG interface can realize efficient data synchronous scheduling without depending on a traditional synchronizing signal or an external trigger, thereby avoiding the problems of data transmission delay, data error or loss caused by the limitation of the JTAG interface, solving the technical problem that the effective data synchronous scheduling is difficult to realize due to the limitation of the JTAG interface when the data interaction is performed between the existing FPGA and the application program through the JTAG interface, and improving the reliability of the data synchronous scheduling.
In an embodiment of the present application, the counter may be a handshake counter. By taking the counter as a synchronous handshake signal, the FPGA is guaranteed to perform data reading operation only when the numerical value of the counter is updated, and the application program is guaranteed to perform next updating operation of the intermediate data file after the FPGA synchronizes the data.
In order to further improve reliability of data synchronization scheduling, in the embodiment of the application, after target data is written into a memory area matched with a data writing address, the FPGA can generate feedback information based on the target data to be written into the FPGA and the data writing address, so as to update a data synchronization state of a counter in an intermediate data file, thereby providing preparation for next data synchronization scheduling. Specifically, referring to fig. 5, the flowchart of a feedback information generation process provided by an embodiment of the present application includes the following steps:
In step S501, feedback information is generated based on target data to be written into the FPGA and the data writing address.
In step S501, feedback information is used to characterize that the target data has been synchronized to the FPGA.
Step S502, the feedback information is sent to the application program.
In step S502, the application program is configured to update a data synchronization state of a counter in the intermediate data file based on the feedback information, and determine whether to perform a data update operation for updating data in the intermediate data file based on the data synchronization state. The data synchronization state is used for representing whether the target data are synchronized to the FPGA or not, for example, when the data synchronization state of the counter is 0, the target data are not synchronized to the FPGA, and when the data synchronization state of the counter is 1, the target data are synchronized to the FPGA.
It should be noted that, by generating feedback information based on the target data to be written into the FPGA and the data writing address, and sending the feedback information to the application program, the application program updates the data synchronization state of the counter in the intermediate data file based on the feedback information, so that the application program is ensured to perform the next data update operation after the FPGA synchronizes the data, the problem of data loss caused by performing the next data update operation before the FPGA synchronizes the data is avoided, and the reliability of the data synchronization scheduling is further improved.
According to the data synchronous scheduling method provided by the embodiment of the application, the operation of the FPGA is executed on the independent sub-thread, the operation of the application program is executed on the main thread, the data interaction is carried out between the application program and the FPGA through the JTAG interface sharing intermediate data file, the parallel execution and the mutual noninterference of the operation of the FPGA and the operation of the application program are realized, the direct synchronous dependence of the FPGA and the application program is avoided, the data synchronous scheduling between the FPGA execution and the application program is timely instructed through the numerical value of the updated counter (namely the numerical value of the counter in the updated intermediate data file) based on the sharing mechanism of the intermediate data file, so that the JTAG interface can realize efficient data synchronous scheduling without depending on a traditional synchronous signal or an external trigger, the data synchronous scheduling between the JTAG interface can be efficiently executed based on the updated intermediate data file, the target data and the data writing address to be synchronized to the FPGA, the problem of data transmission delay, data error or loss caused by the JTAG interface limitation is avoided, the problem that the data is difficult to realize the efficient synchronous scheduling due to the JTAG interface when the data interaction is carried out between the FPGA and the application program is realized, and the problem of difficult data synchronous scheduling due to the JTAG interface limitation is solved.
In addition, the data synchronous scheduling method provided by the embodiment of the application enables the FPGA and the application program to maintain flexible and efficient operation among a plurality of threads and a plurality of tasks through an updating mechanism of the intermediate data file under the condition that the FPGA and the application program are executed asynchronously.
System embodiment
The embodiment of the application provides a data synchronous scheduling system, and particularly relates to fig. 6, which is a schematic diagram of the data synchronous scheduling system provided by the embodiment of the application, wherein the system comprises an application program 51 and an FPGA52, the operation of the application program 51 is executed on a main thread, the operation of the FPGA52 is executed on a sub-thread created by the application program 51, and data interaction is performed between the FPGA52 and the application program 51 through a JTAG interface.
The application program 51 is configured to obtain target data and a data writing address to be written into the FPGA, update corresponding data in an intermediate data file based on the target data and the data writing address, and increment a numerical value of a counter in the intermediate data file to obtain an updated intermediate data file, where the numerical value of the counter in the updated intermediate data file is used to instruct the FPGA to execute data synchronous scheduling with the application program, and the application program 51 is further configured to store the updated intermediate data file in a preset storage area.
In the embodiment of the present application, the application program 51 is further configured to store the updated intermediate data file in a preset storage area to perform data synchronization scheduling with the FPGA, where the FPGA is configured to read data in the updated intermediate data file from the preset storage area, and write, when determining that the value of the counter is greater than the historical value, the target data into the memory area of the FPGA based on the data write address, where the historical value is the value of the counter that the FPGA last read from the intermediate data file.
In an alternative implementation manner, the intermediate data file further includes a data synchronization state of the counter, and the application program 51 is further configured to detect whether the current time is a first target time;
If the current time is the first target time, judging whether the target data is synchronized to the FPGA or not based on the data synchronization state;
if the target data is synchronized to the FPGA, allowing to execute data updating operation, wherein the data updating operation is used for updating the data in the intermediate data file;
And if the target data is not synchronized to the FPGA, prohibiting the execution of the data updating operation.
The FPGA52 is configured to detect whether the current time is a second target time, and if the current time is the second target time, execute the TCL script to read data in the intermediate data file from the preset storage area, where the second target time is a time when the FPGA detects whether to execute data synchronous scheduling with the application program, the data includes target data to be written into the FPGA, a data write address, and a value of a counter, the value of the counter is used to indicate whether the FPGA executes data synchronous scheduling with the application program, and if the value of the counter is determined to be greater than a historical value, execute data synchronous scheduling with the application program, and the historical value is a value of the counter that the FPGA has read from the intermediate data file last time.
In an alternative implementation, the FPGA52 is further configured to invoke a data write function to write target data into a memory area matching the data write address based on the target data and the data write address to be written into the FPGA.
In an alternative implementation, FPGA52 is also configured to:
generating feedback information based on target data to be written into the FPGA and a data writing address, wherein the feedback information is used for representing that the target data is synchronized to the FPGA;
The application program is used for updating the data synchronization state in the intermediate data file based on the feedback information, determining whether to execute a data updating operation based on the data synchronization state, wherein the data updating operation is used for updating the data in the intermediate data file.
According to the data synchronous scheduling system provided by the embodiment of the application, the operation of the FPGA is executed on the independent sub-thread, the operation of the application program is executed on the main thread, the data interaction is carried out between the application program and the FPGA through the JTAG interface sharing intermediate data file, the parallel execution and the mutual noninterference of the operation of the FPGA and the operation of the application program are realized, the direct synchronous dependence of the FPGA and the application program is avoided, the data synchronous scheduling between the FPGA execution and the application program is timely instructed through the numerical value of the updated counter (namely the numerical value of the counter in the updated intermediate data file) by an updating mechanism based on the intermediate data file, so that the JTAG interface can realize efficient data synchronous scheduling without depending on a traditional synchronizing signal or an external trigger, the data synchronous scheduling between the JTAG interface can be efficiently executed based on the updated intermediate data file, the target data and the data writing address to be synchronized to the FPGA, the problem of data transmission delay, data error or loss caused by the JTAG interface limitation is avoided, the problem that the data is difficult to realize the efficient synchronous scheduling due to the JTAG interface when the data interaction is carried out between the FPGA and the application program is solved, and the problem of difficult data synchronous scheduling due to the JTAG interface is difficult to realize.
In addition, the data synchronous scheduling system provided by the embodiment of the application enables the FPGA and the application program to maintain flexible and efficient operation among a plurality of threads and a plurality of tasks through an updating mechanism of the intermediate data file under the condition that the FPGA and the application program are executed asynchronously.
Storage medium embodiment
The embodiment of the application provides a computer readable storage medium, and a program is stored on the storage medium, wherein the program realizes part or all of the steps in the data synchronous scheduling method introduced by the embodiment of the method when being executed by a processor. The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Processor embodiments
The embodiment of the application provides a processor, which is used for running a program, wherein part or all of the steps in the data synchronous scheduling method described in the embodiment of the method are executed when the program runs.
It is noted that relational terms such as first and second, and the like in this description are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, with reference to the description of method embodiments in part. The system embodiments described above are merely illustrative, wherein elements illustrated as separate elements may or may not be physically separate, and elements illustrated as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing is only one specific embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be included in the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (10)
1. A method of synchronous scheduling of data, characterized by being applied to an application, operations of which are performed on a main thread, the method comprising:
the method comprises the steps of obtaining target data and a data writing address to be written into an FPGA, wherein the operation of the FPGA is executed on a sub-thread created by an application program, and the FPGA and the application program interact data through a JTAG interface;
Updating corresponding data in an intermediate data file based on the target data and the data writing address, and increasing the numerical value of a counter in the intermediate data file to obtain an updated intermediate data file;
and executing data synchronous scheduling with the FPGA based on the updated intermediate data file.
2. The method of claim 1, wherein the performing data synchronization scheduling with the FPGA based on the updated intermediate data file comprises:
The FPGA is used for reading data in the updated intermediate data file from the preset storage area, writing the target data into a memory area of the FPGA based on the data writing address when the value of the counter is determined to be larger than a historical value, wherein the historical value is the value of the counter which is read from the intermediate data file by the FPGA last time.
3. The method of claim 1, further comprising a data synchronization state of a counter in the intermediate data file, the data synchronization state being used to characterize whether the target data has been synchronized to the FPGA, the method further comprising:
detecting whether the current moment is a first target moment or not, wherein the first target moment is the detection moment of the data synchronization state;
if the current time is the first target time, judging whether the target data is synchronized to the FPGA or not based on the data synchronization state;
If the target data is synchronized to the FPGA, allowing a data updating operation to be executed, wherein the data updating operation is used for updating the data in the intermediate data file;
And if the target data is not synchronized to the FPGA, prohibiting the execution of the data updating operation.
4. The data synchronous scheduling method is characterized by being applied to an FPGA, wherein the operation of the FPGA is executed on a sub-thread created by an application program, the operation of the application program is executed on a main thread, and the FPGA is used for carrying out data interaction with the application program through a JTAG interface, and the method comprises the following steps:
Detecting whether the current time is a second target time or not, wherein the second target time is the time when the FPGA detects whether to execute data synchronous scheduling with the application program or not;
If the current time is the second target time, running a TCL script to read data in an intermediate data file from a preset storage area of the application program, wherein the data comprises target data to be written into an FPGA, a data writing address and a numerical value of a counter, and the numerical value of the counter is used for indicating whether the FPGA executes data synchronous scheduling with the application program or not;
And if the numerical value of the counter is larger than the historical numerical value, executing data synchronous scheduling with the application program, wherein the historical numerical value is the numerical value of the counter read from the intermediate data file by the FPGA last time.
5. The method of claim 4, wherein the performing of the data synchronization schedule with the application comprises:
And calling a data writing function based on the target data and the data writing address, and writing the target data into a memory area matched with the data writing address.
6. The method of claim 5, wherein after writing the target data to the memory region that matches the data write address, the method further comprises:
Generating feedback information based on the target data to be written into the FPGA and the data writing address, wherein the feedback information is used for representing that the target data is synchronized to the FPGA;
The application program is used for updating the data synchronization state of the counter in the intermediate data file based on the feedback information, determining whether to execute a data updating operation or not based on the data synchronization state, wherein the data updating operation is used for updating the data in the intermediate data file.
7. The data synchronous scheduling system is characterized by comprising an application program and an FPGA, wherein the operation of the application program is executed on a main thread, the operation of the FPGA is executed on a sub-thread created by the application program, and the data interaction is carried out between the FPGA and the application program through a JTAG interface;
The application program is used for acquiring target data and a data writing address to be written into the FPGA, updating corresponding data in an intermediate data file based on the target data and the data writing address, and increasing the numerical value of a counter in the intermediate data file to obtain an updated intermediate data file;
The FPGA is used for detecting whether the current time is a second target time, if the current time is the second target time, a TCL script is operated to read data in the intermediate data file from the preset storage area, the second target time is the time when the FPGA detects whether to execute data synchronous scheduling with the application program, the data comprises target data to be written into the FPGA, a data writing address and a numerical value of a counter, the numerical value of the counter is used for indicating whether the FPGA executes data synchronous scheduling with the application program, and if the numerical value of the counter is determined to be larger than a historical numerical value, the FPGA is used for executing data synchronous scheduling with the application program, and the historical numerical value is the numerical value of the counter read from the intermediate data file by the FPGA last time.
8. The system of claim 7, wherein the FPGA is further configured to invoke a data write function based on the target data and the data write address to write the target data into a memory region that matches the data write address.
9. A computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, which, when being executed by a processor, implements the data synchronization scheduling method according to any one of claims 1-6.
10. A processor configured to run a computer program, the computer program when run performing the data synchronous scheduling method of any one of claims 1-6.
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