CN120344867A - Multi-stage logic built-in self-test observation scanning technology - Google Patents

Abstract

A circuit includes a scan chain including scan cells and one or more observation scan chains. The scan chain includes a scan cell. The one or more observation scan chains include an observation scan unit. Testing the circuit includes a scan capture phase and an observation scan phase. During the scan acquisition phase, the scanning unit and the observation scanning unit alternately operate in a shift mode and an acquisition mode. During the observation scan phase, the scan cell operates in a shift mode and the observation scan cell operates in a shift observation mode.

Description

Multi-stage logic built-in self-test observation scanning technique

Technical Field

The disclosed technology relates to the field of circuit testing. Various implementations of the disclosed technology may be particularly useful for improving test coverage and reducing test application time.

Background

Since the last fifty years ago, scanning has become one of the most influential, most industry-proven structured for test (DFT) techniques. It allows to directly access the memory elements of the circuit under test (circuit under test, CUT) by reusing them to form a shift register in test mode. An automatic test equipment (automatic test equipment, ATE) or other test vector source provides serial input to the scan chain, and then the same ATE or test response compressor captures test responses exiting the scan chain through the serial output of the scan chain. Since all scan cells are typically controlled by a single scan enable signal, the scan chains remain functionally indistinguishable, that is, they are both moving data in and out, or are both capturing test responses. Thus, the high controllability and observability of the internal nodes makes it possible to automatically generate high quality test vectors and debug the discovered defects. Furthermore, the simple structure of the scan chain enables it to be automatically stitched and inserted with the support of Electronic Design Automation (EDA) tools.

With the firm establishment of scan-based test paradigms, several more advanced DFT techniques have also been proposed. Notably, many logic built-in self-test (LBIST) schemes employ scanning as their operational baselines to achieve high quality testing with a limited amount of test data. Typically, these solutions include a pseudo-random test vector generator (PRP) feeding a scan chain (FEED SCAN CHAIN) and a multiple-input signature register (MISR) compressing the shifted-out response. The same rules apply to test data compression, in which case PRPG is typically replaced by an on-chip test data decompressor.

The disadvantages of scan-based testing are mainly related to the fact that all scan chains are filled with test vectors before the test vectors are applied. Thus, most of the test time is spent on shifting the test data. Consider a design with a scan chain 100 cells long. Applying 10,000 dual capture test vectors would require 1,000,000 shift cycles and 20,000 capture cycles. Thus, the period actually used for testing (applying test stimulus and capturing test response) is as low as 2%. The results are worse in terms of test time, since the scan shift frequency is typically much lower than the frequency of the capture (functional) mode. In logic BIST, test time efficiency may be lower. Typical scan shift frequencies are on the order of tens of megahertz, while functional clock frequencies can be as high as thousands of megahertz. Thus, 99.99% of the test time is available for scan shifting.

Electronic products in vehicles are increasing, which enables advanced security functions, new information and entertainment services, and higher energy efficiency. Integrated circuits for the automotive electronics market must meet stringent quality and reliability requirements, which are driven primarily by safety standards such as ISO26262 and Automotive Safety Integrity Level (ASIL) targets. ISO26262 compliance requires more advanced test solutions to be adopted. In particular, to achieve the necessary reliability level of integrated circuits, LBIST functions should be capable of handling challenges presented by automotive parts and supporting multiple field test requirements, including the ability to run periodic tests during functional operation. Due to the severe restrictions on the on-time period or the off-time period, these periodic tests must be completed in a short time. Therefore, it would be advantageous to develop test techniques that can shorten test application times without adversely affecting fault coverage. One of the main potential factors leading to low coverage of faults or high vector counts is the unknown state (X) captured by the scan cells. For safety critical devices that must be self-tested during system operation, it is desirable to prevent all X bits from reaching the test response compressor.

Disclosure of Invention

Aspects of the disclosed technology relate to multi-stage observational scanning techniques. In one aspect, there is a circuit comprising a scan chain including scan cells configured to operate in a shift mode or a capture mode based on a scan enable signal, a parallel output of the scan cells coupled to functional circuitry of the circuit, one or more observation scan chains including an observation scan cell configured to operate in the shift mode, the capture mode, or the shift observation mode based on the scan enable signal and the observation scan enable signal, an output of the observation scan cell not coupled to the functional circuitry of the circuit, and a test controller including circuitry configured to generate the scan enable signal and the observation scan enable signal for testing the circuit, the test including a scan capture phase during which the scan cells and the observation scan cells alternately operate in the shift mode and the capture mode, and an observation scan phase during which the scan cells operate in the shift mode and the observation scan cell operates in the shift observation mode.

The number of test vectors for the observation scan capture phase may be less than or equal to the number of test vectors for the scan phase.

The circuit may further include a pseudo-random vector generator configured to generate test vectors to be shifted into the scan chain and the one or more observation scan chains, and a test compressor configured to compress test responses shifted out of the scan chain and the one or more observation scan chains.

Each observation scan cell may include a state element, and a selection and combination circuit including a combination circuit configured to combine a signal from a serial input port of each observation scan cell with a signal from a parallel input port of each observation scan cell to generate an observation scan signal, and a selection circuit configured to select an input signal of the state element from among the signal from the serial input port, the signal from the parallel input port, and the observation scan signal based on the scan enable signal and the observation scan enable signal. The combining circuit may comprise an XOR gate. The state element may be a trigger. The selection circuit includes a 2-to-1 multiplexer AND two AND gates (AND gates).

The selection and combination circuit may further comprise a further combination circuit configured to combine the signal from the parallel input port with the output signal of the state element to generate a capture-accumulation signal, wherein the selection circuit is configured to select the input signal of the state element based on the scan enable signal and the observation scan enable signal from the serial input port, the signal from the parallel input port, the observation scan signal, and the capture-accumulation signal.

In another aspect, there are one or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method comprising creating the above-described circuit in a circuit design.

In yet another aspect, a method includes testing a circuit, wherein the circuit includes a scan chain and one or more observation scan chains, the scan chain including scan cells, the one or more observation scan chains including observation scan cells, and wherein the testing includes a scan capture phase during which the scan cells and the observation scan cells alternately operate in a shift mode and a capture mode, and an observation scan phase during which the scan cells operate in a shift mode and the observation scan cells operate in a shift observation mode.

The accompanying independent and dependent claims set forth certain inventive aspects. Features from the dependent claims may be combined with features from the independent claims and with features from other dependent claims as appropriate and not merely as explicitly set out in the claims.

Certain objects and advantages of various inventive aspects have been described herein above. It should be understood, of course, that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed techniques may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

Drawings

FIG. 1 illustrates an example test architecture that can be implemented in accordance with various embodiments of the disclosed technology.

Fig. 2 shows an example of a conventional scanning unit.

FIG. 3 illustrates an example of an observation scan unit that can be implemented in accordance with various embodiments of the disclosed technology.

Fig. 4 shows a table summarizing the four modes of operation in which the observation scanning unit in fig. 3 can operate and the associated settings for the two control signals.

Fig. 5 shows how X bits captured by a normal scanning unit damage an observation scanning unit using the observation scanning system.

FIG. 6 illustrates a multi-stage observation scan scheme that can be employed to reduce the effects of X bits in accordance with various embodiments of the disclosed technology.

FIG. 7A shows a table showing characteristics of four industrial designs and X-state injection and resulting damage to the observation scan chain under a single-phase observation scan scheme.

FIG. 7B illustrates a table showing test vector counts required to achieve 90% test coverage under different test schemes and/or conditions for the four industrial designs shown in FIG. 7A.

FIG. 8 illustrates an example block diagram of an observation scan unit, which can be implemented in accordance with various embodiments of the disclosed technology.

FIG. 9 illustrates an example block diagram of another observation scan unit, which can be implemented in accordance with various embodiments of the disclosed technology.

FIG. 10 illustrates a programmable computer system in which various embodiments of the disclosed technology may be employed.

Detailed Description

Overall consideration

Aspects of the disclosed technology relate to multi-stage observational scanning techniques. In the following description, for purposes of explanation, numerous details are set forth. However, it will be appreciated by one of ordinary skill in the art that the disclosed techniques may be practiced without such specific details. In other instances, well-known features have not been described in detail so as not to obscure the techniques of this disclosure.

Some of the techniques described herein may be implemented by software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of the two. For example, certain of the disclosed techniques may be implemented as part of an Electronic Design Automation (EDA) tool. The methods may be performed on a single computer or on networked computers.

Although the operations of the disclosed methods are described in a particular order for convenience of presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular order is required by the particular language set forth below. For example, operations described in sequence may be rearranged or performed concurrently in some instances. Moreover, for the sake of brevity, the disclosed flow diagrams and block diagrams generally do not show the various ways in which a particular method may be used in connection with other methods.

Detailed description of the methods or apparatus the terms "combine," "generate," and "operate" are sometimes used to describe the functions/structures of the disclosed methods or apparatus. Such terms are high-level abstractions. The actual operation or function/structure corresponding to these terms will vary depending on the particular embodiment and will be readily recognized by those of ordinary skill in the art.

As used in this disclosure, the singular forms "a", "an" and "the" include plural forms unless the context clearly dictates otherwise. Furthermore, the term "comprising" means "including. Also, unless the context indicates otherwise, the term "couple" means an electrical or electromagnetic connection or link, including a direct connection or direct link, as well as an indirect connection or indirect link through one or more intermediate elements that do not affect the intended operation of the circuit.

Furthermore, the term "design" as used herein is intended to encompass data describing the entire integrated circuit device. However, the term is also intended to encompass smaller data sets describing one or more components of the overall device (e.g., a portion of an integrated circuit device).

Test design, scan-based test, test compaction, logic BIST, and test point

The reduction in feature size increases the probability that an integrated circuit manufacturing defect will cause a chip failure. Small defects may cause the transistor or interconnect to fail. Even a single transistor or wire failure can lead to a malfunction of the entire chip. However, manufacturing defects are unavoidable whether the manufacturing process is in the prototype stage or in the mass production stage. Therefore, it is necessary to test the chip during the manufacturing process. Diagnosing faulty chips is also desirable to improve and maintain manufacturing yields.

Testing typically involves applying a set of test stimuli (test vectors) to the circuit under test, and then analyzing the response produced by the circuit under test. Functional tests attempt to verify whether the circuit under test is operating in accordance with its functional specifications, while structural tests attempt to determine whether the circuit under test has been properly assembled from some low-level building blocks as specified in the structural netlist, and whether these low-level building blocks and their wiring connections have been manufactured without defects. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist, and structural testing has confirmed the correct assembly of structural circuit elements, then the circuit should function properly. Structural testing is widely used, at least in part, because it enables test (test vector) generation to be focused on a relatively simple circuit element with a limited number of tests, without having to deal with the wide variety of functional states and state transitions that grow exponentially.

To more easily develop and apply test vectors, certain testability features have been added to circuit designs, which are referred to as test designs or testability Designs (DFTs). Scan testing is the most common DFT method. In a basic scan test scheme, all or most of the internal sequential state elements (latches, flip-flops, etc.) in the circuit design can be controlled and observed through the serial interface. These functional status elements are typically replaced with dual purpose status elements called scan cells. The scan cells are connected together to form a scan chain-a serial shift register for shifting in test vectors and shifting out test responses. The scanning unit may be operated for its original functional purpose (functional/mission mode) or may be operated as a unit in a scan chain (scan mode). One widely used type of scan cell includes an edge-triggered flip-flop with a bidirectional multiplexer for data input. The bi-directional multiplexer is typically controlled by a single control signal called scan _ enable, which selects the input signal for the scan cell from either the scan signal input port or the system signal input port. The scan signal input port is typically connected to the output of another scan cell, while the system signal input port is connected to the functional logic. The scanning unit can be used as a control point or an observation point. The control points may be used to set specific logic values at certain locations of the circuit under test, thereby stimulating a fault and propagating error values to the observation points. Scan testing allows the test equipment to access deep embedded gates through the main input/output and/or some physical test points and may eliminate the need for complex state transition sequences when attempting to control or observe what happens to some internal circuit elements.

Test vectors for scan testing are typically generated by an automatic test vector generation (ATPG) process. ATPG is typically focused on a set of faults that are derived from a gate level fault model. Defects are imperfections in the device that occur during the manufacturing process. The failure model is a description of how defects change design behavior. In other words, a defect is a flaw or physical defect that may lead to a failure. For a given target fault, ATPG includes two phases, fault activation and fault propagation. The fault activation establishes a signal value at the fault site that is opposite to the signal value generated by the fault. Fault propagation propagates fault effects forward by sensitizing the path from the fault site to the scan cell or primary output. If the scan cell or primary output captured test response value is different than the expected value, it indicates that the test vector detected a fault at the site. The goal of ATPG is to find a test vector that, when applied to a circuit, enables a tester to distinguish between correct circuit behavior and faulty circuit behavior caused by one or more specific faults. The effectiveness of ATPG is measured by the fault coverage and the number of vectors generated (test vector counts) implemented for the fault model, which should be proportional to the test application time. Here, the failure coverage is defined as a ratio of the number of detected failures to the total number of failures.

The most common fault model in practice is the single stationary fault model. In this model, a signal line in the circuit is assumed to be fixed at a fixed logic value, regardless of the input of the circuit. The fixed fault model is a logical fault model in that no delay information is associated with the fault definition. Delay faults cause errors in the functioning of the circuit based on the timing of the circuit. They are caused by the finite rise and fall time periods of the signals in the gates and the propagation delay of the interconnections between the gates. Transition fault (Transition fault) is adopted for its simplicity in modeling point defects that affect delay at the input or output of the gate. In scan-based testing, a transition fault is associated with an additional delay that is sufficient to cause the delay of any path through the fault site to exceed the clock period.

During circuit design and manufacturing, manufacturing tests screen out chips (dies) that contain defects. However, the test itself does not identify the cause of an unacceptably low yield or fluctuating yield that is observable. Physical Failure Analysis (PFA) may inspect the failed chip to locate one or more locations of defects and to find root causes. The process typically involves etching away some layers and then imaging the silicon surface by scanning electron microscopy or a focused ion beam system. This PFA procedure is laborious and time-consuming. To facilitate the PFA process, diagnostic methods are typically employed to narrow down the possible locations of the one or more defects based on analysis of fault logs (fault files, failure files). Fault logs typically contain the time (e.g., test period), place (e.g., at what tester channel) and manner (e.g., at what logic value) of test failures, and which test vectors will produce expected test responses. Layout information of the circuit design may also be used to further reduce the number of suspected points of defects.

Test applications in chip manufacturing testing are typically performed by Automated Test Equipment (ATE), a type of tester. Scan-based testing consumes a significant amount of storage space and test time for ATE. The amount of data increases with the number of logic gates on the chip, as does the number of scan cells. However, practical considerations and ATE specifications often limit the number of pins available for scan input/output and the maximum scan frequency. It is highly desirable to reduce the amount of test data that needs to be loaded into the ATE and ultimately into the circuit under test. Fortunately, the test vectors are compressible, mainly because typically only 1% -5% of the test vector bits are designated bits (bits of interest), while the rest are non-designated bits (irrelevant bits). The unspecified bit can take any value without affecting the fault coverage. Test compression may also take advantage of the fact that test cubes tend to be highly correlated. The test cube is a deterministic test vector in which irrelevant bits are not filled with ATPG. There is a correlation because faults in the circuit are structurally related.

Various test compression techniques have been developed. Typically, additional on-chip hardware is inserted before and after the scan chain. The hardware added before the scan chain (the decompressor) is configured to decompress test stimulus from the ATE, while the hardware added after the scan chain (the compressor) is configured to compress test response captured by the scan chain. The decompressor expands the data from n tester channels to fill more than n scan chains. The increased number of scan chains shortens each scan chain, thereby reducing the number of clock cycles required to move into each test vector. Thus, for a given test data bandwidth, test compression not only reduces the amount of data stored on the tester, but also shortens test time.

Embedded Deterministic Testing (EDT) is one example of a test compression technique. EDT-based compression techniques consist of two complementary parts, hardware embedded on-chip and deterministic ATPG software that uses the embedded hardware to generate compressed vectors. EDT hardware has a continuous flow decompressor. EDT compression of the test cube is performed by treating the external test data as boolean variables. The scan cells are conceptually filled with symbolic expressions that are linear functions of the input variables of the injection decompressor. Where the decompressor includes a loop generator and associated phase shifter, a set of linear equations corresponding to the scan cell whose value is specified may be used. The compressed vector may be determined by solving a system of equations. If the compressed vector thus determined is scanned in by the decompressor, the bit designated by the ATPG will be correspondingly generated. The unspecified bits will be set to pseudo-random values based on the decompressor architecture. For more details regarding EDT-based compression and decompression see ：J.Rajski,J.Tyszer,M.Kassab,and N.Mukherjee,"Embedded deterministic test,"IEEE Trans.CAD,vol.23,pp.776-792,May 2004, and U.S. patent 6,327,687;6,353,842;6,539,409;6,543,020;6,557,129;6,684,358;6,708,192;6,829,740;6,874,109;7,093,175;7,111,209;7,260,591;7,263,641;7,478,296;7,493,540;7,500,163;7,506,232;7,509,546;7,523,372;7,653,851,, the entire contents of which are incorporated herein by reference.

Logic built-in self-test (Logic BIST) is a DFT technique that allows circuits to self-test using embedded test Logic without the need for an external tester. Classical logic BIST applications include detection of early failure defects (infant mortality defect) during burn-in testing, enabling the use of low cost and/or low speed testers that provide only power and clock signals, and self-testing within systems in the aerospace/defense, automotive, telecommunications and healthcare industries to improve system reliability. A typical logic BIST system comprises a test vector generator for automatically generating test vectors, a test response analyzer (compressor) for compressing test responses into signatures, and a logic BIST controller for coordinating BIST operations and for providing pass/fail indications. A pseudo-random vector generator (PRPG), a commonly used test vector generator, may be constructed from a Linear Feedback Shift Register (LFSR) or a cellular automaton. To improve fault coverage, a weighted LFSR may be employed. Another approach is to combine the random test vectors with deterministic vectors in some way, as BIST logic can be used to process compressed test vectors that are deterministically generated and stored on-chip.

All of the above-described processes, including design insertion for testing, test vector generation, test compression, and test point insertion, are typically accomplished by various electronic design automation tools, such as the Tessent series of software tools from siemens industrial software, plauno, tx.

Observation scanning architecture

FIG. 1 illustrates an example test architecture 100, which test architecture 100 may be implemented in accordance with various embodiments of the disclosed technology. The test architecture 100 includes a scan chain 110, one or more observation scan chains 150, and a test controller 160. Scan chain 110 may be comprised of conventional scan cells. The conventional scan unit may be configured to operate in a shift mode or a capture mode based on a scan enable signal generated by the test controller 160. Fig. 2 shows an example of a conventional scanning unit 200. The scan cell 200 includes a state element 210 and a bi-directional multiplexer 220. The state element 210 may be implemented using edge triggered flip-flops. The bi-directional multiplexer 220 selects the signal from the serial input port 230 of the scan cell 200 or the parallel input port 240 of the scan cell 200 as the data input signal for the state element 210. The selection is based on a scan enable signal supplied from the scan enable port 250 of the scan cell 200. Serial input port 230 may be coupled to an output of another scan cell (e.g., one of scan chains 110 in fig. 1) that is in the same scan chain as scan cell 200, while parallel input port 240 may be coupled to functional circuit 270.

The scan cell 200 operates in a shift mode when the scan enable signal 250 selects the serial input port 230 as the data input signal for the state element 210 and the scan cell 200 operates in a capture mode when the scan enable signal 250 selects the parallel input port 240 as the data input signal for the state element 210. Scan cell 200 is tapped to two outputs, serial output 260, which may be coupled to a serial input port of the next scan cell in the scan chain, and parallel output 280, which may be coupled to functional circuit 270. In this arrangement, the data bits stored in the state element 110 are continuously applied to the functional circuit 270 even in the shift mode.

Referring back to fig. 1, one or more observation scan chains 150 may be comprised of observation scan units. The observation scan unit may be configured to operate in a shift mode, a capture mode, or a shift observation mode based on a scan enable signal used by the scan chain 120 and another control signal referred to as an observation scan enable signal. The observation scan enable signal may also be generated by the test controller 160. The test controller 160 may use a counter to facilitate generating the observation scan enable signal based on the scan enable signal. Fig. 3 illustrates one example of an observation scan unit 300, which observation scan unit 300 can be implemented in accordance with various embodiments of the disclosed technology. The observation scan unit 300 includes a state element 310 and a selection and combination circuit 320. The state element 310 may be implemented using edge triggered flip-flops. The selection and combination circuit 320 includes a combination circuit 321 and a selection circuit 325. The combining circuit 321 is configured to combine the signal "s" from the serial input port 330 of the observation scan unit 300 with the signal "d" from the parallel input port 340 of the observation scan unit 300 to generate a signal "s+d". Serial input port 330 may be coupled to an output of another scan cell (e.g., one of one or more observation scan chains 150 in fig. 1) that is in the same scan chain as scan cell 300, while parallel input port 340 may be coupled to functional circuit 390.

The select and combine circuit 320 may further include another combining circuit 323 configured to combine the signal "d" from the parallel input port 340 with the signal "Q" from the output 370 of the state element 310 to generate the signal "d+q". If the select and combine circuit 320 does not have a combining circuit 323, the select circuit 325 is configured to select the input signal of the state element 310 from the signal "s", the signal "d", and the signal "s+d". If combined circuit 323 is present, signal "s+Q" may also be a fourth signal selectable by selection circuit 325. The selection is based on two control signals, a scan enable signal from the scan enable port 360 of the observation scan unit 300 and an observation scan enable signal from the observation scan enable port of the observation scan unit 300. It should be noted that while selection circuit 325 is shown to receive signals from combining circuit 321 and combining circuit 323, some portions of selection circuit 325 may output signals to either or both of them. One such example will be discussed later.

Based on these two control signals, if the selection and combination circuit 320 does not have the combination circuit 323, the observation scanning unit 300 can operate in one of the above three modes (shift mode, capture mode, and shift-observation mode). Otherwise, the observation scan unit 300 may also operate in a capture-accumulation mode. Fig. 4 shows a table summarizing four modes in which the observation scan unit 300 can operate and the associated settings of the two control signals. For example, when the observation scan enable signal is not activated, the operation of the observation scan unit 300 is similar to the scan unit 200 in fig. 2, and a shift operation or a capture operation is performed based on the scan enable signal during a test. Unlike the scan cell 200, in either of these two operations, the data bits stored in the observation scan cell 300 are not applied to the functional circuit 390. This is because the observation scan cell 300 does not have the same parallel output injection of stored bits as the scan cell 200 in fig. 2. When the observation scan enable signal is activated, the observation scan unit 300 may capture test response bits based on the scan enable signal and combine them with stored bits (capture-accumulate) or capture test responses every shift clock cycle (shift-observe). Also, the stored bits do not affect the functional circuit 390.

Referring back to fig. 1, the test architecture 100 may also include a pseudo-random vector generator (PRPG) 130 and a test response compressor 140. The pseudorandom vector generator 130 is configured to generate test vectors for the test circuit, the outputs of which are coupled to serial inputs of the scan chain 110 and one or more observation scan chains 150. Test response compressor 140 is configured to compress a test response with its input coupled to serial outputs of scan chain 110 and one or more observation scan chains 150.

The pseudo-random vector generator 130 may be constructed from a Linear Feedback Shift Register (LFSR) or a cellular automaton. The loop generator is a linear finite state machine that can be derived by changing the canonical form of the linear feedback shift register (external feedback, internal feedback) while maintaining its transfer function. The pseudo-random vector generator 130 may include a loop generator and a phase shifter. The phase shifter may include XOR gates and may extend the finite output of the circular generator to drive a large number of scan chains 150 and one or more observation scan chains 150. The test decompressors used for Embedded Deterministic Testing (EDT) may also be implemented using a loop generator and a phase shifter. Thus, manufacturing tests and in-system tests may share the same hardware to reduce test circuit overhead. The pseudorandom vector generator 130 may be configured as a test decompressor during deterministic testing immediately after chip fabrication is complete and then reconfigured as a pseudorandom vector generator for in-system testing after the chip is installed into a system (e.g., an automobile).

Test response compressor 140 may include a time test response compression circuit, such as a Multiple Input Signature Register (MISR). Test response compressor 140 may further include a spatial test response compression circuit, such as one or more XOR gate networks. The test response compressor 140 may also further include an X-masking circuit configured to mask the X bits in the test response.

Test application time may be shortened with test architecture 100 by configuring one or more observation scan chains 150 to operate under shift observation mode testing while scan chains 110 perform conventional shift operations. The changing content of the scan cells in scan chain 110 becomes the stimulus of the feed circuit every clock cycle, while the observation scan cells in one or more observation scan chains 150 capture and accumulate test responses every clock cycle. The test architecture 100 may also retain the benefits of the conventional per-shift test approach by allowing the scan chains 110 to capture test responses after the shift operation loads the test vectors.

To improve test coverage, suitable test point locations, such as observation points coupled to one or more observation scan chains 150, may be determined by searching for internal lines of propagation paths that are less observable but are preferred for a large number of faults. In addition, the control points coupled to scan chain 110 are selected to increase their detection probability by also considering whether the control points coupled to scan chain 110 can improve the propagation of faults to observation points driven per clock test.

X-tolerant and multi-stage observation scan

The X state occurs in the circuit design due to non-scan flip-flops, uninitialized storage elements, floating buses, bus contention, internal tri-state logic, unpackaged analog blocks, spurious paths, cross-domain paths, or paths with timing closure issues. The X state may cause unknown bits (X bits) to appear in the test response, severely degrading the test quality. Typically, the test response compressor employs a mechanism to mask the X bits, which is referred to as X masking. Not all X bits captured in the scan cell will be masked in subsequent manufacturing tests. Designers often attempt to trade-off between on-chip test logic complexity, collateral damage caused by inadvertently masking non-X bits, test coverage and test time resulting therefrom, and test data required to control X masking. On the other hand, in-system test setup requires control of scan selection with a minimum amount of data without compromising high test quality. For safety critical devices that must be self-tested during system operation, it is often necessary to prevent all X bits from reaching the test response compressor. This is especially true for compressors that include multiple input signature registers, where feedback can cause the X bits to spread out quickly, resulting in the whole test being useless.

The test compressor may employ an X-mask circuit to mask the X bits in the test response based on the mask information stored in the registers. One simple method for X-masking is to mask any scan chain that captures at least one X-bit. This may result in low fault coverage or high vector counts because many useful test response bits may also be masked. To address this problem, the X-mask circuit may be configured to mask the X bits in each shift clock cycle pattern, thereby masking only some of the bits output from the scan chain, but allowing other bits to be compressed. However, both methods are less effective for the observational scanning technique. Any X bits captured by conventional scan cells in a conventional scan chain may propagate into the circuit during a shift operation and damage more observation scan cells in an observation scan chain operating in a shift-observation mode.

Fig. 5 uses an observation scanning system 500 to show how X-bits captured by a conventional scanning unit can damage the observation scanning unit. The observation scan system 500 includes conventional scan chains 511-514, an observation scan chain 520, a pseudo-random vector generator 530 configured to generate test vectors, and a multi-input signature register 540 as a test response compressor. During the capture operation, three scan cells 521, 523, and 524 in scan chains 511, 513, and 514, respectively, capture X bits. As previously discussed, these captured X bits are applied serially to the functional circuits in shift mode through the parallel output ports of the scan cells in scan chains 511, 513, and 514. Thus, these X bits may cause some X states to be captured by the observation scan cells in observation scan chain 520. Masking the observation scan chain will lose the benefit of the observation scan technique.

According to various embodiments of the disclosed technology, a multi-stage observation scan scheme may be employed to reduce the effects of the X bits. Fig. 6 shows an example of such a multi-stage observation scanning scheme. The multi-stage observation scanning scheme may include two stages, a scan capture stage 610 and an observation scanning stage 620. In scan capture phase 610, the scan cells in regular scan chain 630 and the observation scan cells in observation scan chain 640 alternately operate in a shift mode and a capture mode. In shift mode, test vectors are shifted into scan chain 630, and in capture mode, scan cells in scan chain 630 capture test responses. Scan chain 630 then switches back to shift mode, shifting out the captured test response, and simultaneously shifting in the next test vector. Unlike the scan cells in conventional scan chain 630, the observation scan cells in observation scan chain 640 do not participate in applying test vectors to the circuit because they have no parallel output ports. Nor do they capture test responses in shift mode. However, the observation scan cells in the observation scan chain 640 can also capture test responses in capture mode.

In observation scan stage 620, the scan cells in regular scan chain 630 operate in a shifted mode, while the observation scan cells in observation scan chain 640 operate in a shifted observation mode. At this stage, the conventional scan chain 630 continually applies test stimulus to the circuit, while the observation scan chain 640 continually captures the corresponding test response. The timing anomaly path is the main source of the X state, so that the X state is rarely generated in the shift mode. Even if an observation scan cell captures an X bit, the X bit will not propagate back into the circuit to destroy other observation scan cells. Thus, most of the output of the observation scan chain 640 need not be masked and the observation scan stage 620 can retain the benefits of the observation scan technique. According to some embodiments of the disclosed technology, the number of test vectors for the observation scan capture phase may be less than or equal to the number of test vectors for the scan phase.

FIG. 7A shows a table showing characteristics of four industrial designs and X-state injection and resulting damage to the observation scan chain under a single-stage observation scan scheme. Each of the four industrial designs D1, D2, D3 and D4 has approximately 100 to 300 tens of thousands of gates, and 1254, 1255, 2502 and 528 scan chains, respectively. Of these scan chains, there are 34, 39, 74 and 7 observation scan chains, respectively. In a single-stage observation scan scheme, the conventional scan chains alternately operate in a shift mode and a capture mode, while the observation scan chains alternately operate in a shift-observation mode and a capture-accumulation mode. As shown in the sixth column, a small amount of random X is injected in each of the four designs. As a result, 1% -2.5% of the conventional scan chains capture X bits, but 57% -94% of the observation scan chains capture X bits. This suggests that the X state can have a significant adverse effect on the single-phase observation scan scheme, as most observation scan chains have to be masked.

FIG. 7B shows a table showing test vector counts required to achieve 90% test coverage under different test schemes and/or conditions for the four industrial designs in FIG. 7A. Column B shows the number of test vectors required under conditions where neither the X state nor the observation scan chain is used. Column C shows the number of test vectors required without injecting the X state but using the observation scan chain. Column D calculates the ratio of columns B to C, which shows that vector counts can be reduced by more than 7 times using the observation scan chain, in addition to design 4.

Column E shows test vector counts with the X state injected but without the observation scan chain. Column F shows the test vector counts under the conditions of injecting the X-state and using the observation scan chain in a two-stage observation scan scheme. Columns G and H list the ratio of columns E to F and the ratio of columns B to F, respectively. Column G shows a significant reduction in vector counts when using a two-stage observation scan scheme. This cannot be achieved using a single-stage observation scan scheme. Even with the design of D1-D3, a vector count reduction of more than 2.5 times can be achieved using a two-stage observation scan scheme, as compared to conventional LBST operation without X-state. For design D4, the two-stage observation scan scheme only requires an increase in vector of about 15% compared to a conventional LBIST run without any X-state.

Example of an observation scan Unit architecture

Fig. 8 illustrates a block diagram example of an observation scan unit 800, which observation scan unit 800 can be implemented in accordance with various embodiments of the disclosed technology. Similar to the observation scan unit 300 in fig. 3, the observation scan unit 800 includes a state element 810 and a selection and combination circuit 820. The state element 810 may be implemented using a flip-flop. The selection and combination circuit 820 includes two logical XOR gates 830 and 840, which function as the combination circuit 321 and the combination circuit 323 shown in fig. 3, respectively. XOR gate 930 may generate the first signal by combining a signal from scan input port (SI) 870 of observation scan unit 800 with a signal from functional circuit input port (D) 860 (also referred to as a parallel input port) of observation scan unit 800. XOR gate 840 may generate a second signal by combining a signal from functional circuit input port (D) 860 of observation scan unit 800 with output signal (Q) 815 of state element 810. The select and combine circuit 820 further includes a four-to-one multiplexer 850 that serves as the select circuit 325 shown in fig. 3. The four-to-one multiplexer 850 may select the input signal of the state element 810 from among the first signal, the second signal, the signal from the scan input port (SI) 870 of the observation scan unit 800, and the signal from the functional circuit input port (D) 860 of the observation scan unit 800 based on the two select input signals M1 (880) and M2 (890) of the observation scan unit 800. The selection input signals M1 (880) and M2 (890) may be the scan enable signal and the observation scan enable signal in fig. 4, respectively.

When a signal from a scan input port (SI) 830 of the observation scan unit 800 is selected, the observation scan unit 800 operates in a normal shift mode. When a signal from the functional circuit input port (D) 840 of the observation scan unit 800 is selected, the observation scan unit 800 operates in a normal capture mode or a circuit functional mode. When the first signal is selected, the observation scan unit 800 accumulates circuit test responses during a shift mode of the conventional scan unit, corresponding to the shift observation mode shown in fig. 4. When the second signal is selected, the observation scan unit 800 accumulates circuit test responses during the capture mode of the conventional scan unit, corresponding to the capture-accumulation mode shown in fig. 4.

Fig. 9 illustrates another example of a block diagram of an observation scan unit 900, which observation scan unit 900 can be implemented in accordance with various embodiments of the disclosed technology. Like the observation scan unit 800, the observation scan unit 900 includes a status element 910 and a selection and combination circuit 915. Also like the observation scan unit 800, the selection and combination circuit 915 includes two logical XOR gates 940 and 930, which are used as the combination circuit 321 and the combination circuit 323 shown in fig. 3, respectively. Unlike the select AND combine circuit 820 of fig. 8, the select AND combine circuit 915 employs two AND gates 923 AND 925 AND a two-to-one multiplexer 920 (rather than the single four-to-one multiplexer 850) to perform the select function.

When the select input signal M2 (950) is 0, the outputs of AND gate 923 AND gate 925 are both 0. Thus, the outputs of XOR gate 940 and XOR gate 930 will follow the signals from scan input port (SI) 980 and functional circuit input port (D) 970, respectively. Another select input signal M1 (960) will determine whether the signal at scan input port (SI) 980 or the signal at functional circuit input port (D) 970 drives the state element 910. These two modes of operation correspond to a conventional shift mode and a conventional capture mode, respectively.

When the select input signal M2 (950) is 1, the outputs of AND gate 923 AND gate 925 are the signal from output port (Q) 990 of state element 910 AND the signal from functional circuit input port (D) 970, respectively. Thus, XOR gate 940 and XOR gate 930 combine the signal from functional circuit input port (D) 970 with the signal from scan input port (SI) 980 and the signal from the output port of state element 910, respectively. The selection input signal M1 (960) may decide whether the previous or the next combined signal drives the state element 910, which correspond to the shift-observe mode and the capture-accumulate mode in fig. 4, respectively.

Example computing Environment

Some embodiments of the disclosed technology related to inserting test circuits into a design may be implemented by execution of software instructions by a computing device, such as a programmable computer. Fig. 10 shows an illustrative example of such a programmable computer (computing device 1001). As shown, the computing device 1001 includes a computing unit 1003, the computing unit 1003 having a processing unit 1005 and a system memory 1007. The processing unit 1005 may be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. The system memory 1007 may include Read Only Memory (ROM) 1009 and Random Access Memory (RAM) 1011. Those skilled in the art will appreciate that Read Only Memory (ROM) 1009 and Random Access Memory (RAM) 1011 may both store software instructions for execution by processing unit 1005.

The processing unit 1005 and the system memory 1007 are directly or indirectly connected to one or more peripheral devices through a bus 1013 or alternative communication structure. For example, the processing unit 1005 or system memory 1007 may be directly or indirectly connected to one or more additional memory storage devices, such as a "hard" magnetic disk drive 1015, a removable magnetic disk drive 1017, an optical disk drive 1019, or a flash memory card 1021. The processing unit 1005 and the system memory 1007 may also be directly or indirectly connected to one or more input devices 1023 and one or more output devices 1025. Input devices 1023 may include, for example, a keyboard, a pointing device (e.g., a mouse, touchpad, stylus, trackball or joystick), a scanner, a camera, and a microphone. Output device 1025 may include, for example, a display, a printer, and speakers. In various examples of computer 1001, one or more peripheral devices 1015-1025 may be mounted internally with computing unit 1003. In addition, one or more peripheral devices 1015-1025 may be located outside the housing of computing unit 1003 and connected to bus 1013 by, for example, a Universal Serial Bus (USB) connection.

In some implementations, the computing unit 1003 may be directly or indirectly connected to one or more network interfaces 1027 for communicating with other devices making up the network. The network interface 1027 converts the data and control signals from the calculation unit 1003 into network information according to one or more communication protocols, such as Transmission Control Protocol (TCP) and Internet Protocol (IP). In addition, interface 1027 may also employ any suitable connection agent (or combination of agents) to connect to a network, including, for example, a wireless transceiver, modem, or ethernet connection. These network interfaces and protocols are well known in the art and therefore will not be discussed in detail herein.

It should be understood that computer 1001 is illustrated by way of example only and is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of computer 1001 shown in FIG. 10, or that include only a subset of the components shown in FIG. 10, or that include alternative combinations of components, including components not shown in FIG. 10. For example, various embodiments of the disclosed technology may be implemented using multiple processor computers, multiple single processors arranged in a network, and/or multiple processor computers, or some combination of both.

Conclusion(s)

While the disclosed technology has been described with respect to specific examples including presently preferred modes of carrying out the disclosed technology, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques that fall within the spirit and scope of the disclosed technology as set forth in the appended claims. For example, while two examples of selection and combination circuits in a scanning unit (fig. 3 and 5) have been used in order to describe the disclosed technology, it should be understood that various examples of the disclosed technology may be implemented using selection and combination circuits having topologies different from those shown in fig. 3 and 5.

Claims (17)

1. A circuit, comprising:

a scan chain comprising a scan cell configured to operate in a shift mode or a capture mode based on a scan enable signal, a parallel output of the scan cell being coupled to a functional circuit of the circuit;

one or more observation scan chains including an observation scan unit configured to operate in a shift mode, a capture mode, or a shift observation mode based on the scan enable signal and an observation scan enable signal, an output of the observation scan unit not coupled to the functional circuitry of the circuitry, and

A test controller including circuitry configured to generate the scan enable signal and the observation scan enable signal for testing the circuitry, the test including a scan capture phase during which the scan cell and the observation scan cell alternately operate in the shift mode and the capture mode, and an observation scan phase during which the scan cell operates in the shift mode and the observation scan cell operates in the shift observation mode.

2. The circuit of claim 1, wherein the number of test vectors for the observation scan capture stage is less than or equal to the number of test vectors for the scan stage.

3. The circuit of claim 1, further comprising:

A pseudo-random vector generator configured to generate test vectors to be shifted into the scan chain and the one or more observation scan chains, and

A test compressor configured to compress test responses shifted out of the scan chain and the one or more observation scan chains.

4. The circuit of claim 1, wherein each of the observation scan units comprises:

Status element, and

A selection and combination circuit, comprising:

A combining circuit configured to combine the signal from the serial input port of each of the observation scan units with the signal from the parallel input port of each of the observation scan units to generate an observation scan signal, and

A selection circuit configured to select an input signal of the state element from among a signal from the serial input port, a signal from the parallel input port, and the observation scan signal based on the scan enable signal and the observation scan enable signal.

5. The circuit of claim 4, wherein the select and combine circuit further comprises:

Another combining circuit configured to combine the signals from the parallel input ports with the output signals of the state elements to generate a capture-accumulation signal,

Wherein the selection circuit is configured to select the input signal of the state element from among the signal from the serial input port, the signal from the parallel input port, the observation scan signal, and the capture accumulation signal based on the scan enable signal and the observation scan enable signal.

6. The circuit of claim 4, wherein the combining circuit comprises an XOR gate.

7. The circuit of claim 4, wherein the state element is a flip-flop.

8. The circuit of claim 4, wherein the selection circuit comprises a 2-to-1 multiplexer AND two AND gates.

9. One or more computer-readable media storing computer-executable instructions for causing one or more processors to perform a method comprising creating a circuit in a circuit design, the circuit comprising:

a scan chain comprising a scan cell configured to operate in a shift mode or a capture mode based on a scan enable signal, a parallel output of the scan cell being coupled to a functional circuit of the circuit;

one or more observation scan chains including an observation scan unit configured to operate in a shift mode, a capture mode, or a shift observation mode based on the scan enable signal and an observation scan enable signal, an output of the observation scan unit not coupled to the functional circuitry of the circuitry, and

A test controller including circuitry configured to generate the scan enable signal and the observation scan enable signal for testing the circuitry, the test including a scan capture phase during which the scan cell and the observation scan cell alternately operate in the shift mode and the capture mode, and an observation scan phase during which the scan cell operates in the shift mode and the observation scan cell operates in the shift observation mode.

10. The one or more computer-readable media of claim 9, wherein the number of test vectors of the observation scan capture stage is less than or equal to the number of test vectors of the scan stage.

11. The one or more computer-readable media of claim 9, wherein the circuitry further comprises:

A pseudo-random vector generator configured to generate test vectors to be shifted into the scan chain and the one or more observation scan chains, and

A test compressor configured to compress test responses shifted out of the scan chain and the one or more observation scan chains.

12. The one or more computer-readable media of claim 9, wherein each of the observation scan units comprises:

Status element, and

A selection and combination circuit, comprising:

A combining circuit configured to combine the signal from the serial input port of each of the observation scan units with the signal from the parallel input port of each of the observation scan units to generate an observation scan signal, and

A selection circuit configured to select an input signal of the state element from among a signal from the serial input port, a signal from the parallel input port, and the observation scan signal based on the scan enable signal and the observation scan enable signal.

13. The one or more computer-readable media of claim 12, wherein the selection and combining circuitry further comprises:

Another combining circuit configured to combine the signals from the parallel input ports with the output signals of the state elements to generate a capture-accumulation signal,

Wherein the selection circuit is configured to select the input signal of the state element from among the signal from the serial input port, the signal from the parallel input port, the observation scan signal, and the capture accumulation signal based on the scan enable signal and the observation scan enable signal.

14. The one or more computer-readable media of claim 12, wherein the combining circuit comprises an XOR gate.

15. The one or more computer-readable media of claim 12, wherein the status element is a trigger.

16. The one or more computer-readable media of claim 12, wherein the selection circuit comprises a 2-to-1 multiplexer AND two AND gates.

17. A method, comprising:

the test circuitry is configured to test the circuit,

Wherein the circuit comprises a scan chain and one or more observation scan chains, the scan chain comprising a scan cell, the one or more observation scan chains comprising an observation scan cell, and

Wherein the test comprises a scan capture phase and an observation scan phase, during which the scan unit and the observation scan unit are alternately operated in a shift mode and a capture mode, and during which the scan unit is operated in the shift mode and the observation scan unit is operated in a shift observation mode.