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CN120319165B - Data processing circuit, display device and data processing method - Google Patents

Data processing circuit, display device and data processing method

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Publication number
CN120319165B
CN120319165B CN202510798043.7A CN202510798043A CN120319165B CN 120319165 B CN120319165 B CN 120319165B CN 202510798043 A CN202510798043 A CN 202510798043A CN 120319165 B CN120319165 B CN 120319165B
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China
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previous
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state
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Application number
CN202510798043.7A
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Chinese (zh)
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CN120319165A (en
Inventor
陈志翔
何庆涛
孙丽娜
刘建
牛越
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Tianyi Microelectronics Hangzhou Co ltd
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Tianyi Microelectronics Hangzhou Co ltd
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Priority to CN202510798043.7A priority Critical patent/CN120319165B/en
Publication of CN120319165A publication Critical patent/CN120319165A/en
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Publication of CN120319165B publication Critical patent/CN120319165B/en
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application discloses a data processing circuit, a display device and a data processing method. The data processing circuit comprises a judging module, a processing module and a time sequence control module, wherein the judging module receives first image data and obtains control signals according to the first image data, the processing module processes the first image data to obtain second image data and stores the second image data, the time sequence control module processes the second image data to obtain digital signals, the control signals are output to control the processing module to directly output the second image data when the judging module judges that the first image data is in a first state, and the control signals are output to control the processing module to process the first image data when the judging module judges that the first image data is in a second state.

Description

Data processing circuit, display device and data processing method
Technical Field
The present invention relates to the field of display technologies, and in particular, to a data processing circuit, a display device, and a data processing method.
Background
As the resolution of display panels increases, the refresh rate and speed also increase, and thus, power consumption increases, reducing the power consumption of display devices has become a hot spot problem for research.
The data processing circuitry represents a significant part of the power consumption of the display device. Especially when the operations such as real-time noise reduction, super-resolution algorithm, dynamic contrast enhancement and the like are required, the power consumption of the data processing circuit is greatly increased. In order to reduce the power consumption of data processing circuits, the prior art generally employs dedicated hardware acceleration (e.g., AI coprocessors) or dynamic shutdown of unnecessary functions. However, the above-described manner of reducing the power consumption of the data processing circuit greatly increases the complexity of the circuit.
It is therefore desirable to provide an improved data processing circuit that reduces power consumption and compromises circuit simplicity.
Disclosure of Invention
In view of the foregoing, an object of the present invention is to provide a data processing circuit, a display device and a data processing method, which can reduce power consumption and achieve simplicity of the circuit.
According to an aspect of the present invention, there is provided a data processing circuit comprising:
The judging module is used for receiving the first image data and obtaining a control signal according to the first image data;
A processing module for processing the first image data to obtain second image data and storing the second image data;
a timing control module for processing the second image data to obtain digital signals,
Wherein when the judging module judges that the first image data is in a first state, the control signal is output to control the processing module to directly output the second image data,
And when the judging module judges that the first image data is in the second state, outputting the control signal to control the processing module to process the first image data.
Optionally, the judging module comprises a first unit and a second unit,
The first unit stores the first image data of the previous line, compares the first image data of the current line with the first image data of the previous line, and judges that the first image data of the current line is in the first state if the first image data of the current line is the same as the first image data of the previous line;
The second unit stores each piece of first image data of a current line, compares the current first image data with the previous first image data, and judges that the current first image data is in the first state if the current first image data is the same as the previous first image data;
And if the first unit judges that the first image data of the current line is different from the first image data of the previous line, and the second unit judges that the current first image data is different from the previous first image data, the judging module judges that the current first image data is in the second state.
Optionally, the first unit has a higher priority than the second unit, and after the first unit determines that the first image data of the current line is in the first state, the second unit does not perform the determining action on the first image data of the current line.
Optionally, the first unit is further configured to determine whether the number of the same first image data reaches a set value if the first image data of the current line is the same as the first image data of the previous line, and if so, output the control signal to control the processing module to directly output the second image data, and if not, wait for the determining module to continue receiving the first image data until the number of the same first image data reaches the set value.
Optionally, the second unit is further configured to determine whether the number of identical first image data reaches a set value if the current first image data is identical to the previous first image data, and if so, output the control signal to control the processing module to directly output the second image data, and if not, wait for the determining module to continue receiving the first image data until the number of identical first image data reaches the set value.
Optionally, the second unit is further configured to count the same number of the first image data by using a counter, and clear the counter and output the corresponding control signal if the current first image data is different from the previous first image data or the same number of the first image data reaches a set value.
According to a second aspect of the present invention, there is provided a display device comprising:
a data processing circuit for providing a digital signal corresponding to the first image data as described above, and
And the display panel converts the digital signal into an analog signal and performs luminous display according to the analog signal.
According to a third aspect of the present invention, there is provided a data processing method comprising:
obtaining a control signal according to the first image data;
processing the first image data to obtain second image data and storing the second image data;
processing the second image data to obtain a digital signal,
Wherein when the first image data is in a first state, the control signal corresponding to the first state is output to directly output the second image data,
When the first image data is in a second state, the control signal corresponding to the second state is output to process the first image data.
Optionally, obtaining the control signal from the first image data includes:
Comparing the first image data of the current line with the first image data of the previous line, if the first image data of the current line is identical with the first image data of the previous line, judging that the first image data of the current line is in the first state, and outputting the control signal corresponding to the first state;
comparing the current first image data with the previous first image data, judging that the current first image data is in the first state if the current first image data is the same as the previous first image data, and outputting the control signal corresponding to the first state;
And if the first image data of the current row is different from the first image data of the previous row and the current first image data is different from the previous first image data, judging that the current first image data is in the second state, and outputting the control signal corresponding to the second state.
Optionally, after determining that the first image data of the current line is in the first state, the determining action is not performed on the single first image data of the current line.
Optionally, if the first image data of the current line is identical to the first image data of the previous line, or if the current first image data is identical to the previous first image data, determining whether the number of identical first image data reaches a set value,
If yes, outputting the control signal to directly output the second image data, and if no, continuing to receive the first image data until the same number of the first image data reaches a set value.
According to the data processing circuit, the display device and the data processing method, the state judgment is carried out on the first image data, when the same first image data exist, the data processing is not carried out on the same first image data, the selectivity is high, only part of functions or all functions in the data processing circuit can be started through configuration, and the power consumption can be saved.
In some alternative embodiments, the data processing circuit and the display device may design different parameters according to a specific circuit design, for example, the first unit and the second unit may use different types of memories/buffers to store data, and may set a counter, or may not set a counter, so that the circuit has good expansibility and high efficiency.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a schematic diagram of a display device according to an embodiment of the invention;
FIG. 2 shows a schematic diagram of a data processing circuit according to an embodiment of the invention;
Fig. 3 shows a flow chart of a data processing method according to a first embodiment of the invention;
fig. 4 shows a flow chart of a data processing method according to a second embodiment of the invention;
fig. 5 shows a flow chart of a data processing method according to a third embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown in the drawings.
Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that the connection/coupling between a and B in the embodiments of the present application means that a and B may be connected in series or parallel, or that a and B may be connected by other devices, which are not limited in the embodiments of the present application.
Embodiments of a data processing circuit, a display device, and a data processing method according to the present application will be described below with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a display device according to an embodiment of the invention.
As shown in fig. 1, the display device 100 includes a host 110, a data processing circuit 120, and a display panel 130.
The host 110 is used to generate or receive image data. The host 110 may be a stand-alone electronic device (e.g., a computer, a mobile phone, a set-top box), or a control module integrated within the display apparatus 100. The host 110 communicates with the data processing circuit 120 via a wired or wireless interface (e.g., HDMI, USB, wi-Fi), and the transmitted signals include, but are not limited to, digital video signals, control instructions, or configuration parameters. Image data (e.g., RGB format or YCbCr format) output by the host 110 is processed by the data processing circuit 120.
The data processing circuit 120 receives and processes image data from the host 110, and generates digital signals (including scan signals and data signals) required to drive the display panel 130. The data processing circuit 120 may be integrated On a flexible circuit board (Flexible Printed Circuit Board, FPCB) or a printed circuit board (Printed Circuit Board, PCB), for example, and electrically connected to the display panel 130 through connectors (e.g., chip On Film (COF), tape carrier package (TAPE CARRIER PACKAGE, TCP), etc.). The data processing circuit 120 may be a timing controller, may be a control device that includes a timing controller and performs other control functions, or may be a control device other than a timing controller. The Data processing circuit 120 includes at least a timing controller (Timing Controller, TCON) to convert signals into progressive synchronization signals including, for example, horizontal synchronization signals (Horizontal Synchronization, HSYNC), vertical synchronization signals (Vertical Synchronization, VSYNC), and generate driving signals of corresponding scan lines (Gate lines) and Data lines (Data lines) according to the synchronization signals.
The display panel 130 includes a substrate 131, a pixel array 132, a scan driving circuit 133, and a data driving circuit 134, wherein the pixel array 132 is disposed on the substrate 131, and the driving circuit is used for driving each pixel circuit in the pixel array 132. In the display panel 130, one column of pixel circuits shares one data line, one row of pixel circuits shares one scan line, and all pixel circuits may share one common voltage. The scan driving circuit 133 may include one or more scan driver ICs (GDICs). Each scan driver IC may include a shift register, a level shifter, and the like. The data drive circuit 134 may include one or more Source Driver ICs (SDICs). Each source driver IC may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, and the like. In some cases, the source driver IC may also include an analog-to-digital converter (ADC). The data driving circuit 134 is also referred to herein as a "source driver". In the display panel 130, the scan lines sequentially activate the pixel circuits in rows or columns, and the data lines write data voltages or currents to the activated pixel circuits, thereby forming an image on the substrate 131.
In the embodiment of the present application, the type of the display panel 130 may be any one of a Low-temperature polysilicon Organic light Emitting Diode (LTPS OLED) display panel, a Micro Organic LIGHT EMITTING Diode (Micro-OLED) display panel, a Mini Organic LIGHT EMITTING Diode, mimi-OLED display panel, a Micro light Emitting Diode (Micro LIGHT EMITTING Diode, micro-LED) display panel, a passive matrix Organic light Emitting Diode (Passive Matrix Organic LIGHT EMITTING Diode, passive Matrix OLED) display panel, an active matrix Organic light Emitting Diode (Active Matrix Organic LIGHT EMITTING Diode, active Matrix OLED) display panel, a Flexible Organic LIGHT EMITTING Diode (Flexible OLED) display panel, a transparent Organic light Emitting Diode (TRANSPARENT ORGANIC LIGHT EMITTING Diode, TRANSPARENT OLED) display panel, a quantum dot (Quantum Dot Light-email Diode, QLED) display panel, and an Electronic paper display (Electronic display panel.
The data processing circuit 120 controls the data driving circuit 134 and the scan driving circuit 133 by supplying a data signal and a scan signal to the data driving circuit 134 and the scan driving circuit 133, respectively. The data processing circuit 120 starts scanning at a timing realized by each frame, converts image data input from the host 110 into second image data having a digital signal format readable by the data driving circuit 134, outputs the second image data, and controls data driving at an appropriate point in time according to the scanning. The scan driving circuit 133 sequentially supplies a scan signal having an on or off voltage to the plurality of scan lines GL under the control of the data processing circuit 120. When the predetermined scan line GL is turned on by the scan driving circuit 133, the data driving circuit 134 converts the digital signal (including the second image data) received from the data processing circuit 120 into analog image data, and supplies the data signal Vdata corresponding to the analog image data to the plurality of data lines DL. The data driving circuit 134 drives the plurality of data lines DL by supplying the data signal Vdata to the plurality of data lines DL.
The scan driving circuit 133 sequentially drives the plurality of scan lines GL by sequentially supplying a scan signal Vgate (also referred to as a scan voltage, a scan signal, or a gate voltage) to the plurality of scan lines GL. The scan driving circuit 133 is also referred to herein as a "gate driver". Here, the scan signal Vgate includes an off-level gate voltage for turning off the corresponding scan line GL and an on-level gate voltage for turning on the corresponding scan line GL. More specifically, the scan signal Vgate includes an off-level gate voltage that turns off the transistor connected to the corresponding scan line GL and an on-level gate voltage that turns on the transistor connected to the corresponding scan line GL.
In the case where the transistor in the pixel circuit is an n-type transistor, the off-level scanning voltage may be a low-level scanning voltage VGL, and the on-level scanning voltage may be a high-level scanning voltage VGH. If the transistor is a p-type transistor, the off-level scan voltage may be a high-level scan voltage VGH and the on-level scan voltage may be a low-level scan voltage VGL.
Some examples of the display device of the embodiment of the present invention are described above, however, the embodiment of the present invention is not limited thereto, and other manners of expansion and modification are also possible.
The data processing circuit 120 provided by embodiments of the present application may be provided as a separate component from the data driving circuit 134, or may be provided in combination with the data driving circuit 134 to form an Integrated Circuit (IC).
The respective source driver ICs may be connected to bonding pads of the display panel 130 by a Tape Automated Bonding (TAB) method or a Chip On Glass (COG) method, may be directly mounted on the display panel 130, or in some cases, may be integrated with the display panel 130. In addition, each source driver IC may be implemented using a chip-on-film (COF) structure mounted to be connected to the display panel 130.
The respective scan driving circuits 133 may be connected to the bonding pads of the display panel 130 by a TAB method or a COG method, may be implemented using a Gate In Panel (GIP) structure directly mounted on the display panel 130, or may be integrated with the display panel 130 in some cases. In addition, each gate driving circuit may be implemented using a COF structure mounted on a film connected to the display panel 130.
The data driving circuit 134 may be disposed at one side of the display panel 130 (e.g., at an upper or lower portion of the display panel 130), as shown in fig. 1. In some cases, the data driving circuit 134 may be disposed at both sides of the display panel 130 (e.g., at upper and lower portions of the display panel 130) according to a driving system, a design of the display panel, etc.
The scan driving circuit 133 may be disposed at one side of the display panel 130 (e.g., at the right or left portion of the display panel 130), as shown in fig. 1. In some cases, the scan driving circuit 133 may be disposed at both sides of the display panel 130 (e.g., at right and left portions of the display panel 130) according to a driving system, a design of the display panel, and the like.
Each pixel circuit arranged in the display panel 130 may include one or more circuit elements (e.g., transistors or capacitors).
For example, in the case where the display panel 130 is an LCD panel, pixel electrodes may be disposed in respective pixel circuits, and transistors may be electrically connected between the pixel electrodes and the corresponding data lines DL. The transistor may be turned on by a scan signal Vgate supplied to the gate electrode through the scan line GL. When turned on, the transistor may output the data signal Vdata supplied to the source electrode (or drain electrode) via the data line DL to the drain electrode (or source electrode) such that the data signal Vdata is applied to the pixel electrode electrically connected to the drain electrode (or source electrode). An electric field may be generated between the pixel electrode to which the data signal Vdata is applied and the common electrode COM to which the common voltage Vcom is applied, and a capacitance may be generated between the pixel electrode and the common electrode COM.
The structure of each pixel circuit may be determined differently according to the type of display panel, the function provided by the panel, the design, and the like.
In addition, the display device can integrate other functional modules. For example, the touch sensing layer is integrated on the surface or inside of the display panel 130 to realize a touch input function, the 3D display module alternately displays left eye and right eye images through time division and is matched with shutter glasses or cylindrical lenses to realize stereoscopic vision, the flexible display module is used for the display panel 130 to support bending or folding by adopting a flexible substrate (such as PI material), the power management module is used for providing stable working voltage for the display driving circuit and the display panel 130, and the heat dissipation structure is used for arranging heat dissipation fins or heat pipes for a high-brightness display panel (such as Micro LEDs) to ensure long-term reliability.
Also, those of ordinary skill in the art will recognize that structures and methods of examples described in connection with the embodiments disclosed herein may be implemented using different configurations or adaptations of each structure or reasonable variations of that structure to achieve the described functionality, but such implementations should not be considered to be beyond the scope of the present application. Also, it should be understood that the connection relationship between the respective components of the amplifier of the foregoing drawings in the embodiments of the present application is illustrative and not limiting in any way.
In the embodiment of the present application, in order to control the power consumption of the display device, a judgment module is provided in the data processing circuit 120 to simplify the data processing. The data processing circuit and the data processing method of the application will be described in detail below with reference to fig. 2-5.
Fig. 2 shows a schematic diagram of a data processing circuit according to an embodiment of the invention.
As shown in fig. 2, the data processing circuit 120 includes a judging module 121, a processing module 122, and a timing control module 123. The DATA processing circuit 120 is a core electronic circuitry responsible for processing, converting and transmitting the first image DATA1 and controlling the display panel to emit light or image. The function of the display device is to convert an input video signal (such as a signal from a video card, a set top box or other devices) into a driving signal which can be recognized by a display panel, and finally, a clear image is displayed on a screen. For example, the DATA processing circuit 120 receives the first image DATA1 from the host and processes it to generate a digital signal DATA3 (e.g., including a scan signal and a DATA signal) required to drive the display panel 130. For example, the DATA processing circuit 120 converts the signal into a progressive synchronizing signal including, for example, a horizontal synchronizing signal (Horizontal Synchronization, HSYNC), a vertical synchronizing signal (Vertical Synchronization, VSYNC), and generates driving signals corresponding to a scan Line (Gate Line) and a DATA Line (DATA Line) from the synchronizing signal and the first image DATA 1.
The judging module 121 is configured to receive the first image DATA1 and obtain a control signal according to the first image DATA1. Wherein, when the judging module 121 judges that the first image DATA1 is in the first state, a control signal corresponding to the first state (hereinafter referred to as a first control signal S1) is outputted to control the processing module 122 to directly output the second image DATA2, and when the judging module 121 judges that the first image DATA1 is in the second state, a control signal (hereinafter referred to as a second control signal S2) corresponding to the second state is output to control the processing module 122 to process the first image DATA1, so that the processing module 122 obtains the second image DATA2 corresponding to the first image DATA1 and stores the second image DATA2. The judging module 121 also has a storage function and can temporarily store the first image DATA1.
In the embodiment of the present invention, the first state means that at least one first image DATA1 is identical to a previous first image DATA1, or at least one line of first image DATA1 is identical to a previous line of first image DATA 1; the second state means that the first image DATA1 of the current line is different from the first image DATA1 of the previous line, and the first image DATA1 is different from the previous first image DATA 1.
As one example, the determination module 121 includes a first unit 1211 for determining whether the first image DATA1 of the current line is in the first state, and a second unit 1212 for determining whether the first image DATA1 of the current single line is in the first state.
The first unit 1211 includes a first buffer and a first comparator. The first buffer buffers at least one line of the first image DATA 1. The first input terminal of the first comparator is connected to the output terminal of the first buffer to receive the first image DATA1 of the previous line, and the second input terminal receives the first image DATA1 of the current line, so that the first comparator can compare whether the first image DATA1 of the current line and the first image DATA1 of the previous line are identical. The first unit 1211 determines that the first image DATA1 of the current line is in the first state if the first image DATA1 of the current line is identical to the first image DATA1 of the previous line. If the first image DATA1 of the current line is different from the first image DATA1 of the previous line, the first unit 1211 determines that the first image DATA1 of the current line is in the second state, and instructs the second unit 1212 to determine whether the current single image DATA is in the first state (e.g., sequentially compares each of the first image DATA1 of the current line with the previous first image DATA 1). After the first comparator completes the comparison of the first image DATA1 of the current line, an instruction is issued to refresh the first buffer and store the first image DATA1 of the current line so as to compare with the first image DATA1 of the next line.
Optionally, the first unit 1211 is further configured to: if the first image DATA1 of the current line is identical to the first image DATA1 of the previous line, it is judged whether the number of identical first image DATA1 reaches the set value, and if so, the control signal is outputted to control the processing module 122 to directly output the second image DATA2, and if not, the waiting judgment module 121 continues to receive the first image DATA1 until the number of identical first image DATA1 reaches the set value.
The second unit 1212 includes a second buffer and a second comparator. The second buffer buffers at least one first image DATA 1. The first input terminal of the second comparator is connected to the output terminal of the second buffer to receive the previous first image DATA1, and the second input terminal receives the current first image DATA1, so that the second comparator can compare whether the current first image DATA1 and the previous first image DATA1 are the same. The second unit 1212 determines that the current first image DATA1 is in the first state if the current first image DATA1 is the same as the previous first image DATA 1. If the first unit 1211 determines that the first image DATA1 of the current line is different from the first image DATA1 of the previous line, and the second unit 1212 determines that the current first image DATA1 is different from the previous first image DATA1, the determination module 121 determines that the current first image DATA1 is in the second state. After the second comparator completes the comparison of the current first image DATA1, an instruction is issued to refresh the second buffer and store the current first image DATA1 so as to compare with the next first image DATA 1.
Optionally, the second unit 1212 is further configured to: if the current first image DATA1 is identical to the previous first image DATA1, it is judged whether the number of identical first image DATA1 reaches the set value, and if so, the control signal is outputted to control the processing module 122 to directly output the second image DATA2, and if not, the waiting judgment module 121 continues to receive the first image DATA1 until the number of identical first image DATA1 reaches the set value.
In some embodiments, the second unit 1212 is further configured to count the same number of first image DATA1 with a counter, clear the counter if the current first image DATA1 is different from the previous first image DATA1 or the same number of first image DATA1 reaches a set value, and output a corresponding control signal. In other embodiments, the absence of a counter is also possible, as the processing of data from the data input is accomplished with some delay itself, and the counter may be omitted to some extent, depending on different design requirements.
Optionally, the judging module 121 is provided with an interface circuit for connecting to an external signal source (such as HDMI interface, LVDS interface) and transmitting data to the processing module 122. Optionally, the interface circuit integrates a Type-C interface, supporting signal and power integrated transmission.
The processing module 122 is configured to process the first image DATA1 to obtain the second image DATA2, and store the second image DATA2. The input terminal of the processing module 122 is connected to the judging module 121 to receive the first image DATA1 and the control signal. If the processing module 122 receives the first control signal S1, the first image DATA1 representing the current line is identical to the first image DATA1 of the previous line, the processing module 122 directly outputs the second image DATA2 stored therein (i.e., the second image DATA2 corresponding to the first image DATA1 of the previous line). Since the first image DATA1 of the current line and the first image DATA1 of the previous line are identical, the second image DATA2 of the current line and the second image DATA2 of the previous line are also identical, the processing module 122 can directly output the second image DATA2 stored therein, which saves the processing steps for the first image DATA1 of the current line, and greatly saves the power consumption of the processing module 122.
The processing module 122 performs decoding, scaling, noise reduction, color correction, etc. on the first image DATA1, for example, by receiving the first image DATA1 (e.g., HDMI, DP, VGA, etc.). The processing circuitry is typically integrated in the form of a chip in the data processing circuitry, e.g. an image processing chip, a video decoding chip.
The timing control module 123 processes the second image DATA2 to obtain a digital signal DATA3. The timing control circuit is used for synchronizing the timing of the second image DATA2, for example, converting the parallel input second image DATA2 (e.g., RGB) into the digital signal DATA3 of the serial DATA stream, divided by row/column. For example, by generating a vertical synchronization signal and a horizontal synchronization signal, the image scanning order is ensured to be correct, and the picture is prevented from tearing or flickering. The timing control module 123 is further configured to generate timing signals, such as a row synchronization (HSYNC) signal, a column synchronization signal (VSYNC), a Clock (CLK) signal, and the like, for coordinating the operation rhythms of the source/gate driving circuits.
In some alternative embodiments, data processing circuit 120 also includes power management circuitry, timing control circuitry, protection circuitry, and the like. The power management circuit is used for providing stable voltages (such as backlight voltage of LCD, high voltage power supply of OLED, common voltage of OLED, etc.) to the display panel and the driving circuit. The power management circuit includes a buck/boost module, a voltage stabilizing circuit, and the like. In the embodiment of the invention, the power management circuit can be directly or indirectly controlled by the power consumption control module, for example, the power management circuit is controlled by a microprocessor in the display circuit, and the microprocessor is controlled by the power consumption control module. And the protection circuit is used for overvoltage and overcurrent protection and preventing the panel or the driving chip from being damaged due to voltage fluctuation.
It should be noted that the specific components of the data processing circuit are merely examples given for more clearly and in detail describing the technical solution of the present invention. These examples are not intended to limit the scope of the invention nor are they intended to limit the invention to the specific circuit configurations and arrangements described.
Fig. 3 shows a flow chart of a data processing method according to a first embodiment of the invention.
As shown in fig. 3, the data processing method includes steps S301 to S303.
In step S301, a control signal is obtained from the first image data. In this step, a status judgment is made on the first image data to determine whether the first image data is in the first state or the second state. The control signals include a first control signal corresponding to the first state and a second control signal corresponding to the second state. The first state means that at least one first image data is identical to a previous first image data or at least one line of first image data is identical to a previous line of first image data, and the second state means that the first image data of the current line is different from the first image data of the previous line and the first image data is different from the previous first image data.
In this step, if the first image data of the current line is the same as the first image data of the previous line, the first image data of the current line is judged to be in the first state. If the first image data of the current line is different from the first image data of the previous line, then the first image data of the current line is judged to be in the second state, and whether the current single image data is in the first state is continuously judged (for example, whether each of the first image data of the current line and the previous first image data are the same or not is sequentially compared). After the comparison of the first image data of the current line is completed, an instruction is issued to refresh the cache and store the first image data of the current line so as to be compared with the first image data of the next line. And if the current first image data is the same as the previous first image data, judging that the current first image data is in a first state. And if the first image data of the current line is different from the first image data of the previous line and the current first image data is different from the previous first image data, judging that the current first image data is in the second state. After the comparison of the current first image data is completed, an instruction is issued to refresh the cache and store the current first image data for comparison with the next first image data.
As an example, obtaining the control signal according to the first image data includes comparing the first image data of the current line with the first image data of the previous line, judging that the first image data of the current line is in a first state if the first image data of the current line is identical to the first image data of the previous line, outputting the control signal corresponding to the first state, comparing the current first image data with the previous first image data, judging that the current first image data is in the first state if the current first image data is identical to the previous first image data, outputting the control signal corresponding to the first state, and judging that the current first image data is in a second state if the first image data of the current line is different from the first image data of the previous line and the current first image data is different from the previous first image data, and outputting the control signal corresponding to the second state.
Optionally, after the first image data of the current line is determined to be in the first state, the determining action is no longer performed on the single first image data of the current line.
Optionally, if the first image data of the current line is the same as the first image data of the previous line, or if the current first image data is the same as the previous first image data, judging whether the number of the same first image data reaches a set value, if so, outputting a control signal to directly output the second image data, and if not, continuing to receive the first image data until the number of the same first image data reaches the set value.
In step S302, the first image data is processed to obtain second image data, and the second image data is stored. When the first image data is in the first state, the first image data of the current line is the same as the first image data of the previous line, so that the second image data of the current line is the same as the second image data of the previous line, a control signal corresponding to the first state can be directly output to directly output the second image data, and when the first image data is in the second state, a control signal corresponding to the second state is output to process the first image data, and the second image data corresponding to the first image data is obtained and stored. Therefore, when the same first image data exist, the same first image data do not need to be subjected to data processing, the processing steps of the first image data of the current line are saved, and the power consumption of a processing circuit is greatly reduced.
In this step, the processing of the first image data includes, for example, receiving the first image data (e.g., HDMI, DP, VGA, etc.), performing decoding, scaling, noise reduction, color correction, etc.
In step S303, the second image data is processed to obtain a digital signal. The digital signals include, for example, data signals and scan signals. In this step, for example, the second image data (e.g., RGB) input in parallel is converted into a digital signal of a serial data stream, divided by row/column. For example, by generating a vertical synchronization signal and a horizontal synchronization signal, the image scanning order is ensured to be correct, and the picture is prevented from tearing or flickering.
Fig. 4 shows a flow chart of a data processing method according to a second embodiment of the invention.
As shown in fig. 4, the data processing method includes steps S401 to S405. This embodiment mainly describes the steps of processing the first image data of the current line.
In step S401, after the first image data is input, it is determined whether or not the first image data of the current line has changed. In this step, the first image data of the current line is compared with the first image data of the previous line. If the first image data of the current line is different from the first image data of the previous line, the first image data of the current line is judged to be in a second state, and a control signal corresponding to the second state is output.
In step S402, if the first image data of the current line is different from the first image data of the previous line, the data is updated and the first image data of the current line is subjected to data processing, the counter is cleared, and the count is restarted.
In step S403, if the first image data of the current line is the same as the first image data of the previous line, it is determined whether the number of the same first image data reaches the set value.
In step S404, if the same number of first image data reaches the set value, the control timing control circuit processes the second image data to output a digital signal (including a data signal and a scan signal).
In step S405, if the number of identical first image data does not reach the set value, the first image data is continuously received until the number of identical first image data reaches the set value.
Fig. 5 shows a flow chart of a data processing method according to a third embodiment of the invention.
As shown in fig. 5, the data processing method includes steps S501 to S507. This embodiment mainly describes the step of processing the current single first image data.
In step S501, after the first image data is input, it is determined whether or not the current first image data has changed. In this step, the current first image data is compared with the previous first image data. And if the current first image data is different from the previous first image data, judging that the current first image data is in a second state, and outputting a control signal corresponding to the second state.
In step S502, the current first image data is different from the previous first image data, the data is updated and the current first image data is subjected to data processing, and step S503 is performed.
In step S503, the counter is cleared and restarted to count, and step S504 is executed.
In step S504, the control timing control circuit processes the second image data to output a digital signal.
In step S505, the current first image data is the same as the previous first image data, the counter is incremented by 1, the same first image data is not processed, and step S506 is performed.
In step S506, it is determined whether the number of identical first image data has reached a set value. If the same number of first image data reaches the set value, steps S503 and S504 are executed.
In step S507, if the number of identical first image data does not reach the set value, the first image data is continuously received until the number of identical first image data reaches the set value.
The data processing circuit, the display device and the data processing method provided by the invention can only process the first image data if the first image data of the continuous multiple lines are the same and each first image data in each line is the same, can only process the first image data if the first image data of the continuous multiple lines are the same and the first image data in each line are different, can only process the first image data of the first line if the first image data of the continuous two lines are different and part or all of the first image data in the current line are the same, can only process the first image data of part or all of the first image data, and only needs to process each first image data if the first image data of the continuous two lines are different and all of the first image data in the current line are different.
According to the data processing circuit, the display device and the data processing method, the state judgment is carried out on the first image data, when the same first image data exist, the data processing is not carried out on the same first image data, the selectivity is high, only part of functions or all functions in the data processing circuit can be started through configuration, and the power consumption can be saved.
In some alternative embodiments, the data processing circuit and the display device may design different parameters according to a specific circuit design, for example, the first unit and the second unit may use different types of memories/buffers to store data, and may set a counter, or may not set a counter, so that the circuit has good expansibility and high efficiency.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims (9)

1. A data processing circuit, comprising:
The judging module is used for receiving the first image data and obtaining a control signal according to the first image data;
A processing module for processing the first image data to obtain second image data and storing the second image data;
a timing control module for processing the second image data to obtain digital signals,
Wherein when the judging module judges that the first image data is in a first state, the control signal is output to control the processing module to directly output the second image data,
When the judging module judges that the first image data is in the second state, the control signal is output to control the processing module to process the first image data,
The judging module comprises a first unit and a second unit,
The first unit stores the first image data of the previous line, compares the first image data of the current line with the first image data of the previous line, and judges that the first image data of the current line is in the first state if the first image data of the current line is the same as the first image data of the previous line;
The second unit stores each of the first image data of the current line, compares the current first image data with the previous first image data, judges that the current first image data is the first state if the current first image data is the same as the previous first image data,
The first unit has a higher priority than the second unit, and after the first unit determines that the first image data of the current line is in the first state, the second unit does not perform a determination operation on the first image data of the current line.
2. The data processing circuit according to claim 1, wherein the judging module judges that the current first image data is the second state if the first unit judges that the first image data of a current line is different from the first image data of a previous line, and the second unit judges that the current first image data is different from the previous first image data.
3. The data processing circuit of claim 1, wherein the first unit is further configured to determine whether the number of identical first image data reaches a set value if the first image data of a current line is identical to the first image data of a previous line, and if so, output the control signal to control the processing module to directly output the second image data, and if not, wait for the determination module to continue receiving the first image data until the number of identical first image data reaches a set value.
4. The data processing circuit according to claim 1, wherein the second unit is further configured to determine whether the number of identical first image data reaches a set value if the current first image data is identical to the previous first image data, and if so, output the control signal to control the processing module to directly output the second image data, and if not, wait for the determination module to continue receiving the first image data until the number of identical first image data reaches a set value.
5. The data processing circuit according to claim 4, wherein the second unit is further configured to count the same number of the first image data with a counter, clear the counter if the current first image data is different from the previous first image data or the same number of the first image data reaches a set value, and output the corresponding control signal.
6. A display device, comprising:
a data processing circuit according to any one of claims 1 to 5 for providing a digital signal corresponding to the first image data, and
And the display panel converts the digital signal into an analog signal and performs luminous display according to the analog signal.
7. A data processing method, comprising:
obtaining a control signal according to the first image data;
processing the first image data to obtain second image data and storing the second image data;
processing the second image data to obtain a digital signal,
Wherein when the first image data is in a first state, the control signal corresponding to the first state is output to directly output the second image data,
Outputting the control signal corresponding to the second state to process the first image data when the first image data is in the second state,
Obtaining the control signal from the first image data includes:
Comparing the first image data of the current line with the first image data of the previous line, if the first image data of the current line is identical with the first image data of the previous line, judging that the first image data of the current line is in the first state, and outputting the control signal corresponding to the first state;
Comparing the current first image data with the previous first image data, if the current first image data is the same as the previous first image data, judging that the current first image data is in the first state, outputting the control signal corresponding to the first state,
After the first image data of the current line is judged to be in the first state, the judgment action is not executed on the single first image data of the current line.
8. The data processing method of claim 7, wherein obtaining the control signal from the first image data further comprises:
And if the first image data of the current row is different from the first image data of the previous row and the current first image data is different from the previous first image data, judging that the current first image data is in the second state, and outputting the control signal corresponding to the second state.
9. The data processing method according to claim 8, wherein if the first image data of a current line is identical to the first image data of a previous line or if the current first image data is identical to the previous first image data, it is judged whether the number of identical first image data reaches a set value,
If yes, outputting the control signal to directly output the second image data, and if no, continuing to receive the first image data until the same number of the first image data reaches a set value.
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