CN120256358A - Signal recognition method, device, electronic device and storage medium - Google Patents
Signal recognition method, device, electronic device and storage medium Download PDFInfo
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- CN120256358A CN120256358A CN202510708170.3A CN202510708170A CN120256358A CN 120256358 A CN120256358 A CN 120256358A CN 202510708170 A CN202510708170 A CN 202510708170A CN 120256358 A CN120256358 A CN 120256358A
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Abstract
The application discloses a signal identification method, a device, electronic equipment and a storage medium, and relates to the technical field of computers, wherein the identification method is applied to a backboard in target equipment, the backboard is connected with a main board through a first connector, the backboard is connected with a switch through a second connector, the first connector is connected with a voltage dividing circuit, the second connector is connected with a grounding resistor, the method comprises the steps of receiving a signal which is output after voltage value conversion is carried out on a main board signal sent by a main board port by the voltage dividing circuit, or receiving a second voltage signal which is output after voltage value conversion is carried out on a switch signal of the switch by the grounding resistor, and determining the voltage value of the voltage signal based on the received voltage signal, so that the source of the voltage signal is identified according to the voltage value. The voltage value is wide in identifiable range relative to the address bit, so that the technical effects of increasing the expandability of the target equipment and improving the performance of the target equipment can be achieved, and the technical problem that the expandability of the current target equipment is limited is solved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a signal identification method, a signal identification device, an electronic device, and a storage medium.
Background
In modern data centers and cloud computing environments, the flexibility and scalability of computer devices has become a key factor in supporting business growth, coping with changes in data processing requirements. However, when the conventional computer device faces diversified application scenarios and continuously updated hardware requirements, a series of technical problems are exposed in hardware resource management, and the overall performance of the computer device is limited.
Currently, computer devices rely on limited address bit resources to distinguish between a motherboard and a switch in hardware resource management. Specifically, different high-low level combinations of address bits are set to map different mainboard ports of the switch and the mainboard, so that hard disk devices connected under the switch and the mainboard are controlled.
However, as the number of switches and ports of a motherboard increases, especially in a high-density server, such a resource allocation method based on fixed address bits has been difficult to meet the requirements, so that the expandability of the computer device is limited, and the performance of the computer device is seriously affected.
Disclosure of Invention
The application provides a signal identification method, a signal identification device, electronic equipment and a storage medium, which are used for at least solving the problem that the expandability of related technology target equipment is limited.
The application provides a signal identification method which is applied to a backboard in target equipment, wherein the backboard is connected with a main board through a first connector, the backboard is connected with a switch through a second connector, the first connector is connected with a voltage dividing circuit, the second connector is connected with a grounding resistor, the signal identification method comprises the steps of receiving voltage signals, wherein the voltage signals comprise first voltage signals or second voltage signals, the first voltage signals are signals which are output through pins of the first connector after voltage value conversion is carried out on main board signals sent by a main board port of the main board through the voltage dividing circuit, the second voltage signals are signals which are output through pins of the second connector after voltage value conversion is carried out on switch signals sent by the grounding resistor, determining voltage values of the voltage signals, and identifying signal sources of the voltage signals according to the voltage values.
The application further provides a signal identification device which comprises a receiving module and an identification module, wherein the receiving module is used for receiving voltage signals, the voltage signals comprise first voltage signals or second voltage signals, the first voltage signals are signals which are output through pins of a first connector after voltage value conversion is carried out on main board signals sent by main board ports of a main board through a voltage dividing circuit, the second voltage signals are signals which are output through pins of a second connector after voltage value conversion is carried out on switch signals sent by a switch through a grounding resistor, and the identification module is used for determining the voltage values of the voltage signals and identifying signal sources of the voltage signals according to the voltage values.
The application also provides electronic equipment which comprises a memory and a processor, wherein the memory is used for storing a computer program, and the processor is used for realizing the steps of any signal identification method when executing the computer program.
The application also provides a computer readable storage medium having a computer program stored therein, wherein the computer program when executed by a processor implements the steps of any of the signal recognition methods described above.
The application also provides a computer program product comprising a computer program which when executed by a processor implements the steps of any of the signal recognition methods described above.
The application is applied to a backboard in target equipment, the backboard is connected with a main board through a first connector, the backboard is connected with a switch through a second connector, the first connector is connected with a voltage dividing circuit, the second connector is connected with a grounding resistor, and further, after voltage value conversion of a main board signal sent by a main board port of the main board is carried out by the voltage dividing circuit, a signal output by a pin of the first connector or a second voltage signal output by a pin of the second connector after voltage value conversion of a switch signal sent by the switch is received by the grounding resistor, and the voltage value of the voltage signal can be determined based on the received voltage signal, namely the first voltage signal or the second voltage signal, so that the source of the voltage signal is identified according to the voltage value. The voltage value is wide in identifiable range relative to the address bit, and has higher flexibility, so that more mainboard ports and switches can be distinguished, the technical problem that the expandability of the current target equipment is limited can be solved, and the technical effects of increasing the flexibility and expandability of the target equipment and improving the performance of the target equipment are achieved.
Drawings
For a clearer description of embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 (a) is a block diagram of a hardware structure of a target device according to an embodiment of the present application;
FIG. 1 (b) is a second block diagram of a hardware structure of a target device according to an embodiment of the present application;
fig. 2 is a flowchart of a signal identifying method according to an embodiment of the present application;
fig. 3 is a schematic diagram of a hardware structure of a target device according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a topology structure of a connection between a motherboard and a back board in the related art;
FIG. 5 is a second schematic diagram of a hardware structure of a target device according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a topology of a switch and backplane connection in the related art;
Fig. 7 is a block diagram of a signal recognition device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present application.
It should be noted that in the description of the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "first," "second," and the like in this specification are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The present application will be further described in detail below with reference to the drawings and detailed description for the purpose of enabling those skilled in the art to better understand the aspects of the present application.
The signal identifying method provided by the embodiment of the application can be executed on a backboard of the target equipment, and the target equipment can be particularly a server equipment or a similar operation device. Specifically, taking a back board running on a server device as an example, fig. 1 (a) is a block diagram of a hardware structure in which a main board is connected to the back board, the back board is connected to the main board through a first connector, the first connector is connected to a voltage dividing circuit, and further the back board can receive a signal output through a pin of the first connector after the voltage dividing circuit converts a voltage value of a main board signal sent by a main board port of the main board. As shown in fig. 1 (b), the hardware structure block diagram of the switch and the back board is connected, the back board is connected with the switch through a second connector, the second connector is connected with a grounding resistor, and then the signal output by a pin of the first connector after the voltage value conversion of the main board signal sent by the main board port of the main board is received by the voltage dividing circuit, or the second voltage signal output by a pin of the second connector after the voltage value conversion of the switch signal sent by the switch is received by the grounding resistor.
The embodiment of the application provides a signal identification method which is applied to a backboard in target equipment, wherein the target equipment can be specifically a server equipment, the backboard is connected with a main board through a first connector, the backboard is connected with a switch through a second connector, the first connector is connected with a voltage division circuit, the second connector is connected with a grounding resistor, and as shown in fig. 2, the method comprises the following steps S202-204:
s202, receiving voltage signals, wherein the voltage signals comprise first voltage signals or second voltage signals, the first voltage signals are signals which are output through pins of the first connector after voltage value conversion of main board signals sent by a main board port of the main board by the voltage dividing circuit, and the second voltage signals are signals which are output through pins of the second connector after voltage value conversion of switch signals sent by the switch by the grounding resistor.
The backboard is an important element for realizing high-speed data transmission and control signal exchange of all functional components of the computer equipment (such as a central processing unit, a GPU (Graphics Processing Unit, a graphic processing unit), a storage device, a network interface and the like). A CPLD (Complex Programmable Logic Device ) may be integrated on the backplane for implementing various signal processing and control logic.
The motherboard integrates multiple components such as a Central Processing Unit (CPU), a memory slot, a PCIe (PCI Express, high-speed serial computer expansion bus standard) slot, a hot plug interface, a baseboard management controller (BMC, (Baseboard Management Controller, baseboard management controller) and the like.
The switch refers to a PCIe SW switch, which can extend the PCIe port number of the motherboard, allowing more devices (e.g., GPU, NVMe (nonvolatile memory host controller interface specification) hard disk) to be connected into the server device. PCIe SW provides the necessary interface expansion, especially when the server device needs to handle a large number of parallel computing tasks or memory requirements.
It will be appreciated that, whether the switch or the port of the motherboard, the backplane may send a voltage signal to the backplane, so that the backplane identifies the source of the signal based on the voltage signal, and further may identify and execute a control instruction (such as a lighting instruction, that is, an instruction for displaying the status of a computer component (such as a hard disk, a drive, etc.) sent by the motherboard or the switch), where the backplane performs a lighting operation based on the lighting instruction, so as to indicate whether the hard disk is in place, is operating normally, or is in a fault condition. The first voltage signal is sent to the back plate through the first connector by the port of the main board when the hard disk is connected with the main board, and the second voltage signal is sent to the back plate through the switch when the hard disk is connected with the switch.
It should be noted that, the voltage signal is used to indicate the source of the signal, that is, through the voltage signal, the back plane can determine whether the signal originates from the port of the motherboard or from the switch. The main board port can send signals to the backboard through the first connector, the voltage dividing circuit connected with the first connector converts the voltage value of the main board signals sent by the main board port, and the signals are output to the backboard through the pins of the first connector. The scene that the motherboard port sends the motherboard signal includes, but is not limited to, equipment in-place identification, fault detection and the like. The device location identifier is that the motherboard may send a motherboard signal periodically to inform the backplane that the hard disk is in place, for example, after a certain hard disk is detected to be ready, the motherboard sends a motherboard signal to the backplane through the motherboard port, and after the backplane identifier is a signal sent by the motherboard port, the subsequent motherboard port may send a first lighting instruction to the backplane, so that the backplane lights an "on line" or "ready" indicator of a slot or a bracket in which the hard disk is located. The fault detection is that when the main board detects that the hard disk fails, the main board can send a signal to inform the back board, and after the back board identifies the main board signal sent by the main board, a second lighting instruction is subsequently sent to the back board, so that the back board lights the fault indicator lamp.
It can be understood that the switch can send a switch signal to the back board through the second connector, and the ground resistor connected with the second connector converts the voltage value of the switch signal sent by the switch, and then outputs the switch signal to the back board through the pin of the second connector. The scenes of the switch sending the switch signals are the same as the main board, and the application is not repeated here.
In some embodiments, the voltage divider circuit may be comprised of two precision resistors (R1 and R2), where R1 is pulled up to a 3v3 power supply and R2 is connected to Ground (GND). According to the resistance value of the resistor and the voltage division principle, when the main board signal passes through the first connector, the voltage value of the main board signal is converted through the voltage division circuit connected with the first connector and then is output. For example, R1 may have a value of 30kΩ, and when R2 has a value of 1000kΩ, i.e. 1mΩ, the theoretical value obtained by converting the calculated voltage is 3.21V.
In other embodiments, the resistance of the second connector connected to the ground resistor R4, R4 may be set to be fixed to 0 Ω, and when the switch signal passes through the second connector, the switch signal is output after voltage value conversion by the ground resistor R4 connected to the second connector, and the level of the switch signal is pulled down to 0V.
In some embodiments, the voltage divider circuit may be connected through either one of pins of the first connector and the second connector. The types of the pins of the first connector and the pins of the second connector can be the same, so that signals can be accurately transmitted according to different connection conditions (namely connection of a main board and a back board and connection of a switch and the back board), and the consistency and compatibility of overall signal transmission are maintained.
S204, determining a voltage value of the voltage signal, and identifying a signal source of the voltage signal according to the voltage value.
It will be appreciated that at the back board end, an ADC (analog-to-digital conversion) pin may be configured, through which a voltage signal sent by the pin of the first connector or the second connector may be received, and analog-to-digital conversion may be performed on the voltage signal, so as to convert the analog voltage signal into a digital signal, thereby obtaining a voltage value.
In an exemplary embodiment, the identifying the signal source of the voltage signal according to the voltage value includes obtaining a pre-built port mapping table, wherein the port mapping table at least includes a plurality of voltage intervals and a target voltage value, the voltage values included in the voltage intervals do not include the target voltage value, matching the voltage value with the voltage intervals and the target voltage value respectively to obtain a matching result, and identifying the signal source of the voltage signal based on the matching result.
It will be appreciated that the port mapping table is the basis for identifying the source of the voltage signal. It contains a plurality of voltage intervals and target voltage values. The voltage intervals correspond to the main board ports, and as the main board comprises a plurality of main board ports, each voltage interval in the voltage intervals corresponds to a respective main board port. The pull-up resistor R1 and the pull-down resistor R2 in the voltage divider circuit are adjustable, and in the case of adjustability, the pull-up resistor R1 and the pull-down resistor R2 may use varistors, digital potentiometers, or other programmable resistive elements that can be adjusted by external control signals or software configurations. And then, after voltage value conversion is carried out on any mainboard port, the voltage value is unique. For example, voltage intervals 3.18V to 3.24V may correspond to motherboard port a, and voltage intervals 4.18V to 5.24V may correspond to motherboard port B.
The target voltage value is set for the switch, and none of the voltage values included in the plurality of voltage intervals includes the target voltage value, that is, any value other than the voltage value included in the voltage interval may be included in the target voltage. Illustratively, the target voltage value is 0.
In some embodiments, the back plane may compare the voltage value with a plurality of voltage intervals, target voltage values in a pre-built port mapping table. If the voltage value falls within a certain voltage interval, the back plane may identify that the signal source belongs to the type of device represented by the voltage interval. If the voltage value is the target voltage value, the back plane may identify that the signal source belongs to the device type represented by the target voltage value.
In the above embodiment, the signal source can be accurately identified by the voltage value, the voltage interval and the target voltage value, so that ambiguity and errors possibly caused by the traditional logic level based identification method are avoided, fewer hardware resources are allowed to be used in a mode of using the voltage value, more ports or devices can be distinguished, and flexibility and expandability of the target device are greatly improved.
In an exemplary embodiment, the identifying the signal source of the voltage signal based on the matching result includes identifying the signal source of the voltage signal as a motherboard port of the motherboard when the matching result is that the voltage value is in any one of the plurality of voltage intervals, and identifying the signal source of the voltage signal as the switch when the matching result is that the voltage value is the target voltage value.
In some embodiments, in the event that a voltage value is detected to fall within any of a plurality of voltage intervals, the backplane may determine that this voltage signal is from a particular motherboard port of the motherboard. For example, if the voltage value is 3.21V and the voltage interval is 3.18V to 3.24V, the cpld can identify that the signal originates from the motherboard port, and further, can determine that the model of the motherboard port is a PE0A/PE0B port.
In other embodiments, if the backplane detects that the voltage is at the target voltage, e.g., 0V, the backplane can identify that the signal originated from the switch, rather than the motherboard port. Since the second connector is connected with the ground resistor R4, the ground resistor R4 can be set to 0Ω, and when the switch signal transmitted from the switch passes through the ground resistor R4, the voltage is converted to 0V.
In the above embodiment, the backplane can accurately and rapidly distinguish whether the signal source is a motherboard port or a switch based on the detection result of the voltage value. In this way, not only can the signal source be identified, but also appropriate control logic can be selected later according to the type of signal source.
The method comprises the steps of S202-S204, wherein the backboard is applied to a backboard in target equipment and is connected with a main board through a first connector, the backboard is connected with a switch through a second connector, the first connector is connected with a voltage dividing circuit, the second connector is connected with a grounding resistor, and then a signal output through a pin of the first connector after voltage value conversion of a main board signal sent by a main board port of the main board is carried out by the voltage dividing circuit or a second voltage signal output through a pin of the second connector after voltage value conversion of a switch signal sent by the switch is carried out by the grounding resistor is received. The voltage value is wide in identifiable range relative to the address bit, and has higher flexibility, so that more mainboard ports and switches can be distinguished, the technical problem that the expandability of the current target equipment is limited can be solved, and the technical effects of increasing the flexibility and expandability of the target equipment and improving the performance of the target equipment are achieved.
In an exemplary embodiment, before the signal source of the voltage signal is identified according to the voltage value, the method further comprises determining, for any one of the main board ports of the main board, a port voltage value matched with the any one of the main board ports, and a switch voltage value matched with the switch, performing error processing on the port voltage value of the any one of the main board ports according to a preset error value, determining a first voltage interval of the any one of the main board ports based on the error-processed port voltage value, constructing a first mapping relation based on the first voltage interval of the any one of the main board ports and a port identification of the any one of the main board ports, and constructing a second mapping relation based on the switch voltage value of the switch and a switch identification of the switch, wherein the port mapping table corresponding to the back board comprises the first mapping relation and the second mapping relation.
It should be noted that, for each motherboard port on the motherboard, a port voltage value matching the motherboard may be determined. The port voltage value is determined by a pull-up resistor R1 and a pull-down resistor R2, the specific value depending on the resistance ratio of R1 and R2. For example, for the PE0A/PE0B port, R1 is set to 30kΩ, R2 is set to 1000kΩ, and the theoretical voltage value obtained by the voltage division calculation is 3.21V.
For the voltage value of the switch, the voltage value of the switch signal is converted into 0V through the ground resistor in the process of retransmitting the switch signal to the back plate. Therefore, the switch voltage value matched to the switch is constant at 0V.
The determined port voltage value may be error processed in consideration of an accuracy error of the resistor (e.g., 1%). This means that the actually detected voltage value can fluctuate within a small range of the theoretical value. For example, for a theoretical voltage value of 3.21V, the actual detection range may be 3.18V to 3.24V.
And defining a first voltage interval for each main board port based on the error processed voltage value. For example, the voltage interval of PE0A/PE0B is 3.18V to 3.24V, which represents the range of voltage variation that CPLD can recognize, to ensure that the signal source can be recognized accurately even under small range of voltage fluctuations.
In some embodiments, the mapping relationship may be constructed between the first voltage interval of each motherboard port and its port identification (e.g., PE0A/PE 0B). Thus, when the backboard detects that the voltage value is within a certain interval, the backboard can identify that the signal source is a corresponding mainboard port according to the first mapping relation. For a switch, a second mapping relationship is constructed in which a switch voltage value (0V) corresponds to a switch identification (e.g., broadcom, microchip, etc.). Thus, when the backboard detects that the voltage value is 0V, the signal source can be rapidly identified as the switch, and the corresponding lighting control logic is ready to be invoked.
In a specific application, the first mapping relationship and the second mapping relationship may be summarized into a port mapping table of the back plate to form a comprehensive identification database. After the back plate detects the voltage value, the back plate can be quickly matched according to the port mapping table. If the voltage value belongs to a first voltage interval of a certain main board port, the back board identifies the voltage value as a main board port signal source, and if the voltage value is 0V, the back board identifies the voltage value as a switch signal source.
In the above embodiment, the back board can directly obtain the port mapping table by pre-establishing the port mapping table, and then, when identifying the signal source, the back board can intelligently and accurately identify the signal source, and then, execute the correct control logic.
In one exemplary embodiment, the determining the port voltage value matched with any one of the main board ports includes determining a pull-up resistance value and a pull-down resistance value corresponding to the any one of the main board ports from a preset resistance value range, wherein the pull-up resistance value of each main board port is different, the pull-down resistance value of each main board port is different, or the pull-up resistance value and the pull-down resistance value of each main board port are different, determining a resistance sum of the pull-up resistance value and the pull-down resistance value, determining a resistance quotient based on the resistance value and the pull-down resistance value, and determining a product of a power supply voltage of the main board and the resistance quotient as the port voltage value matched with the any one of the main board ports.
It should be noted that, from the preset resistance range, a pull-up resistance value and a pull-down resistance value are set for each motherboard port. The choice of these resistances is critical because they determine the final port voltage value. It is noted that these resistances must be guaranteed to be sufficiently accurate, for example, using a 1% accurate resistor, to ensure that the voltage divider circuit is able to stably output the desired voltage value.
The pull-up resistance, the pull-down resistance, or a combination thereof may be different for each motherboard port. This difference in resistance ensures that the voltage value generated by each motherboard port through the voltage divider circuit is unique even at the same power supply voltage, so that the backplane can distinguish between different ports based on the voltage value.
For each selected motherboard port, the sum of its pull-up resistance value and pull-down resistance value, referred to as the sum of the resistance values, is calculated. Further, based on the resistance sum and the pull-down resistance value, a resistance quotient is calculated, and the product of the power supply voltage of the main board and the resistance quotient is determined as a port voltage value matched with any main board port. To cope with the accuracy errors (typically + -1%) that may exist in the resistor, the calculated port voltage values may be error processed. For example, if the calculated voltage value is 3.2V, the final voltage interval is approximately between 3.168V and 3.232V, taking account of ±1% error.
In the above embodiment, by setting the pull-up resistor and the pull-down resistor of each main board port, a unique port voltage value can be generated for each main board port, and this can be used as a basis for identifying the signal source.
In an exemplary embodiment, after the signal source of the voltage signal is identified according to the voltage value, the method further includes determining, based on a port identifier corresponding to the main board port in a port mapping table, a first control instruction sent by the main board port of the main board, analyzing the first control instruction according to an instruction analysis format matched with the port identifier to obtain a first analysis result, and controlling a display state of a display device according to the first analysis result, where different display states of the display device are used to indicate a state of a first hardware device connected to the main board, and the port mapping table includes a first mapping relationship, where the first mapping relationship is constructed by a first voltage interval of any main board port and a port identifier of any main board port.
It should be noted that, after identifying the signal source as the port of the motherboard, the back board may refer to the first mapping relationship stored in the port mapping table to find the port identifier matched with the detected voltage value. The port identification is a unique identifier of the motherboard port and is used to distinguish between different motherboard ports. Once the identity of the motherboard port of the signal source is determined, the backplane may begin to monitor the first control instruction sent by the motherboard port via the bus. The first control instruction may include an operational requirement for hard disk status indicators (e.g., SSDO _loc and SSDO _err).
In some embodiments, the backplane is capable of determining a format of the first control instruction to be parsed based on a port identification corresponding to the motherboard port in the port mapping table. For example, if the identified port identifier is PE0A/PE0B, the back plane may invoke an parsing algorithm corresponding to the port identifier, and the back plane may parse the first control instruction received from the motherboard port according to the parsing algorithm matching the port identifier. Different motherboard ports may use different control instruction formats, and thus the backplane needs to flexibly parse instructions in various formats.
In some embodiments, after the parsing process is finished, the back plane generates a first parsing result that includes a complete understanding of the first control instruction, i.e., how to change the state of the display device to meet the current state or management requirements of the first hardware device (e.g., NVMe hard disk). And calling a preset state control logic to change the state of the display equipment by the backboard according to the instruction parameters in the first analysis result. For example, if the first control command requires an LED lamp (LIGHT EMITTING Diode) at a certain hard disk location to display an error status, the back-plate will send a corresponding signal to trigger the display of this status.
In one particular application, the status of a display device (e.g., status indicator light) may be dynamically adjusted based on signals sent by the back plate. Different display states (such as normal lighting, flashing and extinguishing) can intuitively reflect state information of the first hardware equipment (such as an NVMe hard disk) such as in-place, normal operation, faults and the like, and an intuitive hardware state indication is provided for a user. By changing the display state, the backboard can accurately transmit the state information of the first hardware equipment to the user in real time. For example, when an LED light is normally on, it may indicate that the hard disk is in place and working properly, flashing may mean that the hard disk is reading and writing data, and extinguishing may mean that the hard disk is not inserted or is malfunctioning. The change of the states has an important indication function in the operation and maintenance of the server, is beneficial to quickly positioning the problem disk position and performs targeted fault detection and maintenance work.
In the above embodiment, after the signal source is identified as the main board port, the display state of the display device can be accurately controlled by analyzing the first control instruction received from the main board port according to the instruction analysis format matched with the port identifier, so as to indicate the real-time state of the first hardware device connected with the main board. The process relies on accurate voltage detection, port identification matching in a mapping table, and efficient analysis of control instructions, together forming the core logic for display state control in a server backplane design. Through the mechanism, not only is the visual management of the hardware state enhanced, but also the operation and maintenance efficiency and the user experience are improved.
In an exemplary embodiment, after the signal source of the voltage signal is identified according to the voltage value, the method further includes determining a second control instruction sent by the switch based on a switch identifier corresponding to the switch in a port mapping table in the case that the signal source of the voltage signal is the switch, analyzing the second control instruction according to an instruction analysis format matched with the switch identifier to obtain a second analysis result, and controlling a display state of a display device according to the second analysis result, wherein different display states of the display device are used for indicating states of a second hardware device connected with the switch, and the port mapping table includes a second mapping relationship constructed by the switch voltage value of the switch and the switch identifier of the switch.
It should be noted that, after identifying that the signal source is a switch, the back board may refer to the second mapping relationship stored in the port mapping table to find the switch identifier matched with the detected voltage value. The switch identification is a unique identifier of the switch. Once the switch identification of the signal source is determined, the backplane may begin monitoring the second control instructions sent by the switch over the bus. The second control instruction may include an operational requirement for hard disk status indicators (e.g., ssd1_loc and ssd1_err).
In some embodiments, the backplane is capable of determining a format of the second control instruction to be parsed based on a switch identification corresponding to the switch in the port mapping table. For example, if the identified switch identity is SW, the backplane may invoke a parsing algorithm corresponding to the switch identity, and the backplane may parse the second control instruction received from the switch according to a parsing algorithm matching the switch identity.
In some embodiments, after the parsing process is finished, the back plane generates a second parsing result that includes a complete understanding of the second control instruction, i.e., how to change the state of the display device to meet the current state or management requirements of the second hardware device (e.g., NVMe hard disk). And calling a preset state control logic to change the state of the display equipment by the backboard according to the instruction parameters in the second analysis result. For example, if the second control command requires that an LED lamp (LIGHT EMITTING Diode) at a certain hard disk location display an on-line status, the back-plate will send a corresponding signal to trigger the display of this status.
In the above embodiment, after identifying that the signal source is the switch, the display state of the display device can be accurately controlled by analyzing the second control instruction received from the main board port according to the instruction analysis format matched with the switch identifier, so as to indicate the real-time state of the first hardware device connected with the main board. The process relies on accurate voltage detection, port identification matching in a mapping table, and efficient analysis of control instructions, together forming the core logic for display state control in a server backplane design. Through the mechanism, not only is the visual management of the hardware state enhanced, but also the operation and maintenance efficiency and the user experience are improved.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment.
It will be apparent that the embodiments described above are merely some, but not all, embodiments of the invention. For better understanding of the above method, the following description will explain the above process with reference to the examples, but is not intended to limit the technical solution of the embodiments of the present invention, specifically:
The application aims to solve the key problems in the prior art and aims to optimally upgrade target equipment by innovatively introducing voltage signals. In conventional designs, address discrimination is achieved by means of 4-bit data bits, the 4-bit data bits corresponding to 4 pins, which exposes serious limitations in the face of a continuous increase in the number of ports.
The application provides that the original 4-bit data pin combination can be replaced by only setting 1 address pin. Specifically, in the present application, the CPLD on the backplane will have the ability to detect this particular pin voltage value. Through the accurate voltage variation that detects this pin, CPLD not only can high-efficient discernment go up the source, and clear signal is sourced from the mainboard (specifically can refer to CPU (Central Processing Unit, central processing unit)) or switch on the mainboard), can also accurately establish the mapping relation with the PCIe port of CPU. Based on the method, an intelligent self-adaptive function is realized, the working mode and parameter configuration can be automatically adjusted according to different hardware connection conditions and actual application requirements, the flexibility, the universality and the expandability of the system are greatly improved, and the bottleneck of the prior art in the aspects of address distinction and hardware resource utilization is effectively broken through.
First, from the architecture, the application adjusts the motherboard, the back plane and the switch. Referring to FIG. 3, a schematic topology of the motherboard and the backplane is shown, and FIG. 3 is divided into a Motherboard (MB) and a backplane-101 (BP), wherein the MB includes BMC, CPU, MCIO (Mini Cool Edge Input/Output Connector, mini-cooled edge I/O Connector), i.e. Connector, and other components. MCIO pins, such as the X pin, are connected with a voltage dividing circuit, and the voltage dividing circuit is composed of R1 and R2.
The CPU may be connected to MCIO via vpp_scl (clock signal line) and vpp_sda (clock data line). MCIO may include a motherboard terminal MCIO, i.e., a connector (motherboard terminal) in fig. 3, and a backplane terminal MCIO, i.e., a connector (backplane terminal) in fig. 3, to which signals of the CPU may be transmitted, voltage-value-processed by a voltage-dividing circuit connected via the connector (motherboard terminal), and then sent to the connector (backplane terminal), and then connected to a Complex Programmable Logic Device (CPLD) of the backplane-101 by the connector (backplane terminal).
Specifically, in FIG. 3, R1 may be pulled up to the 3v3 power supply while R2 is grounded, where R2 is set to 1000kΩ, i.e. 1MΩ, by default. Through the accurate resistance value that sets up R1 and R2, utilize the partial pressure principle to realize different voltage output. It is worth emphasizing that R1 and R2 are resistors with high precision of 1%, so that accuracy and stability of a voltage division result are guaranteed, a reliable basis is provided for identifying information through detecting pin voltage later, and performance and reliability of the server device are greatly improved.
At the back-plane end, the data transmission stability and compatibility are ensured by connecting to the CPLD by a connector (back-plane end). Meanwhile, aiming at the key first voltage signal, the first voltage signal is connected into an ADC (analog-to-digital conversion) pin of the CPLD, so that the accurate detection and analysis of the first voltage signal are realized. In the back plane circuit design, the first voltage signal is pulled up to the 3v3 power supply through a 500k omega resistor R3 with an accuracy of 1%. The high-precision resistor is selected, so that stability and accuracy of a voltage value of the first voltage signal are effectively guaranteed, and a solid foundation is laid for information identification of the follow-up CPLD based on voltage detection.
Based on the topological structure constructed by the figure 3, differentiated and efficient operation logic is shown, specifically, 1) the situation that the main board is connected in an uplink manner is shown at the main board end, and the arrangement of R1 and R2 conforms to a specific design rule. According to the parallel voltage division principle of the resistor, when the R1 value is 30kΩ, the actual signal level theoretical value is calculated to be 3.21V. The actual voltage signal level ranges between 3.18V and 3.16V, considering that the resistor has an accuracy error of 1%. In this case, once the CPLD detects a voltage value within this range, it can accurately determine that the upstream port (i.e., the main board port) is PE0A/PE0B. Similarly, when R1 is set to 60kΩ, the theoretical value of the signal level of the actual voltage signal is 3.24V, and the signal level range thereof is 3.10V to 3.16V in consideration of the accuracy error. At this time, when the CPLD detects the voltage value in the range, the upstream port can be identified as PE0C/PE0D. When R1 is set to 400kΩ, the signal level theoretical value of the actual voltage signal is 2.7V, and the signal level range thereof is 2.67V to 2.73V in consideration of the accuracy error. At this time, when the CPLD detects the voltage value in the range, the upstream port can be identified as PE4A/PE4B. And so on, the CPLD can accurately distinguish the corresponding uplink port based on the detected different voltage values.
When the CPLD recognizes that the upstream connection is a motherboard, the Operating System (OS) level may issue lighting instructions (i.e., instruction 1, instruction 2..instruction 4, etc. in fig. 3), common instructions such as ledctrl (a command line tool for managing and controlling LED lights, often used for controlling server devices) or setpci (a command line tool for querying and configuring). At this time, the Basic Input Output System (BIOS) and in-band mechanism recognize the instruction quickly, and send a lighting instruction to 9555 address (backplane CPLD analog 9555 function) of the corresponding CPU port through I 2 C (Inter-INTEGRATED CIRCUIT, integrated circuit interconnect) bus, and the instruction is transmitted in the form of an 8-bit data frame. The backboard CPLD accurately identifies the CPU port corresponding to the uplink lighting requirement, and further performs accurate lighting control operation on the LEDs of the corresponding hard disk.
Referring to fig. 4, a schematic structure of a connection between a motherboard and a back board is shown in a conventional design architecture. Fig. 4 is different from fig. 3 in that in fig. 4, 4-bit address bits are set on the interface design of the backplane and the motherboard, i.e., MCIO (MB Side). At the motherboard end, different combinations of high and low levels can be produced by setting different pull-up or pull-down resistors (typically set to 100 ohms for pull-down and 1 kohm for pull-up) for the 4-bit address bits. In this way, a binding mapping relationship can be established between the CPU port and the different addresses. When a lighting operation is required to be performed on one of the hard disks, a lighting instruction is issued through an Operating System (OS). The instruction will send a lighting instruction to the backplane along the physical link, i.e. the VPP link. After receiving the lighting instruction, the backboard identifies the uplink lighting demand according to the I 2 C address in the VPP bus, and finally lights the indicator lamp corresponding to the disk position.
For the case that the uplink connection is a switch (i.e., PCIe SW), fig. 5 is a schematic topology diagram of the uplink connection PCIe SW, referring to fig. 5, the lighting control function is implemented through a bus (i.e., I 2 C bus), the physical link switch (PCIe SW) of the lighting control function is connected to a connector (motherboard end), and the pins connected to the PCIe SW are consistent with the pins used by the motherboard, so that when different boards are connected, lighting control signals can be accurately transmitted, and the consistency and compatibility of signal transmission of the whole system are maintained. In the switch board design, a second voltage signal is innovatively added. The second voltage signal is connected to GND through resistor R4 on the switch board and in the backplane circuit design is pulled up to 3v3 through a 500kΩ resistor R5 with an accuracy of 1%. The high-precision resistor is selected, so that the stability and accuracy of the voltage value of the second voltage signal are effectively ensured, and a solid foundation is laid for information identification of the follow-up CPLD based on voltage detection. A significant difference from the motherboard is that the resistor R4 on the switch board is set to 0Ω and then this pin is connected to MCIO connectors (motherboard ends) and the connection pins are identical to the motherboard-taken-over pins. Through this unique design for the switch board can work with the mainboard in voltage signal processing, satisfies self specific functional requirement simultaneously, has greatly promoted flexibility and adaptability. The motherboard may design an I 2 C line for switch board management, I 2 C from the BMC to the switch chip on the switch board, where the BMC may obtain the switch model through I 2 C.
When the upstream connection is a switch board, since the voltage signal of the switch board is directly connected to the ground through r4=0Ω, the signal level is pulled down to 0V. Therefore, when the CPLD of the backplane-101 detects that the signal level is 0V, it can be quickly and accurately recognized that the upstream connection is a switch board. In this connection, a lighting instruction is issued at the OS. After the switch recognizes the lighting instruction, the switch further sends lighting data to the backboard CPLD through the bus. It should be noted that, there is a certain difference in the lighting data formats adopted by different PCIE SWs. To this end, the Baseboard Management Controller (BMC) will obtain and identify PCIE SW model information via I 2 C, and then pass this information to the CPLD. Based on this, the CPLD can effectively analyze different PCIE SW lighting data frames, and finally realize lighting control of the hard disk.
Furthermore, in the running process, the application also constructs a perfect and sensitive detection and feedback mechanism for the possible abnormal conditions such as uplink unconnected wires or poor contact. When the upstream is in an unconnected state or poor contact is caused by line aging, connection process defects and the like, the upstream voltage signal is disconnected. At this time, the backplate Complex Programmable Logic Device (CPLD) exhibits a detected signal level of 3.3V based on its accurate signal detection capability. Once this abnormal signal level is detected by the backplane CPLD, the fault feedback process is initiated quickly. Which sends fault alert information to a Baseboard Management Controller (BMC) in an efficient, stable communication protocol via an I 2 C communication link. After receiving the alarm information, the BMC can accurately locate and record the faults, and meanwhile, according to a preset fault processing strategy, corresponding measures are taken, such as triggering a system alarm and generating a detailed fault log, so that operation and maintenance personnel can timely and accurately check and repair the faults, the influence on the system operation caused by abnormal uplink connection is reduced to the greatest extent, and the stability and reliability of the whole server system are powerfully ensured.
Referring to fig. 6, fig. 6 is a schematic topology diagram of an uplink PCIe SW in the related art, and as can be seen in fig. 6, the adopted back plane is BP-102. Usually, a backboard is difficult to simultaneously support both an uplink connection CPU and an uplink connection PCIe SW, so that a plurality of CPLD firmware of different versions are required to be developed and maintained for different uplink connection conditions (such as connection of the CPU or the PCIe SW) and corresponding to different board card material numbers. The process not only consumes a great deal of manpower, material resources and time cost, but also causes great waste of management resources. More importantly, the mode of relying on a plurality of board material number management and control firmware makes the system difficult to realize flexible switching configuration in actual use. When the service requirement changes and the switching between different uplink connection modes is needed, the switching cannot be conveniently and efficiently completed, the flexibility and the adaptability of the system are severely restricted, and the application scene requirement of diversification and dynamic change is difficult to meet. In the practical application scene, the limitation greatly limits the universality and flexibility of the backboard, cannot meet the diversified system configuration requirements, and needs to be solved by innovative technical means.
Therefore, the application reduces the original 4-bit address pins to 1 ADC detection pin, thereby saving 75% of hardware interface resources. The accurate identification of an uplink source (CPU or PCIe SW) is realized by adopting a high-precision voltage division circuit (1% precision resistor) and the ADC detection function of the CPLD. In the application, the same backboard firmware can be adapted to different hardware topological structures, so that the current requirement of developing multi-version firmware is eliminated, and the management and control efficiency of production materials is improved by more than 80%.
The embodiment also provides a signal identifying device, which is used for implementing the above embodiment and the preferred implementation manner, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the modules described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
Fig. 7 is a block diagram of a signal recognition apparatus according to an embodiment of the present application, the apparatus including:
The receiving module 702 is configured to receive a voltage signal, where the voltage signal includes a first voltage signal or a second voltage signal, where the first voltage signal is a signal output through a pin of the first connector after a voltage value of a main board signal sent by a main board port of the main board is converted by a voltage dividing circuit, and the second voltage signal is a signal output through a pin of the second connector after a voltage value of a switch signal sent by the switch is converted by a grounding resistor;
The identifying module 704 is configured to determine a voltage value of the voltage signal, and identify a signal source of the voltage signal according to the voltage value.
The device is applied to a backboard in target equipment, the backboard is connected with a mainboard through a first connector, the backboard is connected with a switch through a second connector, the first connector is connected with a voltage dividing circuit, the second connector is connected with a grounding resistor, and therefore a signal output through a pin of the first connector after voltage value conversion of a mainboard signal sent by a mainboard port of the mainboard by the voltage dividing circuit is received, or a second voltage signal output through a pin of the second connector after voltage value conversion of a switch signal sent by the switch is received by the grounding resistor, and the voltage value of the voltage signal can be determined based on the received voltage signal, namely the first voltage signal or the second voltage signal, so that the source of the voltage signal is identified according to the voltage value. The voltage value is wide in identifiable range relative to the address bit, and has higher flexibility, so that more mainboard ports and switches can be distinguished, the technical problem that the expandability of the current target equipment is limited can be solved, and the technical effects of increasing the flexibility and expandability of the target equipment and improving the performance of the target equipment are achieved.
In an exemplary embodiment, the identifying module 704 is further configured to obtain a pre-constructed port mapping table, where the port mapping table at least includes a plurality of voltage intervals and a target voltage value, the voltage values included in the plurality of voltage intervals do not include the target voltage value, match the voltage values with the plurality of voltage intervals and the target voltage value respectively to obtain a matching result, and identify a signal source of the voltage signal based on the matching result.
In an exemplary embodiment, the identifying module 704 is further configured to identify a signal source of the voltage signal as a motherboard port of the motherboard when the matching result is that the voltage value is in any one of the voltage intervals, and identify the signal source of the voltage signal as the switch when the matching result is that the voltage value is the target voltage value.
In an exemplary embodiment, the device further comprises a construction module, wherein the construction module is used for determining a port voltage value matched with any mainboard port of the mainboard, determining a switch voltage value matched with the switch, performing error processing on the port voltage value of the any mainboard port according to a preset error value, determining a first voltage interval of the any mainboard port based on the error processed port voltage value, constructing a first mapping relation based on the first voltage interval of the any mainboard port and a port identification of the any mainboard port, and constructing a second mapping relation based on the switch voltage value of the switch and the switch identification of the switch, wherein the port mapping table corresponding to the backboard comprises the first mapping relation and the second mapping relation.
In an exemplary embodiment, the building module is further configured to determine a pull-up resistance value and a pull-down resistance value corresponding to the any one of the motherboard ports from a preset resistance value range, where the pull-up resistance value of each motherboard port is different, the pull-down resistance value of each motherboard port is different, or the pull-up resistance value and the pull-down resistance value of each motherboard port are different, determine a resistance sum of the pull-up resistance value and the pull-down resistance value, determine a resistance quotient based on the resistance sum and the pull-down resistance value, and determine a product of a power supply voltage of the motherboard and the resistance quotient as a port voltage value matching the any one motherboard port.
In an exemplary embodiment, the apparatus further includes a control module, where the control module is configured to determine, based on a port identifier corresponding to the port of the motherboard in a port mapping table, a first control instruction sent by the port of the motherboard, and parse the first control instruction according to an instruction parsing format matched with the port identifier, to obtain a first parsing result, and control a display state of a display device according to the first parsing result, where different display states of the display device are used to indicate a state of a first hardware device connected to the motherboard, and the port mapping table includes a first mapping relationship, where the first mapping relationship is constructed by a first voltage interval of any motherboard port and the port identifier of any motherboard port.
In an exemplary embodiment, the control module is further configured to determine, based on a switch identifier corresponding to the switch in a port mapping table, a second control instruction sent by the switch, and parse the second control instruction according to an instruction parsing format matched with the switch identifier to obtain a second parsing result, and control a display state of a display device according to the second parsing result, where different display states of the display device are used to indicate a state of a second hardware device connected to the switch, and the port mapping table includes a second mapping relationship, where the second mapping relationship is constructed by a switch voltage value of the switch and the switch identifier of the switch.
An embodiment of the application also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the signal recognition method embodiments described above.
Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the signal recognition method embodiments described above when run.
In an exemplary embodiment, the computer readable storage medium may include, but is not limited to, a U disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, etc. various media in which a computer program may be stored.
Embodiments of the present application also provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the signal recognition method embodiments described above.
Embodiments of the present application also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which when executed by a processor implements the steps of any of the signal recognition method embodiments described above.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above describes a signal recognition method provided by the application in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
Claims (10)
1. The signal identification method is characterized by being applied to a backboard in target equipment, wherein the backboard is connected with a main board through a first connector, the backboard is connected with a switch through a second connector, the first connector is connected with a voltage division circuit, and the second connector is connected with a grounding resistor, and the method comprises the following steps:
The voltage dividing circuit is used for converting the voltage value of a main board signal sent by a main board port of the main board into a first voltage signal or a second voltage signal, wherein the first voltage signal is a signal output by a pin of the first connector after the voltage value of the main board signal sent by the main board port of the main board is converted by the voltage dividing circuit;
And determining a voltage value of the voltage signal, and identifying a signal source of the voltage signal according to the voltage value.
2. The signal recognition method according to claim 1, wherein the recognizing the signal source of the voltage signal according to the voltage value includes:
Obtaining a pre-constructed port mapping table, wherein the port mapping table at least comprises a plurality of voltage intervals and target voltage values, and the voltage values included in the voltage intervals do not include the target voltage values;
Respectively matching the voltage values with the voltage intervals and the target voltage values to obtain a matching result;
And identifying a signal source of the voltage signal based on the matching result.
3. The signal identifying method according to claim 2, wherein the identifying the signal source of the voltage signal based on the matching result includes:
When the matching result is that the voltage value is in any one of the voltage intervals, identifying a signal source of the voltage signal as a main board port of the main board;
And identifying a signal source of the voltage signal as the switch under the condition that the matching result is that the voltage value is the target voltage value.
4. The signal recognition method according to claim 1, wherein before recognizing a signal source of the voltage signal from the voltage value, the method further comprises:
Determining a port voltage value matched with any main board port of the main board and determining a switch voltage value matched with the switch;
Performing error processing on the port voltage value of any main board port according to a preset error value, and determining a first voltage interval of any main board port based on the port voltage value after error processing;
Constructing a first mapping relation based on a first voltage interval of any main board port and a port identification of any main board port, and constructing a second mapping relation based on a switch voltage value of the switch and a switch identification of the switch, wherein the port mapping table corresponding to the backboard comprises the first mapping relation and the second mapping relation.
5. The signal recognition method according to claim 4, wherein the determining a port voltage value matched to the any one of the main board ports includes:
Determining a pull-up resistance value and a pull-down resistance value corresponding to any main board port from a preset resistance value range, wherein the pull-up resistance value of each main board port is different, the pull-down resistance value of each main board port is different, or the pull-up resistance value and the pull-down resistance value of each main board port are different;
determining a resistance sum of the pull-up resistance value and the pull-down resistance value, and determining a resistance quotient based on the resistance sum and the pull-down resistance value;
and determining the product of the power supply voltage of the mainboard and the resistance quotient as a port voltage value matched with any mainboard port.
6. The signal recognition method according to claim 1, wherein after the signal source of the voltage signal is recognized from the voltage value, the method further comprises:
When the signal source of the voltage signal is a main board port of the main board, determining a first control instruction sent by the main board port of the main board based on a port identification corresponding to the main board port in a port mapping table, and analyzing the first control instruction according to an instruction analysis format matched with the port identification to obtain a first analysis result;
And controlling the display state of the display device according to the first analysis result, wherein different display states of the display device are used for indicating the state of a first hardware device connected with the main board, the port mapping table comprises a first mapping relation, and the first mapping relation is constructed by a first voltage interval of any main board port and a port identifier of any main board port.
7. The signal recognition method according to claim 1, wherein after the signal source of the voltage signal is recognized from the voltage value, the method further comprises:
When the signal source of the voltage signal is the switch, determining a second control instruction sent by the switch based on a switch identifier corresponding to the switch in a port mapping table, and analyzing the second control instruction according to an instruction analysis format matched with the switch identifier to obtain a second analysis result;
and controlling the display state of the display device according to the second analysis result, wherein different display states of the display device are used for indicating the state of a second hardware device connected with the switch, and the port mapping table comprises a second mapping relation which is constructed by the switch voltage value of the switch and the switch identifier of the switch.
8. A signal recognition device, comprising:
The receiving module is used for receiving voltage signals, wherein the voltage signals comprise first voltage signals or second voltage signals, the first voltage signals are signals which are output through pins of a first connector after voltage value conversion is carried out on main board signals sent by a main board port of a main board by a voltage dividing circuit, and the second voltage signals are signals which are output through pins of a second connector after voltage value conversion is carried out on switch signals sent by a switch by a grounding resistor;
and the identification module is used for determining the voltage value of the voltage signal and identifying the signal source of the voltage signal according to the voltage value.
9. An electronic device, comprising:
A memory for storing a computer program;
processor for implementing the steps of the signal recognition method according to any one of claims 1 to 7 when executing said computer program.
10. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when being executed by a processor, implements the steps of the signal recognition method according to any one of claims 1 to 7.
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