CN120255818A

CN120255818A - Data migration method, device, storage medium and electronic device

Info

Publication number: CN120255818A
Application number: CN202510667819.1A
Authority: CN
Inventors: 王瑞; 杨勇军; 王琨; 郭晓琳
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2025-05-23
Filing date: 2025-05-23
Publication date: 2025-07-04
Anticipated expiration: 2045-05-23
Also published as: CN120255818B

Abstract

The embodiment of the disclosure provides a data migration method, a device, a storage medium and electronic equipment, and relates to the technical field of computers, wherein the method comprises the steps of obtaining first information of a solid state disk, wherein the first information is used for reflecting the input and output conditions of the solid state disk; and executing a first migration operation if the solid state disk meets the first condition according to the first information, and executing a second migration operation if the solid state disk does not meet the first condition, wherein the first migration operation comprises executing the migration operation of the cache data, and the second migration operation comprises executing the migration operation of the cache data according to the cache allowance. Therefore, by acquiring the first information of the solid state disk and executing the decision of the migration operation according to the input and output conditions, the intelligent data migration is realized, and the time and mode of the data migration are optimized.

Description

Data migration method and device, storage medium and electronic equipment

Technical Field

The disclosure relates to the field of computer technology, and in particular, to a data migration method, a data migration device, a storage medium and electronic equipment.

Background

As a main storage device in the present era, solid state disk (Solid STATE DISK) is favored by the majority of users due to its advantages of low power consumption, small volume, high shock resistance and the like. With the evolution of NAND (a nonvolatile flash technology) fabrication process, flash memory grains have evolved from the original Single Bit memory cell (SLC, single-LEVEL CELL, i.e., 1 Bit/cell), multi-Bit memory cell (MLC, multi-LEVEL CELL, i.e., 2 Bit/cell), to today's three-Bit memory cell (TLC, trinary-LEVEL CELL, i.e., 3 Bit/cell), four-Bit memory cell (QLC, quad-LEVEL CELL, i.e., 4 Bit/cell), and even five-Bit memory cell (PLC, penta-LEVEL CELL, i.e., 5 Bit/cell). Investigation shows that storage devices based on high-density flash particles have taken up a considerable market share, and currently manufacturers have completed the production of solid-state storage based on QLC particles, leading to a new trend in SSD development.

The higher the storage density of the flash memory particles, the more pronounced the programming effect between the memory cells (cells) is due to the physical characteristics. To solve this problem, a Two-Step programming (TSP) method is proposed in the related art, that is, a fine programming of a next layer Word Line (WL) after a coarse programming is completed. Thus, the TSP method requires that the SSD must retain data of at least one layer (WL). To save costs, most manufacturers use a policy of SLC cache (cache) to reduce the use of dynamic random access memory (DRAM, dynamic Random Access Memory) and to compromise Input-Output (IO) performance. This strategy requires that host (host) data be written to SLC cache first, and then the SLC cached data be migrated to QLC, typically during IO execution or after SLC cache exhaustion. This strategy has two problems:

1. From the perspective of migration time, if data are migrated during IO processing, normal IO bandwidth is occupied, and SSD performance is reduced;

2. From the processing scene, if host continuously initiates a write command, two processes of data migration and IO processing cannot be balanced, or data migration can only be started after SLC cache is exhausted.

Disclosure of Invention

The present disclosure provides a data migration method, apparatus, storage medium, and electronic device, so as to at least solve the above technical problems in the prior art.

The technical scheme of the embodiment of the disclosure is realized as follows:

in a first aspect, an embodiment of the present disclosure provides a data migration method, including:

acquiring first information of a solid state disk, wherein the first information is used for reflecting the input and output conditions of the solid state disk;

if the solid state disk meets the first condition according to the first information, executing a first migration operation; if the solid state disk does not meet the first condition, executing a second migration operation;

The first migration operation comprises the step of executing the migration operation of the cache data, and the second migration operation comprises the step of executing the migration operation of the cache data according to the cache allowance.

In the above scheme, the obtaining the first information of the solid state disk includes:

acquiring the total input and output amount in each statistical period;

And determining the first information according to the total input and output in each statistical period.

In the above scheme, the solid state disk satisfies a first condition, including:

the input and output of the solid state disk are in an idle state in a first statistical period, and the first statistical period is a period before a second statistical period for executing cache data migration.

In the above solution, the executing a first migration operation includes:

And determining a first migration speed, and migrating the cache data of the flash memory to a storage unit of the flash memory according to the first migration speed.

In the above solution, the determining the first migration velocity includes:

Acquiring third information of the solid state disk, and determining a first migration duration according to the third information, wherein the first migration duration is completed The time required by the cache data migration of the parallel pages is longer than or equal to 1;

determining a first migration speed according to the first migration duration;

The third information includes a first read time period, a first programming time period, a second programming time period, the number of parallel Logic Unit Numbers (LUNs), and the size of a Page (Page).

In the above solution, the executing the second migration operation includes:

Acquiring second information, wherein the second information is used for reflecting the buffer margin of the solid state disk;

determining a second migration speed according to the buffer margin;

And migrating the cache data of the flash memory to a storage unit of the flash memory according to the second migration speed.

In the above solution, before the determining the second migration speed according to the buffer margin, the method further includes:

Comparing the buffer margin with a first threshold, and if the buffer margin is smaller than or equal to the first threshold, determining a second migration speed;

And if the buffer margin is larger than the first threshold, determining that data migration is not executed.

In the above solution, the determining the second migration velocity includes:

obtaining the maximum migration speed of the solid state disk, wherein the maximum migration speed corresponds to the recovery speed;

and determining a second migration speed according to the migration speed maximum value, the buffer margin, the first threshold value and the second threshold value.

In the above scheme, the obtaining the maximum value of the migration speed of the solid state disk includes:

And determining the maximum migration speed according to the first writing time, the first recycling time and the first migration speed.

In the scheme, the method is applied to the solid state disk, and the solid state disk comprises a flash memory chip, wherein the flash memory chip comprises a cache part and a storage unit part;

The executing the migration operation of the cache data comprises the steps of migrating the data of the cache part to the storage unit part;

The method for executing the migration operation of the cache data according to the cache allowance comprises the step of migrating the data of the cache part to the storage unit part according to the cache allowance of the cache part.

In the scheme, the buffer memory part comprises SLC buffer memory, and the storage unit part comprises at least one of TLC, QLC, PLC.

In a second aspect, embodiments of the present disclosure provide a data migration apparatus, the apparatus including:

the processing module is used for acquiring first information of the solid state disk, wherein the first information is used for reflecting the input and output conditions of the solid state disk;

the migration module is used for executing a first migration operation if the solid state disk meets the first condition according to the first information, and executing a second migration operation if the solid state disk does not meet the first condition;

In the above scheme, the processing module is configured to obtain the total input/output amount in each statistical period;

In the above scheme, the migration module is configured to determine a first migration speed, and migrate the cache data of the flash memory to the storage unit of the flash memory according to the first migration speed.

In the above solution, the migration module is configured to obtain third information of the solid state disk, determine a first migration duration according to the third information, where the first migration duration is completeThe time required by the cache data migration of the parallel pages is longer than or equal to 1;

determining a first migration speed according to the first migration duration;

In the above scheme, the migration module is configured to obtain second information, where the second information is used to reflect a buffer margin of the solid state disk;

determining a second migration speed according to the buffer margin;

In the above scheme, the migration module is configured to compare the buffer margin with a first threshold before determining a second migration speed according to the buffer margin, and determine the second migration speed if the buffer margin is less than or equal to the first threshold;

In the above scheme, the migration module is configured to obtain a maximum migration speed of the solid state disk, where the maximum migration speed corresponds to the recovery speed;

In the above scheme, the migration module is configured to determine the maximum migration speed according to the first write duration, the first recovery duration, and the first migration speed.

In the scheme, the device is applied to the solid state disk, and the solid state disk comprises a flash memory chip, wherein the flash memory chip comprises a cache part and a storage unit part;

In a third aspect, an embodiment of the present disclosure provides an electronic device comprising at least one processor, and a memory communicatively coupled to the at least one processor, wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform any one of the data migration methods.

In a fourth aspect, embodiments of the present disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform a data migration method according to any one of the above.

The embodiment of the disclosure has the following beneficial effects:

By applying the data migration method, the device, the storage medium and the electronic equipment provided by the embodiment of the disclosure, first information of the solid state disk is obtained, the first information is used for reflecting the input and output conditions of the solid state disk, if the solid state disk meets the first condition according to the first information, first migration operation is executed, and if the solid state disk does not meet the first condition, second migration operation is executed, wherein the first migration operation comprises execution of migration operation of cache data, and the second migration operation comprises execution of migration operation of cache data according to the cache allowance. Therefore, by acquiring the first information of the solid state disk and executing the decision of the migration operation according to the input and output conditions, the intelligent data migration is realized, and the time and mode of the data migration are optimized.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

Fig. 1 is a schematic flow chart of a data migration method according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a second buffer rate variation provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a cache migration process according to an embodiment of the present disclosure;

Fig. 4 is a flow chart of a data migration method provided by an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of a solid state disk according to an embodiment of the present disclosure;

Fig. 6 is a schematic structural diagram of a data migration apparatus according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, features and advantages of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly described in conjunction with the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" are merely distinguishing between similar objects and not representing a particular ordering of the objects, it being understood that the "first/second/third" may be interchanged with a particular order or precedence, if allowed, so that embodiments of the application described herein may be practiced otherwise than as illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.

Before explaining the embodiments of the present disclosure in further detail, terms and terminology involved in the embodiments of the present disclosure are explained, and the terms and terminology involved in the embodiments of the present disclosure are applicable to the following explanation.

Solid State Disks (SSDs), which are hard disks based on flash memory technology, use flash memory cells instead of rotating disks as in conventional mechanical hard disks (HDDs). Advantages of SSDs include faster read and write speeds, low power consumption, and higher shock resistance. The core memory cells of an SSD are typically NAND flash memory, which has different types such as SLC (single bit memory cell), MLC (Multi bit memory cell), TLC (three bit memory cell) and QLC (four bit memory cell).

SLC (Single-LEVEL CELL) is the most basic type of storage, storing one bit of data (0 or 1) per cell. The SLC flash memory has higher durability and faster writing speed, and is suitable for applications with higher performance requirements.

QLC (Quad-LEVEL CELL) is one type of flash memory with the highest storage density, storing 4 bits of data per cell. QLC has a higher storage density than SLC, but a slower writing speed.

A Two-Step programming (TSP) is a technology proposed for high-density flash memory to avoid the mutual interference of cells of WL (word line) of different layers. The meaning of "two-step" is to write to the same WL twice. TSP is generally adopted in two ways, one is that TSP is implemented by using DRAM, but this way is relatively costly, so another is proposed, i.e. data is written into SLC cache first, and then the data of the SLC cache is migrated into QLC, and this migration process usually occurs in the following two cases:

in the IO execution process, when the SSD has idle time, the background writes the cached data into the QLC;

After the SLC buffer is exhausted, when the SLC buffer is filled, new data is written directly into the QLC, and the data in the buffer is migrated to the QLC.

The SLC cache serves as a temporary storage area for storing frequently written data. It enables SSDs to provide high performance in a short time, as SLC writes at a much higher speed than QLC. When the cache is filled, the cached data must be migrated into the QLC, which may cause performance fluctuations.

Therefore, the choice of data migration timing is critical, and in most cases, the migration operation is asynchronous, which means that the process of writing data is not interrupted by the migration process, and if the data is cached too much, the migration operation can slow down the new writing process. However, in the related art, migration generally occurs during the IO execution process or after SLC cache exhaustion, which results in a cliff-like drop phenomenon that inevitably affects the IO performance, and even occurs in the IO performance. Therefore, reasonable scheduling manages data migration and IO processing, and reducing performance fluctuations due to migration is a problem to be solved.

Based on the above, the embodiment of the disclosure provides a data migration method, a device, a storage medium and an electronic apparatus, wherein the first information is used for reflecting the input and output conditions of a solid state disk, the first migration operation is executed if the solid state disk is determined to meet a first condition according to the first information, the second migration operation is executed if the solid state disk is not met the first condition, the first migration operation comprises executing the migration operation of cache data, and the second migration operation comprises executing the migration operation of cache data according to the cache allowance. Therefore, by acquiring the first information of the solid state disk and executing the decision of the migration operation according to the input and output conditions, the intelligent data migration is realized, and the time and mode of the data migration are optimized.

Fig. 1 is a flow chart of a data migration method according to an embodiment of the present disclosure, as shown in fig. 1, where the data migration method includes:

step 101, acquiring first information of a Solid State Disk (SSD), wherein the first information is used for reflecting the Input-Output (IO) condition of the SSD;

step 102, if the solid state disk meets the first condition according to the first information, executing a first migration operation;

The first migration operation is a rapidly started migration operation, data migration is performed at a first migration speed, and the second migration operation is performed at a second migration speed.

The second migration speed and the first migration speed represent migration speeds of data in the cache, the second migration speed is lower than the first migration speed, and in the process of the second migration operation, the second migration speed can change along with the size of the cache allowance, namely, data migration is performed at a variable migration speed (namely, the second migration speed) in the second migration operation.

Therefore, when the solid state disk meets the first condition, data migration is performed at the first rate, and when the first condition is not met, the migration operation of the cache data is performed according to the cache allowance (the migration speed can be adjusted), meanwhile, the cache migration and the IO processing are considered, the IO processing and the cache data migration are balanced, and cliff type drop of IO performance is avoided.

Specifically, the first migration operation or the second migration operation is determined to be executed according to the input and output conditions of the solid state disk, so that excessive occupation of IO bandwidth is avoided, interference to normal IO operation is reduced, and high performance of the SSD is maintained. And when the second migration operation is executed, the data migration speed can be flexibly adjusted according to the buffer margin, and the phenomenon that the IO performance is broken down is prevented.

In some embodiments, the obtaining the first information of the solid state disk includes:

Acquiring the total input and output in a first statistical period;

And determining first information according to the total input and output in the first statistic period.

Here, the total input/output amount represents input and/or output data of the solid state disk in the first statistical period, and whether the IO is in an idle state can be determined according to the first information.

Here, the input and/or output data may include read data and/or write data.

The first statistical period may be a predetermined time window, may be tens to hundreds of milliseconds, or other suitable period of time. During this period, the SSD counts all of the input-output data that it has processed.

Here, by calculating the total amount of input and output of the SSD in the first statistical period, the running condition of the SSD, that is, whether it is in such an idle state, can be obtained. For example, if the total amount of input and output is high, the SSD may be considered to be in a busy state, if the total amount of input and output is low, the SSD may be considered to be in a low load state, and if the total amount of input and output is 0 or near 0, the SSD may be considered to be in an idle state.

The first information may specifically characterize the input/output condition as an idle state or a non-idle state, or may be a busy state, an idle or low load state, or the like.

Here, by acquiring the first information of the solid state disk and evaluating the load condition of the SSD based on the total amount of input and output in the first statistical period, the system can effectively monitor the real-time performance and resource utilization condition of the SSD. The total input and output amount reflects the data processing amount of the SSD in the period, and can intuitively reflect the current IO load so as to judge whether the SSD is in an idle state or not. Based on these data, the system can dynamically adjust IO processing and cache data migration policies to optimize performance under different load conditions.

Specifically, if the IO is detected to be in an idle state, the migration rate of the cache data can be timely improved to improve the cache recovery efficiency and avoid the performance waste caused by idle resources, and under the condition of high load, the system can limit the data migration rate, reduce the occupation of IO bandwidth and prevent the occurrence of abrupt decline of IO performance or excessive consumption of bandwidth.

Therefore, based on dynamic adjustment of IO conditions, performance fluctuation caused by frequent migration in the traditional method can be avoided, and stable operation of SSD under different use scenes can be ensured. By optimizing the resource allocation, the excessive occupation and performance fluctuation of IO bandwidth are avoided, and the efficiency and reliability of SSD are improved.

In some embodiments, the solid state disk satisfies a first condition, including:

Here, by using the time locality principle, it is considered that if the last period (corresponding to the first statistical period) IO is in an idle state, the next period (corresponding to the second statistical period) IO is reasonably considered to have a high probability of being idle, and therefore, whether to initiate background migration (i.e., the first migration operation) of the cache data can be determined based on the state of the last period.

It should be noted that, the next time may refer to the start time of the second statistical period, where the first statistical period and the second statistical period correspond to two time windows and slide with time, so if the first statistical period between the current time is always in an idle state, the current time corresponds to a time point at which data migration can be performed, and these time points continuously form the second statistical period, and it is easy to understand that, from the time point, the second statistical period characterizes a period of time after the first statistical period, and the time length of the second statistical period may be the same as or different from the time length of the first statistical period. For example, if the IO processing is suddenly performed after the cache data migration is performed, the time length of the second statistical period may be smaller than the length of the first statistical period.

Therefore, regularity brought by time locality is utilized, and the resource scheduling efficiency of the system is effectively improved. Specifically, if the input/output is idle during the first statistics period, it means that the load of the SSD is low during this period, and the system has a high probability of continuing to keep the low IO load during the next second statistics period. At this time, by starting the background data migration operation, the idle time can be effectively utilized, and the migration task of the cache data can be completed in advance without affecting the current IO performance. The cache migration mode based on the prediction of the last period state not only can avoid delay caused by waiting for an IO idle state, but also can reasonably process data when the SSD is low in load, improves the overall performance of the system, and can reduce occupation of SSD bandwidth and avoid performance bottleneck by avoiding starting migration operation when the SSD is high in load.

In some embodiments, the performing a first migration operation includes:

Determining a first migration speed;

And migrating the cache data of the flash memory to a storage unit of the flash memory according to the first migration speed.

The cache data of the flash memory refers to data in an SLC cache of the solid state disk, wherein the cache refers to the SLC cache, and is called cache for short;

the memory cell of the flash memory comprises at least one of TLC, QLC, PLC;

migrating cached data of the flash memory to a storage unit of the flash memory refers to migrating data in the SLC cache to a storage unit (such as QLC) of the flash memory.

When normal migration (i.e., the first migration operation) is started, the migration data amount (i.e., migration speed) processed by the SSD in unit time needs to be matched with the current statistical period (recorded as dt), so that the rapid response of burst IO in the next statistical period can be ensured.

In some embodiments, the determining the first migration velocity includes:

determining a first migration speed according to the first migration duration;

The third information includes a first read time period, a first programming time period, a second programming time period, a number of parallel logical unit numbers (LUNs, logical Unit Number), and a size of a Page (Page).

Here, the first read duration is a time required to read one SLC (Single-LEVEL CELL, single-bit memory cell) Page.

The first programming duration is the duration of writing data coarsely to one QLC (four layer cell) page (i.e., the duration of coarsely programming one QLC page).

The second programming time period is the time for finely writing data into one QLC page (i.e. the time for finely programming one QLC page), wherein coarse programming refers to the writing operation of the flash memory, and refers to the fast writing but not completely optimizing process, and fine programming generally means that the data is more precisely optimized in the writing process to improve the storage stability and the long-term service life, so the second programming time period is generally longer than the first programming time period.

The LUN is a logical unit number, which is used to represent a storage unit in the flash memory chip, and in the flash memory, multiple LUNs can generally operate in parallel, so as to improve the performance of the system, so that the number of parallel LUNs (denoted as N, where N is greater than or equal to 1) represents the number of storage units that the flash memory chip supports parallel processing, and generally, the greater N is, the stronger the parallel reading and writing capability of the flash memory.

Pages refer to pages of a flash memory, which are typically fixed memory block sizes (e.g., 4KB, 8KB, etc.), and are the basic unit for performing read and write operations.

The parallel pages refer to N SLC pages corresponding to N parallel LUNs. It should be noted that, since the N parallel pages are on N different LUNs, the LUNs are the smallest units for parallel reading and writing. Thus, the time to migrate one page on one LUN is close to the time to migrate corresponding N parallel pages on N LUNs simultaneously.

The first migration speed represents migration data quantity processed by the solid state disk in unit time.

It should be noted that, the first reading duration, the first programming duration, the second programming duration, the number of parallel logic units, the size of the page, and the like in the third information are determined based on the attribute or the parameter of the solid state disk, and different solid state disks may have different third information, and the following description of the third information is only an example, so as to understand the determination method of the first migration speed.

For example, assume that the time to read one SLC page (i.e., the first read duration) isThe time to coarsely program a QLC page (i.e., the first programming duration) isFinely programming a QLC page for a second programming period of timeThe number of parallel LUNs (i.e. the number of parallel logic units) of the flash memory chip isThe size of each page (i.e., the size of the page) isThen confirm completionThe time taken for the cached data migration of the parallel pages is about;

Then, according to completionTime spent for cache data migration of individual pagesDetermining a first migration rate (i.e., the amount of migration data processed per unit time) as. I.e.When the solid state disk is in an idle state, only data migration operation of migrating data of the cache part to a storage unit part (such as SLC cache to QLC) is performed, and when the solid state disk runs at full load, the maximum speed of data migration (or SLC recovery) is realized.

Here, the first migration velocity is combined in a statistical periodThe data volume of the solid state disk at most can be known to beDt represents the duration of the statistical period;

therefore, when the IO is in an idle state, the solid state disk can be continuously processed at most in the statistical period And the buffer data quantity is large and small so as to ensure the response time of burst IO in the next statistical period.

An application embodiment is provided herein assuming that,,,,,The first migration velocity is aboutThe amount of data migrated in dt=100 ms time is at most about 48MiB.

In some embodiments, the performing a second migration operation includes:

determining a second migration speed according to the buffer margin;

The cache refers to SLC cache, and the cache allowance refers to the residual space of the SLC cache of the solid state disk;

The cache data of the flash memory refers to data in an SLC cache of the solid state disk;

The cache unit of the flash memory may include at least one of TLC, QLC, PLC;

migrating the cache data of the flash memory to the storage unit of the flash memory refers to migrating the data in the SLC cache to the storage unit (such as QLC) of the flash memory.

In actual design, a detection unit can be designed in the solid state disk, and the detection unit is used for detecting the buffer margin of the solid state disk, and judging the buffer (i.e. SLC cache) of the solid state disk in a release state and without writing data according to the detected buffer margin.

Therefore, by monitoring the buffer margin, targeted buffer data migration is executed, so that the buffer space is prevented from being filled, smooth migration of the buffer data is ensured, and the cliff type drop of SSD performance is avoided. According to the method, the data migration strategy is dynamically adjusted, so that the processes of data migration and normal IO processing can be balanced, abrupt starting of data migration when the cache is exhausted is avoided, and risks of unstable system and performance fluctuation are reduced.

In some embodiments, before the determining the second migration speed according to the buffer margin, the method further includes:

In some embodiments, the determining the second migration velocity includes:

The obtaining the maximum value of the migration speed of the solid state disk includes:

Here, the second migration speed characterizes an amount of migration data handled by the solid state disk in a unit time. Since the buffer margin may vary with the migration and/or reclamation process, it will be appreciated that the second migration rate is a variable value.

The first write latency represents the time required to write data to one SLC page;

The first reclamation period represents the time required to reclaim (i.e., complete data movement) the data of the N parallel pages, where, The parallel pages refer to N SLC pages corresponding to N parallel LUNs, and the time required for recovering the data of one page on one LUN is very similar to the time required for simultaneously recovering the data of N parallel pages corresponding to N LUNs, and is equivalent to coincidence;

to implement the second migration operation, a ratio of the data size of the cache migration to the IO data size is determined, for example, it is assumed that a time of writing one SLC page data (i.e., the first writing duration) is The time for recovering N parallel SLC page data (first recovery duration) is;

Determining a maximum value of the migration speed in the second migration operation as。

Specifically, when the buffer margin reaches a second threshold (i.e., nearWhen the SSD is needed to ensure that the recovery rate and the consumption rate of the cache are substantially consistent, so that the margin of the cache is stabilized to smoothly perform subsequent IO, and therefore, the time period of the statistical period (dt) needs to beWherein the maximum value of the amount of the buffered data migrated during the dt period is determined to be. Thus, according toCan determine the maximum value of the migration velocityIs that。

When the buffer margin has just reached the first threshold (i.e. is greater thanAnd is close to) When the SLC data migration is just started, the SLC data volume migrated in the dt time period is almost zero, and the data migration is performed according to the following conditions0) And%,) The two nodes can establish a functional relation between the buffer margin and the buffer data quantity T migrated in dt time to obtain the following relation:;

further determining a second migration velocity based on the relationship

Where T represents the amount of migration data in dt time,Represents the maximum value of the migration data amount in dt time, r represents the buffer margin, and dt represents the duration of the statistical period.

By the method, when mixed processing (namely, the migration of the cache data and the IO processing are carried out simultaneously) is started, the amount of the cache data migrated and the amount of the IO data processed in the time of a statistical period (dt) are reasonably distributed. On one hand, the cliff type drop of IO performance is avoided, the stability is ensured, and on the other hand, the consumption of the cache is delayed, and the subsequent IO can be normally performed.

By designing two thresholdsAndWhen the buffer margin is just smaller than the first threshold valueWhen the SSD starts to perform data migration of the cache in the IO process, the IO performance is slightly reduced, and when the cache margin approaches (here, the approach means that the difference between the cache margin and the second threshold approaches 0), the second thresholdWhen the SSD is used, the recovery rate and the consumption rate of the cache are required to be basically consistent, so that the allowance of the cache is stabilized, and the subsequent IO is smoothly carried out.

From a first threshold valueTo a second threshold valueThe bandwidth occupation proportion caused by the migration of the cache is gradually increased, the IO bandwidth occupation proportion is gradually reduced, and the cliff drop of IO performance is effectively avoided. In addition, during the second migration operation, the system may have the condition that the IO is in an idle state, and at this time, the migration mode may be directly switched to the first migration operation, so as to accelerate the recovery speed of the cache.

FIG. 2 is a schematic diagram of a second buffer rate change according to an embodiment of the disclosure, where the second migration rate is shown in FIG. 2As the buffer margin r changes, when the buffer margin r is larger than the threshold valueWhen the buffer margin r is just smaller than the threshold value, the buffer data migration is not neededWhen SSD starts to carry out data migration of cache in IO process, IO performance is slightly reduced at the moment, and the threshold value is set along with the cache allowance rChanging to a threshold valueIts migration rate also increases from 0 to maximumThe method comprisesThe method is used for ensuring that the recovery rate and the consumption rate of the cache are basically consistent, so that the allowance of the cache is stabilized, and the subsequent IO is smoothly carried out.

Fig. 3 is a schematic diagram of a buffer migration process provided by an embodiment of the present disclosure, where in fig. 3, IO indicates that there is an IO operation and a non-idle state, idle indicates that there is no idle state of the IO operation, reaching a first threshold indicates that a buffer margin exceeds the first threshold in the IO operation and the non-idle state. As shown in FIG. 3, the buffer margin space is sufficient at the beginning, and buffer data migration will not occur when the system accepts IO operation, and when the firmware captures an idle state, the migration speed (speed is that of idle state)) After continuing IO operation for a period of time, the buffer memory allowance is insufficient and reaches a first threshold value [ ]) The second migration operation is started and the system gradually increases the cache data migration speed, at most v _mix, and when the idle state is monitored again, the system continues to be fast (the migration speed is now) And performing data migration.

In some embodiments, the method is applied to a solid state disk, wherein the solid state disk comprises a flash memory chip, a storage unit part and a cache part;

Here, the cache portion includes an SLC cache (cache) and the storage unit portion includes at least one of TLC, QLC, PLC.

Wherein, QLC (Quad-LEVEL CELL) each memory cell (NAND flash memory cell) can store 4 bits of data.

TLC (Triple-LEVEL CELL) is that each memory cell can store 3 bits of data. Compared to QLC, TLC has a slightly higher endurance, but more data is stored per cell, meaning that its storage density is relatively high and performance is also balanced.

PLC (Penta-LEVEL CELL) that each memory cell can store 5 bits of data. The PLC stores more data per cell than the QLC, thereby further improving the storage density.

In the embodiment of the disclosure, the SLC cache is utilized to have higher read-write speed, so that the short-time random read-write performance of the SSD is remarkably improved. After the data is written into the SLC cache, the data is migrated to a storage unit part such as TLC, QLC or PLC according to the cache allowance, so that the utilization of the storage space is optimized, and the writing delay is reduced.

In addition, the dynamic management can also keep the stability of SSD performance, and avoid performance fluctuation caused by buffer full load. Through dynamic management (i.e. based on whether the first condition is met or not and combining with the buffer margin) buffer data migration, the SSD can optimize the storage space while improving the performance, and the cost performance and the use experience of the equipment are improved.

Fig. 4 is a flow chart of a data migration method provided by an embodiment of the present disclosure, where, as shown in fig. 4, the method is applied to a solid state disk, such as the solid state disk shown in fig. 5 below, and the method includes:

step 401, detecting IO state at fixed time;

here, the total input/output (IO) amount of the solid state disk is monitored according to the statistical period, and whether the IO state in the statistical period is an idle state is determined according to the total input/output amount.

Step 402, judging whether the IO is in an idle state, if so, executing a first migration operation, and if not, entering step 403;

here, by using the principle of temporal locality, it is considered that if the IO in the previous statistical period (corresponding to the first statistical period) is in an idle state, it is reasonable to consider that the IO in the next time (corresponding to the second statistical period) is in a high probability of being idle, and the IO state in the next statistical period is estimated based on the fact.

Step 403, detecting a buffer margin;

Here, the cache refers to an SLC cache of the solid state disk, and correspondingly, the cache allowance refers to the remaining space of the SLC cache of the solid state disk;

And step 404, judging whether the buffer margin is early-warned, if the buffer margin is early-warned, executing a second migration operation, and if the buffer margin is not early-warned, normally inputting IO.

Here, two thresholds are provided, respectively denoted asAnd,Greater thanThe buffer margin is recorded as r, and the judging whether the buffer margin is early-warned comprises the step of judging the buffer margin r and a threshold valueAnd threshold valueComparing ifThen execute the second migration operation, ifThe IO processing is normally performed.

Here, performing the second migration operation requires balancing IO performance and cache migration when the cache margin r is just below the threshold valueWhen SSD starts to carry out data migration of cache in IO process, IO performance is slightly reduced at the moment, and when the cache allowance is slowly close to a threshold valueWhen the SSD is used, the recovery rate and the consumption rate of the cache are required to be basically consistent, so that the allowance of the cache is stabilized to smoothly carry out subsequent IO.

A method for determining the second migration velocity is proposed according to @0) And%,) Two nodes are calculated according to the following formula:

;

Where T represents the amount of migration data in dt time, Represents the maximum value of the migration data amount in dt time, r represents the buffer margin, and dt represents the duration of the statistical period. Reference may be made specifically to the description of the method shown in fig. 1, and this is not repeated here.

According to the method provided by the embodiment of the disclosure, the data migration operation is dynamically adjusted according to the input and output conditions of the Solid State Disk (SSD), so that SSD performance is optimized, and cache data migration and IO processing are balanced. Specifically, when SSD meets specific conditions (namely, is in an idle state), data migration is performed at a higher speed, so that SSD performance is fully exerted under a low load condition, and when the load is higher (namely, is in a non-idle state), excessive occupation of resources is avoided by adjusting migration speed according to the buffer margin, and further influence on IO performance is reduced.

Therefore, the cliff type drop of IO performance can be effectively avoided, and stable performance can be ensured under various load conditions. Meanwhile, the dynamic adjustment mode enables the cache data migration and IO processing processes to be mutually coordinated, and performance fluctuation caused by frequent migration in the traditional method is avoided.

In addition, the migration operation is performed according to the buffer margin, so that frequent writing to the hard disk can be reduced, and the writing pressure is reduced. Because the cache migration speed is flexibly adjusted, the method can be better adapted to different load conditions, and the SSD can still keep higher stability and response speed in use.

FIG. 5 is a schematic structural diagram of a solid state disk according to an embodiment of the present disclosure, where, as shown in FIG. 5, the solid state disk includes an IO interface, a cache migration module, and a flash memory;

The IO interface is used for carrying out data transmission with external equipment (such as host).

The buffer memory migration module is responsible for data migration between SLC buffer memory and QLC particles, and can manage the buffer memory space and ensure data migration as required.

Flash memory is a storage medium of a solid state disk, and is a place where data is actually stored.

Specifically, the buffer migration module may include a timer, an IO statistics unit, a buffer margin detection unit, and a buffer migration processing unit;

the timer is used for notifying the IO statistics unit to periodically count IO conditions, and can be set to count once in a statistics unit of tens or hundreds of milliseconds.

The buffer margin monitoring unit is used for monitoring the margin of the SLC buffer (namely the buffer margin) in real time;

The IO statistics unit and the buffer margin monitoring unit respectively output two parameters of the IO condition and the buffer margin in the previous statistics period to the buffer migration processing unit;

The buffer migration processing unit is used for determining the buffer migration data quantity of each period, configuring buffer migration information and the like, and therefore notifying the flash memory end of completing data migration from buffer to QLC particles, namely, the buffer migration processing unit determines how much data should be migrated in each period, namely, determines migration speed according to statistical data (IO (input/output) conditions and buffer allowance) provided by the buffer migration processing unit and configures related buffer migration information. The specific operation performed by the cache migration processing unit may refer to the method shown in fig. 1, and will not be described herein.

Fig. 6 is a schematic structural diagram of a data migration apparatus according to an embodiment of the present disclosure, where, as shown in fig. 6, the apparatus includes:

In some embodiments, the processing module is configured to obtain a total input/output amount in each statistical period;

In some embodiments, the migration module is configured to determine a first migration speed, and migrate the cache data of the flash memory to the storage unit of the flash memory according to the first migration speed.

In some embodiments, the migration module is configured to obtain third information of the solid state disk, determine a first migration duration according to the third information, where the first migration duration is completeThe time required by the cache data migration of the parallel pages is longer than or equal to 1;

determining a first migration speed according to the first migration duration;

In some embodiments, the migration module is configured to obtain second information, where the second information is used to reflect a buffer margin of the solid state disk;

determining a second migration speed according to the buffer margin;

In some embodiments, the migration module is configured to compare the buffer margin with a first threshold before determining a second migration speed according to the buffer margin, and determine the second migration speed if the buffer margin is less than or equal to the first threshold;

In some embodiments, the migration module is configured to obtain a maximum migration speed of the solid state disk, where the maximum migration speed corresponds to a recovery speed;

In some embodiments, the migration module is configured to determine the migration velocity maximum value according to a first write duration, a first recovery duration, and a first migration velocity.

In some embodiments, the device is applied to a solid state disk, wherein the solid state disk comprises a flash memory chip, a storage unit part and a storage unit part;

In some embodiments, the cache portion comprises an SLC cache and the memory cell portion comprises at least one of TLC, QLC, PLC.

It will be appreciated that, when implementing the corresponding data migration method, the data migration apparatus provided in the foregoing embodiment may allocate the processes to be performed by different program modules according to needs, so as to complete all or part of the processes described above. In addition, the apparatus provided in the foregoing embodiments and the embodiments of the corresponding methods belong to the same concept, and specific implementation processes of the apparatus and the embodiments of the methods are detailed in the method embodiments, which are not described herein again.

Embodiments of the present application provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from a computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to perform a data migration method.

Embodiments of the present application provide a computer readable storage medium having stored therein executable instructions that, when executed by a processor, cause the processor to perform the data migration method provided by the embodiments of the present application.

In some embodiments, the computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM, or various devices including one or any combination of the above.

In some embodiments, the executable instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

As an example, executable instructions may, but need not, correspond to files in a file system, may be stored as part of a file that holds other programs or data, such as in one or more scripts in a hypertext markup language (HTML, hyper Text Markup Language) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).

As an example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or distributed across multiple sites and interconnected by a communication network.

Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure, and as shown in fig. 7, the electronic device 70 includes a processor 701, and a memory 702 communicatively connected to the processor 701, where the memory 702 stores instructions executable by the processor 701. The instructions are executed by the processor 701 to enable the processor 701 to perform:

The method comprises the steps of obtaining first information of a solid state disk, wherein the first information is used for reflecting the input and output conditions of the solid state disk, executing first migration operation if the solid state disk is determined to meet a first condition according to the first information, and executing second migration operation if the solid state disk is not determined to meet the first condition, wherein the first migration operation comprises executing the migration operation of cache data, and the second migration operation comprises executing the migration operation of the cache data according to the cache allowance.

The electronic device provided in the foregoing embodiments and the embodiments of the corresponding data migration method belong to the same concept, and specific implementation processes of the electronic device are detailed in the method embodiments, which are not described herein again.

In practice, the electronic device 70 may further comprise at least one network interface 703. The various components in the electronic device 70 are coupled together by a bus system 704. It is appreciated that bus system 704 is used to enable connected communications between these components. The bus system 704 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration, the various buses are labeled as bus system 704 in fig. 7. The number of the processors 701 may be at least one, and the number of the memories 702 may be at least one. The network interface 703 is used for wired or wireless communication between the electronic device 70 and other devices.

The memory 702 in the disclosed embodiments is used to store various types of data to support the operation of the electronic device 70.

The methods disclosed in the embodiments of the present disclosure may be applied to the processor 701 or implemented by the processor 701. The processor 701 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 701 or by instructions in the form of software. The Processor 701 may be a general purpose Processor, a digital signal Processor (DSP, diGital Signal Processor), or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 701 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present disclosure. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present disclosure may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in the decoded processor. The software modules may be located in a storage medium having memory 702, and the processor 701 reads information in the memory 702, in combination with hardware, to perform the steps of the data migration method described above.

In some embodiments, the electronic device 70 may be implemented by one or more Application Specific Integrated Circuits (ASICs), DSPs, programmable logic devices (PLDs, programmable Logic Device), complex Programmable logic devices (CPLDs, complex Programmable Logic Device), field-Programmable gate arrays (FPGAs), general purpose processors, controllers, microcontrollers (MCUs, micro Controller Unit), microprocessors (microprocessors), or other electronic elements for performing the foregoing methods.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

In the above description reference has been made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the present disclosure is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

It should be understood that, in various embodiments of the present disclosure, the size of the sequence number of each implementation process does not mean that the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A data migration method, characterized in that the method comprises:

Acquire first information of the solid state hard disk, where the first information is used to reflect the input and output status of the solid state hard disk;

If it is determined according to the first information that the solid-state hard disk meets the first condition, a first migration operation is performed; if the solid-state hard disk does not meet the first condition, a second migration operation is performed;

The first migration operation includes: performing a migration operation of cache data; and the second migration operation includes: performing a migration operation of cache data according to a cache margin.

2. The method according to claim 1, wherein obtaining the first information of the solid state drive comprises:

Get the total input and output in each statistical period;

The first information is determined according to the total input and output amount in each statistical period.

3. The method according to claim 2, wherein the solid state drive satisfies the first condition, comprising:

The input and output of the solid state hard disk is in an idle state in a first statistical period; the first statistical period is a period before a second statistical period in which cache data migration is to be performed.

4. The method according to claim 1, wherein the performing the first migration operation comprises:

A first migration speed is determined, and cache data of the flash memory is migrated to a storage unit of the flash memory according to the first migration speed.

5. The method according to claim 4, characterized in that the determining the first migration speed comprises:

Obtain third information of the solid state drive, and determine a first migration duration according to the third information, wherein the first migration duration is the duration of completing The time required to migrate cache data of parallel pages; N is greater than or equal to 1;

determining a first migration speed according to the first migration duration;

The third information includes: a first reading time, a first programming time, a second programming time, the number of parallel logical unit numbers LUN and the size of a page.

6. The method according to claim 1, wherein the performing the second migration operation comprises:

Acquire second information, where the second information is used to reflect the cache margin of the solid state drive;

determining a second migration speed according to the cache margin;

The cache data of the flash memory is migrated to the storage unit of the flash memory according to the second migration speed.

7. The method according to claim 6, characterized in that before determining the second migration speed according to the cache margin, the method further comprises:

comparing the cache margin and a first threshold, and determining a second migration speed if the cache margin is less than or equal to the first threshold;

If the cache margin is greater than the first threshold, it is determined not to perform data migration.

8. The method according to claim 6, wherein determining the second migration speed comprises:

Obtaining a maximum migration speed of the solid state drive, wherein the maximum migration speed corresponds to a recycling speed;

A second migration speed is determined according to the maximum migration speed, the buffer margin, the first threshold and the second threshold.

9. The method according to claim 8, wherein obtaining the maximum migration speed of the solid state drive comprises:

The maximum migration speed is determined according to the first writing duration, the first recycling duration, and the first migration speed.

10. The method according to claim 1, characterized in that the method is applied to a solid state drive, the solid state drive comprises: a flash memory chip; the flash memory chip comprises: a cache part and a storage unit part;

The performing of the cache data migration operation includes: migrating the data of the cache portion to the storage unit portion;

The performing the cache data migration operation according to the cache margin includes: migrating the data of the cache part to the storage unit part according to the cache margin of the cache part.

11. The method according to claim 10 is characterized in that the cache part includes a single-bit storage unit SLC cache; the storage unit part includes at least one of the following: a three-bit storage unit TLC, a four-bit storage unit QLC, and a five-bit storage unit PLC.

12. A data migration device, characterized in that the device comprises:

A processing module, used for acquiring first information of the solid state hard disk, where the first information is used for reflecting the input and output status of the solid state hard disk;

a migration module, configured to execute a first migration operation if it is determined according to the first information that the solid-state hard disk meets a first condition; and execute a second migration operation if the solid-state hard disk does not meet the first condition;

13. The device according to claim 12, characterized in that the device is applied to a solid state hard disk, the solid state hard disk comprises: a flash memory chip; the flash memory chip comprises: a cache part and a storage unit part;

The performing the migration operation of cache data according to the cache margin includes: migrating the data of the cache part to the storage unit part according to the cache margin of the cache part;

The cache portion includes an SLC cache; the storage unit portion includes at least one of the following: TLC, QLC, and PLC.

14. An electronic device, comprising: at least one processor; and a memory connected to the at least one processor in communication; wherein:

The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

15. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 11.