CN120201816A

CN120201816A - A solar cell and a method for preparing the same

Info

Publication number: CN120201816A
Application number: CN202510678754.0A
Authority: CN
Inventors: 刘楦
Original assignee: Yangzhou Ates Solar Cell Co ltd; Jiaxing Canadian Solar Technology Research Institute
Current assignee: Yangzhou Ates Solar Cell Co ltd; Jiaxing Canadian Solar Technology Research Institute
Priority date: 2025-05-26
Filing date: 2025-05-26
Publication date: 2025-06-24

Abstract

The present application discloses a solar cell and a preparation method thereof, belonging to the field of photovoltaic technology. The solar cell comprises: a silicon substrate having a front surface and a back surface arranged opposite to each other, a first region and a second region arranged in a staggered manner and without a gap along a first direction, the thickness of the silicon substrate located in the first region is greater than the thickness of the silicon substrate located in the second region; a first doping structure is arranged on the back surface and located in the first region, comprising a first tunneling layer and a first doped crystalline silicon layer stacked in sequence; a second doping structure is arranged on the back surface and located in the second region; a side of the first tunneling layer facing the silicon substrate is spaced apart from a side of the second doping structure away from the silicon substrate along a second direction. The solar cell does not require laser etching of the Gap region, can increase the area of the photoelectric conversion region, reduce the requirements for graphic accuracy, improve the problem of metallization printing offset short circuit, and at the same time realize the effective spacing of different doping structures, effectively preventing short circuits.

Description

Solar cell and preparation method thereof

Technical Field

The application belongs to the technical field of photovoltaics, and particularly relates to a solar cell and a preparation method thereof.

Background

The Back Contact (BC) type battery has the advantages that a P type doping structure (called a P region), an N type doping structure (called an N region for short) and an electrode are arranged on the Back surface, the front surface is free of electrode shielding, the absorption of sunlight is greatly improved, and the battery efficiency is high.

The existing BC battery generally adopts a design that an isolation region (Gap region) is arranged at the junction of a P region and an N region, and the Gap region is used for preventing the P region and the N region from being contacted to cause short circuit failure. The Gap region is mainly prepared by a laser process, the patterning precision requirement is high, the alignment of a subsequent metallization process is influenced, the battery performance attenuation is easy to occur, and if the Gap region has a communication defect, the battery short circuit failure is also caused.

Disclosure of Invention

The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the solar cell and the preparation method thereof provided by the application can reduce the patterning precision requirement, improve the metallization printing offset short circuit problem, realize the effective intervals of different doping structures and prevent short circuits.

In a first aspect, the present application provides a solar cell comprising:

The silicon substrate is provided with a front surface and a back surface which are oppositely arranged, a first area and a second area which are staggered and have no interval are arranged along a first direction, the first direction is a direction parallel to the plane of the silicon substrate, and the thickness of the silicon substrate positioned in the first area is larger than that of the silicon substrate positioned in the second area;

The first doped structure is arranged on the back surface and positioned in the first region and comprises a first tunneling layer and a first doped crystal silicon layer which are sequentially stacked, and the first tunneling layer is in contact with the silicon substrate;

The second doping structure is arranged on the back surface and is positioned in the second region;

The first tunneling layer and the second tunneling layer are spaced apart from one surface of the silicon substrate facing away from the second doping structure along a second direction, the second direction is perpendicular to a plane of the silicon substrate, and doping types of the first doping structure and the second doping structure are opposite.

According to the solar cell, the first area and the second area which are staggered and have no interval are arranged along the first direction, two doping structures with opposite doping types are respectively arranged, the Gap area is not required to be etched by laser, the area of the photoelectric conversion area can be increased, the patterning precision requirement can be reduced, the problem of offset short circuit of metallization printing is improved, the thickness of the silicon substrate positioned in the first area is larger than that of the silicon substrate positioned in the second area, the first tunneling layer positioned at a thicker position separates the first doping crystal silicon layer from the second doping structure along the second direction, the effective interval of different doping structures is realized, and the short circuit is effectively prevented.

According to one embodiment of the present application, the second doped structure includes a second tunneling layer and a second doped crystalline silicon layer sequentially stacked, the second tunneling layer being in contact with the silicon substrate;

One surface of the first tunneling layer facing the silicon substrate is spaced apart from one surface of the second doped crystalline silicon layer facing away from the silicon substrate along the second direction.

According to one embodiment of the application, the distance between the side of the first tunneling layer facing the silicon substrate and the side of the second doped crystalline silicon layer facing away from the silicon substrate in the second direction is 10 μm-15 μm.

According to one embodiment of the application, the first tunneling layer and the second tunneling layer are integrally provided.

According to one embodiment of the application, the second doping structure is a second diffusion layer formed by diffusing a doping source from the back surface to the front surface in the second direction of the silicon substrate.

According to one embodiment of the application, the distance between the side of the first tunneling layer facing the silicon substrate and the side of the second diffusion layer facing away from the front surface is 10 μm-15 μm in the second direction.

According to one embodiment of the application, the area of the first region is greater than or equal to the area of the second region.

In a second aspect, the present application provides a method for manufacturing a solar cell, the method comprising:

Providing a silicon substrate, wherein the silicon substrate is provided with a front surface and a back surface which are oppositely arranged, the silicon substrate is provided with first areas and second areas which are staggered and have no interval along a first direction, and the first direction is a direction parallel to a plane where the silicon substrate is positioned;

Forming a first doping structure on the back surface, wherein the first doping structure comprises a first tunneling layer and a first doped crystal silicon layer which are sequentially stacked, and the first tunneling layer is in contact with the silicon substrate;

And removing the first doping structure and part of the silicon substrate in the second region of the back surface, and forming a second doping structure with the doping type opposite to that of the first doping structure in the second region, wherein one surface of the first tunneling layer facing the silicon substrate and one surface of the second doping structure facing away from the silicon substrate are spaced along a second direction, and the second direction is a direction perpendicular to the plane of the silicon substrate.

According to the preparation method of the solar cell, the first area and the second area which are staggered and have no interval are arranged along the first direction, two doping structures with opposite doping types are prepared on the back surface of the silicon substrate, the Gap area is not required to be etched by laser, the area of the photoelectric conversion area can be increased, the requirement on patterning precision can be reduced, the problem of offset short circuit of metallization printing is solved, the thickness of the silicon substrate positioned in the first area is larger than that of the silicon substrate positioned in the second area, the first tunneling layer positioned at the thicker position separates the first doping crystal silicon layer from the second doping structure along the second direction, the effective interval of different doping structures is realized, the process is simple, and the short circuit can be effectively prevented.

Forming a first doping structure on the back surface, including:

forming a first tunneling layer, a first doped crystalline silicon layer and a first mask layer which are sequentially stacked, wherein the first mask layer is contacted with one surface of the first doped crystalline silicon layer, which is away from the first tunneling layer;

removing the first doping structure and a part of the silicon substrate in the second region of the back surface, and forming a second doping structure with opposite doping type to the first doping structure in the second region, wherein the method comprises the following steps:

Removing the first mask layer in the second area of the back surface by using laser;

Etching the first doped crystalline silicon layer, the first tunneling layer and a part of the silicon substrate in the second region;

forming a second tunneling layer, a second doped crystalline silicon layer and a second mask layer which are sequentially stacked on the back surface, wherein the second mask layer is contacted with one surface of the second doped crystalline silicon layer, which is away from the second tunneling layer;

Removing the second mask layer in the first region of the back surface by using laser;

Etching the second doped crystalline silicon layer and the second tunneling layer in the first region;

the first mask layer in the first region and the second mask layer in the second region are etched.

According to one embodiment of the application, etching the first doped crystalline silicon layer, the first tunneling layer and a portion of the silicon substrate in the second region comprises:

etching the first doped crystalline silicon layer and the first tunneling layer in the second region;

And etching the silicon substrate with the thickness of 13-18 mu m from the back surface to the front surface along the second direction, so that the distance between the surface of the first tunneling layer facing the silicon substrate and the surface of the second doped crystal silicon layer facing away from the silicon substrate along the second direction is 10-15 mu m.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:

Fig. 1 is a schematic structural diagram of a solar cell according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a solar cell according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a solar cell according to an embodiment of the present application;

fig. 4 is a schematic flow chart of a method for manufacturing a solar cell according to an embodiment of the present application;

fig. 5 is a schematic diagram of an intermediate structure of a solar cell according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a second intermediate structure of a solar cell according to an embodiment of the present application;

FIG. 7 is a third schematic diagram of an intermediate structure of a solar cell according to an embodiment of the present application;

FIG. 8 is a schematic diagram of an intermediate structure of a solar cell according to an embodiment of the present application;

FIG. 9 is a schematic diagram showing an intermediate structure of a solar cell according to an embodiment of the present application;

fig. 10 is a schematic diagram showing an intermediate structure of a solar cell according to an embodiment of the present application.

Reference numerals:

the silicon substrate 100, the first region 110, the second region 120,

The first doped structure 210, the first tunneling layer 211, the first doped crystalline silicon layer 212, the first mask layer 213,

The second doping structure 220, the second tunneling layer 221, the second doped crystalline silicon layer 222, the second mask layer 223, the second diffusion layer 224,

A passivation layer 310, an anti-reflection layer 320, a first electrode structure 410, a second electrode structure 420.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.

The solar cell and the method of manufacturing the solar cell according to the embodiments of the present application are described below with reference to fig. 1 to 10.

As shown in fig. 1, the solar cell includes a silicon substrate 100, a first doping structure 210, and a second doping structure 220.

The silicon substrate 100 has a front surface and a back surface, which are disposed opposite to each other, the front surface being a light receiving surface of the solar cell facing the light source, and the back surface being a backlight surface of the solar cell.

In actual implementation, the silicon substrate 100 may be an N-type silicon wafer or a P-type silicon wafer.

In this embodiment, the first doping structure 210 and the second doping structure 220 are disposed on the back surface of the silicon substrate 100.

The silicon substrate 100 is provided with first regions 110 and second regions 120 which are staggered and have no space along the first direction D1, the first doping structure 210 is disposed on the back surface and located in the first region 110, and the second doping structure 220 is disposed on the back surface and located in the second region 120.

The first direction D1 is a direction parallel to the plane of the silicon substrate 100.

It can be appreciated that the doping types of the first doping structure 210 and the second doping structure 220 are opposite, one of the first doping structure 210 and the second doping structure 220 forms a conductive region (P region) with dominant holes, which is responsible for collecting photo-generated holes and transmitting the photo-generated holes to the corresponding electrode, and the other of the first doping structure 210 and the second doping structure 220 forms a conductive region (N region) with dominant electrons, which is used for collecting photo-generated electrons and transmitting the photo-generated electrons to the corresponding electrode, and efficient separation and collection of photo-generated carriers are achieved through doping structures with different doping types.

For example, the first doping structure 210 may be a P region doped with boron as a doping source, and the second doping structure 220 may be an N region doped with phosphorus as a doping source.

For another example, the first doped structure 210 may be an N region doped with phosphorus as a dopant source, and the second doped structure 220 may be a P region doped with boron as a dopant source.

In this embodiment, the first region 110 is provided with a first doping structure 210, the second region 120 is provided with a second doping structure 220, the first region 110 and the second region 120 are staggered along the first direction D1, and directional migration of photo-generated carriers is realized by a built-in electric field, so as to form a photo-current.

It can be appreciated that the photo-generated current formed by the first doping structure 210 and the second doping structure 220 is collected by the metal electrode, the first electrode structure 410 is in contact with the first doping structure 210, and the second electrode structure 420 is in contact with the second doping structure 220, so as to achieve selective separation of electrons and holes, and lead out the photo-generated current.

The first electrode structure 410 and the second electrode structure 420 may be thin gate, main gate, or other gate line structures.

In practical implementation, the solar cell may further be provided with a passivation layer 310, an anti-reflection layer 320, and other structures to reduce carrier recombination and increase light absorption, and on the back surface, a first electrode structure 410 penetrates the passivation layer 310 and the anti-reflection layer 320 to be in contact with the first doped structure 210, and a second electrode structure 420 penetrates the passivation layer 310 and the anti-reflection layer 320 to be in contact with the second doped structure 220.

The passivation layer 310 may be made of aluminum oxide (Al ₂O₃), the thickness of the passivation layer 310 may be 2nm to 10nm, the anti-reflection layer 320 may be a single-layer structure or a multi-layer structure of a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, and a silicon oxynitride (SiOxNy) layer, and the thickness of the anti-reflection layer 320 may be 10nm to 100nm.

Note that, there is no space between the adjacent first region 110 and second region 120, and the first region 110 and second region 120 are contiguous, i.e., there is no isolation region (i.e., gap region in the related art) between the first region 110 and the second region 120.

In this embodiment, the thickness of the silicon substrate 100 in the first region 110 is greater than the thickness of the silicon substrate 100 in the second region 120, i.e. the silicon substrate 100 in the first region 110 is thicker than the silicon substrate 100 in the second region 120, the first doped structure 210 formed in the first region 110 and the second doped structure 220 formed in the second region 120 form a height difference in the second direction D2, and the first region 110 of the solar cell is thicker than the second region 120.

The second direction D2 is a direction perpendicular to the plane of the silicon substrate 100.

In actual implementation, the second direction D2 may also be referred to as a thickness direction of the silicon substrate 100, and the first direction D1 may be perpendicular to the second direction D2, where "perpendicular" includes not only 90 degrees in absolute sense but also other approximately perpendicular cases similar to 90 degrees.

In this embodiment, the first doping structure 210 includes a first tunneling layer 211 and a first doped crystalline silicon layer 212 sequentially stacked, the first tunneling layer 211 being in contact with the silicon substrate 100.

It is appreciated that the first tunneling layer 211 and the first doped crystalline silicon layer 212 may form a passivation contact structure, which helps to reduce carrier recombination and contact recombination loss.

The first tunneling layer 211 is a hierarchical structure in contact with the silicon substrate 100, so that selective transmission of carriers can be realized, the metal electrode is isolated from the silicon substrate 100, and recombination loss of carriers is reduced.

In actual implementation, the first tunneling layer 211 may be made of silicon oxide (SiO 2).

In this embodiment, the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doping structure 220 facing away from the silicon substrate 100 are spaced apart along the second direction D2, that is, the first doping structure 210 and the second doping structure 220 are spaced apart along the second direction D2, and the first doped crystalline silicon layer 212 and the second doping structure 220 can be spaced apart by the first tunneling layer 211, so that the short circuit caused by the contact of doping structures with different doping types is prevented, and the efficient separation and collection of photo-generated carriers are realized.

A specific embodiment is described below.

As shown in fig. 1, the solar cell includes a silicon substrate 100, a first doping structure 210 and a second doping structure 220, the first doping structure 210 and the second doping structure 220 are disposed on the back surface of the silicon substrate 100, and a first region 110 and a second region 120 which are staggered and have no space are disposed along a first direction D1, the first doping structure 210 is disposed on the back surface and is located in the first region 110, and the second doping structure 220 is disposed on the back surface and is located in the second region 120.

The adjacent first area 110 and second area 120 have no interval, so that the area of a photoelectric conversion area of the solar cell can be effectively increased, a Gap area is not required to be etched by laser in the cell preparation process, the patterning precision requirement can be reduced, and the offset short circuit problem caused by overhigh precision requirement in the subsequent metallization printing process is solved.

The thickness of the silicon substrate 100 located in the first region 110 is greater than the thickness of the silicon substrate 100 located in the second region 120, and the first doping structure 210 includes a first tunneling layer 211 and a first doped crystalline silicon layer 212 stacked in sequence, the side of the first tunneling layer 211 facing the silicon substrate 100 being spaced apart from the side of the second doping structure 220 facing away from the silicon substrate 100 along the second direction D2.

The first regions 110 and the second regions 120 are staggered and have no space along the first direction D1, so that the photoelectric conversion region area of the solar cell is effectively increased, the preparation precision requirement is reduced, and the first tunneling layer 211 separates the first doped crystalline silicon layer 212 from the second doped structure 220 along the second direction D2, so that short circuit caused by contact of doped structures with different doping types can be prevented.

In the related technology, the BC battery generally adopts the design that an isolation region (Gap region) is arranged at the junction of a P region and an N region through laser slotting, the patterning precision requirement of a laser process is higher, the alignment of a subsequent metallization process is influenced, the performance attenuation of the battery is easy to be caused, if the Gap region has a communication defect, the battery is also in short circuit failure, in addition, a photo-generated carrier cannot be generated in the Gap region, the effective area of the battery is reduced due to the Gap region, and the photoelectric conversion efficiency is limited.

In the embodiment of the application, by designing the first region 110 and the second region 120 which are staggered along the first direction D1 and have no space, and arranging the first doping structure 210 and the second doping structure 220, the adjacent first region 110 and second region 120 have no space, so that the photoelectric conversion area of the solar cell can be effectively increased, the photoelectric conversion efficiency is improved, the Gap region is not required to be etched in the cell preparation process, the requirement on patterning precision can be reduced, the offset short circuit problem caused by excessively high precision requirement in the subsequent metallization printing process is improved, the thickness of the silicon substrate 100 positioned in the first region 110 is larger than the thickness of the silicon substrate 100 positioned in the second region 120, the thickness distribution with obvious difference in the solar cell is formed, and the first tunneling layer 211 positioned at the thicker part of the cell is matched to space the first doping crystalline silicon layer 212 and the second doping structure 220 along the second direction D2, so that the short circuit caused by the contact of doping structures with different doping types is effectively prevented.

According to the solar cell provided by the embodiment of the application, the first region 110 and the second region 120 which are staggered and have no interval are arranged along the first direction D1, two doping structures with opposite doping types are respectively arranged, a Gap region is not required to be etched by laser, the area of a photoelectric conversion region can be increased, the requirement on patterning precision can be reduced, the problem of offset short circuit of metallization printing is improved, the thickness of the silicon substrate 100 positioned in the first region 110 is greater than that of the silicon substrate 100 positioned in the second region 120, the first tunneling layer 211 positioned at a thicker position separates the first doped crystal silicon layer 212 from the second doped structure 220 along the second direction D2, the effective interval of different doping structures is realized, and the short circuit is effectively prevented.

In the embodiment of the present application, the doping type of the second doped structure 220 is opposite to that of the first doped structure 210, the first doped structure 210 includes a first tunneling layer 211 and a first doped crystalline silicon layer 212 sequentially stacked, the hierarchy structure of the second doped structure 220 may be the same as that of the first doped structure 210, and the hierarchy structure of the second doped structure 220 may also be different from that of the first doped structure 210.

In some embodiments, as shown in fig. 2, the second doping structure 220 includes a second tunneling layer 221 and a second doped crystalline silicon layer 222 stacked in sequence, the second tunneling layer 221 being in contact with the silicon substrate 100, and a side of the first tunneling layer 211 facing the silicon substrate 100 being spaced apart from a side of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 along a second direction D2.

In this embodiment, the second doped structure 220 and the first doped structure 210 are stacked in order, where the second tunneling layer 221 may also be made of silicon oxide (SiO 2), and the doping types of the first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222 are opposite.

In actual implementation, the first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222 may be doped with a doping source in a microcrystalline silicon layer, an amorphous silicon layer, or a polycrystalline silicon layer.

For example, the first doped crystalline silicon layer 212 may be a polysilicon layer with boron as a doping source, which may be referred to as P-poly, the first doped structure 210 forms a P-region of the solar cell, the second doped crystalline silicon layer 222 may be a polysilicon layer with phosphorus as a doping source, which may be referred to as N-poly, and the second doped structure 220 forms an N-region of the solar cell.

It should be noted that, the second doping structure 220 and the first doping structure 210 adopt the same hierarchical structure, so that parameters such as doping concentrations, junction depths and the like of the P region and the N region are consistent, fluctuation of electrical properties of different conductive regions is reduced, photoelectric conversion efficiency of the solar cell is improved, and a passivation structure formed by sequentially stacking tunneling layers and doped crystal silicon layers can also reduce composite loss of the solar cell.

In some embodiments, the distance between the side of the first tunneling layer 211 facing the silicon substrate 100 and the side of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2 is 10 μm-15 μm.

It will be appreciated that for the first doped structure 210 and the second doped structure 220 employing sequentially stacked tunneling layers and doped crystalline silicon layers, the first tunneling layer 211 is located in the first region 110 where the silicon substrate 100 is thicker, the second doped crystalline silicon layer 222 is located in the second region 120 where the silicon substrate 100 is thinner, and the side of the first tunneling layer 211 facing the silicon substrate 100 is spaced apart from the side of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2, the first tunneling layer 211 may achieve effective isolation of the first doped crystalline silicon layer 212 and the second doped crystalline silicon in the second direction D2.

In this embodiment, as shown in fig. 2, a distance H1 between a side of the first tunneling layer 211 facing the silicon substrate 100 and a side of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 in the second direction D2 is 10 μm-15 μm, and a side of the first tunneling layer 211 facing the silicon substrate 100 is in contact with the silicon substrate 100, i.e. the first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222 are separated in the second direction D2 by the silicon substrate 100 and the first tunneling layer 211 which are 10 μm-15 μm thick.

It should be noted that, for the first region 110 and the second region 120 having no space along the first direction D1, the silicon substrate 100 having a thickness of 10 μm to 15 μm and the first tunneling layer 211 located at a thicker position are disposed in the second direction D2, so as to isolate the first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222, and effectively prevent the short circuit caused by the contact of the doping structures with different doping types while increasing the area of the photoelectric conversion region of the solar cell.

In some embodiments, the first tunneling layer 211 and the second tunneling layer 221 are integrally provided.

In practical implementation, a groove may be formed on the silicon substrate 100, where the groove corresponds to the second region 120, and a tunneling layer is prepared, and the tunneling layer located in the groove may be referred to as a second tunneling layer 221, and the tunneling layer located outside the groove may be referred to as a first tunneling layer 211.

In this embodiment, the first tunneling layer 211 and the second tunneling layer 221 are integrally disposed, and the side wall of the silicon substrate 100 at the junction between the first region 110 and the second region 120 is also covered with a tunneling layer with tunneling effect, so as to effectively reduce the recombination probability of carriers.

In other embodiments, as shown in fig. 3, the second doping structure 220 may be a second diffusion layer 224 formed by diffusing the doping source from the back surface to the front surface in the second direction D2 of the silicon substrate 100.

In this embodiment, the second diffusion layer 224 is prepared by using a doping source to diffuse in the thickness direction of the back surface of the silicon substrate 100 toward the front surface, the diffusion can achieve uniform doping, the apparatus is simple, the process is mature, and parameters such as diffusion time, temperature, gas flow rate and the like can be controlled in the preparation process, so that the doping depth and concentration distribution can be controlled.

In practical implementation, the preparation of the first doped structure 210 may be completed on the silicon substrate 100, then the first doped region in the second region 120 is removed, and part of the silicon substrate 100 in the second region 120 is removed, so that the thickness of the silicon substrate 100 in the first region 110 is greater than that of the silicon substrate 100 in the second region 120, and then the second diffusion layer 224 is prepared by using the doping source to diffuse in the thickness direction in the second region 120.

In some embodiments, the first tunneling layer 211 is located at a distance of 10 μm-15 μm in the second direction D2 from the side of the silicon substrate 100 facing away from the front surface of the second diffusion layer 224.

In this embodiment, as shown in fig. 3, a distance H2 between a side of the first tunneling layer 211 facing the silicon substrate 100 and a side of the second diffusion layer 224 facing away from the front surface in the second direction D2 is 10 μm-15 μm, and a side of the first tunneling layer 211 facing the silicon substrate 100 is in contact with the silicon substrate 100, i.e., the first doped crystalline silicon layer 212 and the second diffusion layer 224 are spaced apart in the second direction D2 by the silicon substrate 100 having a thickness of 10 μm-15 μm and the first tunneling layer 211.

It can be understood that, for the first region 110 and the second region 120 having no space along the first direction D1, the silicon substrate 100 with a thickness of 10 μm-15 μm and the first tunneling layer 211 located at a thicker position are disposed in the second direction D2, so that the first doped crystalline silicon layer 212 and the second diffusion layer 224 are isolated, the area of the photoelectric conversion region of the solar cell is increased, and meanwhile, the contact of doping structures with different doping types is effectively prevented from causing short circuit.

In practical implementation, when the second diffusion layer 224 is prepared by diffusing the second region 120, even if the doping source diffuses to the boundary of the first region 110, the silicon substrate 100 with a sufficient thickness (10 μm-15 μm) and the first tunneling layer 211 are isolated in the first region 110, so that the short circuit caused by the contact of doping structures with different doping types can be effectively prevented without laser etching the Gap region.

In some embodiments, the area of the first region 110 is greater than or equal to the area of the second region 120.

In this embodiment, the total area of the first regions 110 in the solar cell may be greater than or equal to the total area of the second regions 120, or the area of the single first region 110 may be greater than or equal to the area of the single second region 120.

In practical implementation, the area ratio of the first region 110 and the second region 120 may be designed in consideration of the electrical performance, optical loss, process feasibility, and the like of the solar cell.

It should be noted that the area of the first region 110 may be matched to the number of carriers collected by the first doped structure 210 in the first region 110, and the area of the second region 120 may be matched to the number of carriers collected by the second doped structure 220 in the second region 120.

For example, the first doping structure 210 may be a P region doped with boron as a doping source, the second doping structure 220 may be an N region doped with phosphorus as a doping source, and the area of the first region 110 may be set to be larger than that of the second region 120, and the hole collection efficiency may be balanced with a slightly larger P region area.

The embodiment of the application also provides a preparation method of the solar cell, which can be used for preparing the solar cell.

As shown in fig. 4, the method for manufacturing the solar cell includes a step 510, a step 520 and a step 530.

Step 510 provides a silicon substrate 100.

The silicon substrate 100 has a front surface and a back surface that are disposed opposite to each other, and the silicon substrate 100 is provided with first regions 110 and second regions 120 that are staggered and spaced apart along a first direction D1, where the first direction D1 is a direction parallel to a plane in which the silicon substrate 100 is located.

In this step, the silicon substrate 100 may be subjected to pretreatment processes such as cleaning, texturing, etc., to improve the quality of the subsequent processes and the battery performance.

For example, the silicon substrate 100 is an N-type silicon wafer with a resistivity of 0.3 Ω·cm to 7 Ω·cm, the N-type silicon wafer is placed in an alkali polishing slot machine, and the original silicon wafer is subjected to double-sided polishing by alkali etching to form a tower foundation.

Wherein the size of the tower foundation can be 10-20 mu m, the treatment time of the alkali tank can be set to be 50-500 s, the treatment temperature can be set to be 50-90 ℃, the alkali concentration is set to be 0.5-2%, and the additive concentration is set to be 0.5-1%.

Step 520, forming a first doped structure 210 on the back surface.

The first doped structure 210 includes a first tunneling layer 211 and a first doped crystalline silicon layer 212 stacked in sequence, where the first tunneling layer 211 contacts the silicon substrate 100.

In this step, a first tunneling layer 211 and a first doped crystalline silicon layer 212 are sequentially stacked over the entire range of the back surface of the silicon substrate 100 (including the first region 110 and the second region 120), forming a first doping structure 210.

Taking the first doped crystalline silicon layer 212 as an example, a polysilicon layer P-poly with boron as a dopant source is used.

The first tunneling layer 211 and the boron doped first doped crystalline silicon layer 212 are formed by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) with tube diffusion.

In this embodiment, boron trichloride (BCl ₃) or boron tribromide (BBr ₃) may be used as the boron doping source, the diffusion temperature is controlled to be 900-1100 ℃, the sheet resistance is controlled to be 50 Ω/sq-400 Ω/sq, the thickness of the first doped crystalline silicon layer 212 may be 100nm-400nm, and the surface concentration may be 1E18cm ^-3-1E20cm^-3.

It will be appreciated that during the fabrication process, the surface of the first doped si layer 212 (i.e., the side of the first doped si layer 212 facing away from the first tunneling layer 211) may be formed with a first mask layer 213, and the doped si layer may be protected by a mask layer (mask).

Step 530, removing the first doping structure 210 and a portion of the silicon substrate 100 in the back surface second region 120, and forming a second doping structure 220 in the second region 120, the doping type of which is opposite to that of the first doping structure 210.

The surface of the first tunneling layer 211 facing the silicon substrate 100 is spaced apart from the surface of the second doped structure 220 facing away from the silicon substrate 100 along a second direction D2, where the second direction D2 is a direction perpendicular to the plane of the silicon substrate 100.

In this step, the first doping structure 210 in the second region 120 of the back surface is removed, and then a portion of the silicon substrate 100 in the second region 120 is removed, so that the thickness of the silicon substrate 100 in the first region 110 is greater than the thickness of the silicon substrate 100 in the second region 120, and then a second doping structure 220 having a doping type opposite to that of the first doping structure 210 is formed in the second region 120.

It is appreciated that the first doping structure 210 in the first region 110 remains when the first doping structure 210 and a portion of the silicon substrate 100 in the second region 120 are removed.

In actual implementation, the first doped structure 210 and a portion of the silicon substrate 100 in the second region 120 may be removed by laser, alkali etching, acid etching, or the like.

In this embodiment, the second doped structure 220 is prepared in the second region 120, the side of the first tunneling layer 211 of the first region 110 facing the silicon substrate 100 is spaced apart from the side of the second doped structure 220 of the second region 120 facing away from the silicon substrate 100 along the second direction D2, that is, the first doped structure 210 and the second doped structure 220 are spaced apart along the second direction D2, and the first doped crystalline silicon layer 212 and the second doped structure 220 can be spaced apart by the first tunneling layer 211, so that short circuit caused by contact of doped structures with different doping types is prevented, and efficient separation and collection of photo-generated carriers are realized.

It can be appreciated that after the second doped structure 220 is prepared, the passivation layer 310, the anti-reflection layer 320 and other structures can be prepared, and the electrode can also be prepared by a screen printing method, wherein the first doped structure 210 corresponds to the first electrode structure 410, the second doped structure 220 corresponds to the second electrode structure 420, and the first electrode structure 410 and the second electrode structure 420 can be thin gate, main gate and other gate line structures.

According to the method for manufacturing the solar cell provided by the embodiment of the application, the first region 110 and the second region 120 which are staggered and have no interval are arranged along the first direction D1, two doping structures with opposite doping types are manufactured on the back surface of the silicon substrate 100, a Gap region is not required to be etched by laser, the area of a photoelectric conversion region can be increased, the requirement on graphic precision can be reduced, the problem of offset short circuit of metallized printing is improved, the thickness of the silicon substrate 100 positioned in the first region 110 is larger than that of the silicon substrate 100 positioned in the second region 120, the first tunneling layer 211 positioned at a thicker position separates the first doping crystal silicon layer 212 from the second doping structure 220 along the second direction D2, the effective interval of different doping structures is realized, the process is simple, and the short circuit can be effectively prevented.

A specific process for preparing the second doping structure 220 is described below.

The second doped structure 220 includes a second tunneling layer 221 and a second doped crystalline silicon layer 222 stacked in sequence, and the second tunneling layer 221 contacts the silicon substrate 100.

In some embodiments, forming the first doping structure 210 at the back surface includes:

Forming a first tunneling layer 211, a first doped crystalline silicon layer 212 and a first mask layer 213 which are sequentially stacked, wherein the first mask layer 213 is in contact with one surface of the first doped crystalline silicon layer 212, which is away from the first tunneling layer 211;

removing the first doping structure 210 and a portion of the silicon substrate 100 in the back surface second region 120 and forming a second doping structure 220 of opposite doping type to the first doping structure 210 in the second region 120, comprising:

removing the first mask layer 213 in the back surface second region 120 using a laser;

Etching the first doped crystalline silicon layer 212, the first tunneling layer 211, and a portion of the silicon substrate 100 in the second region 120;

forming a second tunneling layer 221, a second doped crystalline silicon layer 222 and a second mask layer 223 which are sequentially stacked on the back surface, wherein the second mask layer 223 is contacted with one surface of the second doped crystalline silicon layer 222, which is away from the second tunneling layer 221;

removing the second mask layer 223 in the back surface first region 110 using a laser;

Etching the second doped crystalline silicon layer 222 and the second tunneling layer 221 in the first region 110;

The first mask layer 213 in the first region 110 and the second mask layer 223 in the second region 120 are etched.

It should be noted that, the first mask layer 213 may protect the first doped crystalline silicon layer 212, and the second mask layer 223 may protect the second doped crystalline silicon layer 222.

As shown in fig. 5, when the first doped structure 210 is prepared, a first tunneling layer 211, a first doped crystalline silicon layer 212 and a first mask layer 213 are formed on the back surface (including the first region 110 and the second region 120) sequentially stacked, and as shown in fig. 6, the first mask layer 213 in the second region 120 is removed by using a laser, and the first mask layer 213 in the first region 110 is remained to protect the first doped crystalline silicon layer 212 in the first region 110.

As shown in fig. 7, the first doped crystalline silicon layer 212, the first tunneling layer 211 and a portion of the silicon substrate 100 in the second region 120 are etched, and the first doped crystalline silicon layer 212 and the first tunneling layer 211 in the first region 110 remain under the protection of the first mask layer 213.

In actual implementation, the first doped crystalline silicon layer 212, the first tunneling layer 211, and a portion of the silicon substrate 100 in the second region 120 may be removed by wet etching.

In this embodiment, after removing the first doped structure 210 and a portion of the silicon substrate 100 in the back surface second region 120, as shown in fig. 8, a second tunneling layer 221, a second doped crystalline silicon layer 222, and a second mask layer 223, which are sequentially stacked, are formed on the back surface (including the first region 110 and the second region 120).

As shown in fig. 9, the second mask layer 223 in the back surface first region 110 is removed using a laser to remove the second doped crystalline silicon layer 222 and the second tunneling layer 221 in the first region 110.

In actual implementation, the second doped crystalline silicon layer 222 and the second tunneling layer 221 in the first region 110 may be removed by wet etching, where the second doped crystalline silicon layer 222 in the second region 120 is protected by the second mask layer 223.

As shown in fig. 10, after the second doped crystalline silicon layer 222 and the second tunneling layer 221 in the first region 110 are removed, the first mask layer 213 in the first region 110 and the second mask layer 223 in the second region 120 may be removed by an acid cleaning method, so that the subsequent passivation layer 310, the anti-reflection layer 320 and the electrode may be conveniently prepared.

In some embodiments, as shown in fig. 2, a distance H1 between a side of the first tunneling layer 211 facing the silicon substrate 100 and a side of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2 may be 10 μm-15 μm, and a side of the first tunneling layer 211 facing the silicon substrate 100 is in contact with the silicon substrate 100, i.e., the first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222 are spaced apart in the second direction D2 by the silicon substrate 100 and the first tunneling layer 211 having a thickness of 10 μm-15 μm.

In some embodiments, etching the first doped crystalline silicon layer 212, the first tunneling layer 211, and a portion of the silicon substrate 100 in the second region 120 includes:

etching the first doped crystalline silicon layer 212 and the first tunneling layer 211 in the second region 120;

The silicon substrate 100 of 13 μm-18 μm is etched from the back surface to the front surface along the second direction D2 such that a distance between a side of the first tunneling layer 211 facing the silicon substrate 100 and a side of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2 is 10 μm-15 μm.

In this embodiment, after the first doped crystalline silicon layer 212 and the first tunneling layer 211 in the second region 120 are removed, as shown in fig. 7, when etching a portion of the silicon substrate 100 in the second region 120, a silicon substrate 100 with a distance h3=13 μm-18 μm may be etched from the back surface to the front surface along the second direction D2 (i.e., the thickness direction of the silicon substrate 100), so that after the second doped structure 220 is prepared, as shown in fig. 10, a distance H1 between a side of the first tunneling layer 211 facing the silicon substrate 100 and a side of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2 is 10 μm-15 μm.

It can be appreciated that after the second doped crystalline silicon layer 222 and the second tunneling layer 221 are prepared, the distance between the surface of the first tunneling layer 211 facing the silicon substrate 100 and the surface of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2 is kept between 10 μm and 15 μm, and the first doped crystalline silicon layer 212 and the second doped crystalline silicon layer 222 are effectively isolated by the silicon substrate 100 with the thickness of 10 μm to 15 μm and the first tunneling layer 211 located at a thicker position, so that the Gap region is not required to be etched by laser, and the short circuit caused by the contact of doping structures with different doping types can be prevented.

A specific embodiment is described below.

An N-type silicon wafer with resistivity of 3 omega cm is selected as a silicon substrate 100, the original silicon wafer is subjected to double-sided polishing by alkali etching to form a tower base, the size of the tower base is 15 mu m, the treatment time of an alkali tank can be set to 300s, the treatment temperature can be set to 70 ℃, the alkali concentration is set to 1%, and the additive concentration is set to 0.5%.

As shown in fig. 5, by using boron trichloride (BCl ₃) or boron tribromide (BBr ₃) as a boron doping source in a manner of LPCVD and tube diffusion, the diffusion temperature is controlled to 980 ℃, the sheet resistance is controlled to 200 Ω/sq, and a first tunneling layer 211, a first doped crystalline silicon layer 212 and a first mask layer 213 are sequentially formed over the entire range of the back surface of the silicon substrate 100 (including the first region 110 and the second region 120), the first doped crystalline silicon layer 212 may be referred to as P-poly, and the first mask layer 213 is borosilicate glass (BSG).

In this embodiment, the BSG thickness may be 80nm, the first tunneling layer 211 may be 1.5nm, the P-poly thickness may be 250nm, and the surface concentration may be 1E19cm ^-3.

As shown in FIG. 6, the BSG in the second region 120 is removed by laser, and for the UV picosecond laser, the process parameters may include 15W spot power, 100 μm spot, 500kHz frequency, 60000mm/s sweep rate, and for the green picosecond laser, 30W spot power, 100 μm spot, 500kHz frequency, 50000mm/s sweep rate.

The BSG on the front surface was removed by a single-sided chained apparatus using hydrofluoric acid, and the front side-wound P-poly and the P-poly of the back surface second region 120 were removed by a slot machine, and as shown in fig. 7, further etched on the silicon substrate 100 of the back surface second region 120, the depth of the silicon substrate 100 of the back surface second region 120 was 15 μm.

The front and back surfaces are alkali polished, the second region 120 of the back surface has a pyramid foot size of 25 μm and both P-poly and BSG remain in the first region 110.

As shown in fig. 8, a phosphorus doping source is used to form a second tunneling layer 221, a second doped crystalline silicon layer 222 and a second mask layer 223, which are sequentially stacked, over the entire range of the back surface of the silicon substrate 100 (including the first region 110 and the second region 120) by means of LPCVD and tube diffusion, the second doped crystalline silicon layer 222 may be referred to as N-poly, and the second mask layer 223 is phosphosilicate glass (PSG).

In this embodiment, the PSG thickness may be 40nm, the second tunneling layer 221 may be 1.5nm, the N-poly thickness may be 150nm, and the surface concentration may be 5E20cm ^-3.

As shown in fig. 9, laser patterning is performed on the first region 110 of the back surface to remove PSG and expose N-poly overlying the P region, and the laser process parameters may refer to the BSG removal process parameters.

The PSG of the front surface winding plating is removed by a chain machine, then N-poly of the front surface winding plating and N-poly of the first area 110 of the back surface are removed by a groove machine, the front surface is subjected to texturing by an alkali matched additive, the pyramid size is 2 mu m, the texturing groove time is 400s, the temperature is 80 ℃, the alkali concentration is 1%, and the additive concentration is 0.8%.

As shown in fig. 10, the back surface N region PSG, the back surface P region BSG, and the back surface RCA are removed by using hydrofluoric acid, and a vertical height difference h1=12 μm is formed between the N region and the P region, i.e. a distance between the surface of the first tunneling layer 211 facing the silicon substrate 100 and the surface of the second doped crystalline silicon layer 222 facing away from the silicon substrate 100 along the second direction D2 is 10 μm-15 μm.

The passivation layer 310 of Al ₂O₃ is formed on the front and back surfaces by atomic deposition (ALD) process, the thickness of the passivation layer 310 is 3nm, and the anti-reflection layer 320 is deposited on the front and back surfaces by Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the anti-reflection layer 320 can be one or more laminated films of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the anti-reflection layer 320 is 80nm.

The electrodes of the main grid and the auxiliary grid on the back surface are prepared in a screen printing mode, and the printing slurry sintering is optimized through a laser-assisted sintering technology, so that the solar cell shown in figure 2 is prepared.

In the embodiment of the application, the Gap area structure on the back surface of the solar cell is removed, the first area 110 and the second area 120 which are staggered along the first direction D1 and have no interval are arranged, the areas of the N area and the P area on the back surface are increased, the Gap area is not required to be etched by laser in the preparation process of the cell, the laser patterning and metallization difficulty can be reduced, the thickness of the silicon substrate 100 positioned in the first area 110 is larger than that of the silicon substrate 100 positioned in the second area 120, the thickness distribution with obvious difference in the solar cell is formed, the first doped crystal silicon layer 212 and the second doped structure 220 are spaced along the second direction D2 in cooperation with the first tunneling layer 211 positioned at the thicker part of the cell, the short circuit caused by the contact of the doped structures with different doping types is effectively prevented, the preparation process flow of the solar cell is simple, and the large-scale production is facilitated.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

In the description of the present application, it should be understood that the terms "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.

In the description of the application, a "first feature" or "second feature" may include one or more of such features.

In the description of the present application, "plurality" means two or more.

In the description of the application, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by another feature therebetween.

In the description of the application, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the application as defined by the appended claims and their equivalents.

Claims

1. A solar cell, comprising:

A silicon substrate having a front surface and a back surface arranged opposite to each other, and having first regions and second regions arranged in a staggered manner without any gap along a first direction, wherein the first direction is a direction parallel to the plane where the silicon substrate is located, and the thickness of the silicon substrate located in the first region is greater than the thickness of the silicon substrate located in the second region;

A first doping structure, provided on the back surface and located in the first region, comprises a first tunneling layer and a first doped crystalline silicon layer stacked in sequence, wherein the first tunneling layer is in contact with the silicon substrate;

A second doping structure, disposed on the back surface and located in the second region;

Among them, a side of the first tunneling layer facing the silicon substrate is spaced apart from a side of the second doping structure facing away from the silicon substrate along a second direction, and the second direction is a direction perpendicular to the plane where the silicon substrate is located; the doping types of the first doping structure and the second doping structure are opposite.

2. The solar cell according to claim 1, wherein the second doping structure comprises a second tunneling layer and a second doped crystalline silicon layer stacked in sequence, and the second tunneling layer is in contact with the silicon substrate;

A surface of the first tunneling layer facing the silicon substrate is spaced apart from a surface of the second doped crystalline silicon layer facing away from the silicon substrate along the second direction.

3 . The solar cell according to claim 2 , wherein a distance along the second direction between a surface of the first tunneling layer facing the silicon substrate and a surface of the second doped crystalline silicon layer facing away from the silicon substrate is 10 μm-15 μm.

4 . The solar cell according to claim 2 , wherein the first tunneling layer and the second tunneling layer are integrally provided.

5 . The solar cell according to claim 1 , wherein the second doping structure is a second diffusion layer formed by diffusion of a doping source in the silicon substrate along the second direction from the back surface to the front surface.

6 . The solar cell according to claim 5 , wherein a distance along the second direction between a side of the first tunneling layer facing the silicon substrate and a side of the second diffusion layer facing away from the front surface is 10 μm-15 μm.

7 . The solar cell according to claim 1 , wherein an area of the first region is greater than or equal to an area of the second region.

8. A method for preparing a solar cell, comprising:

Providing a silicon substrate, wherein the silicon substrate has a front surface and a back surface arranged opposite to each other, and wherein the silicon substrate has first and second regions arranged in a staggered manner and without any gaps along a first direction, wherein the first direction is a direction parallel to a plane where the silicon substrate is located;

forming a first doping structure on the back surface, wherein the first doping structure comprises a first tunneling layer and a first doped crystalline silicon layer stacked in sequence, and the first tunneling layer is in contact with the silicon substrate;

The first doping structure and a portion of the silicon substrate in the second region of the back surface are removed, and a second doping structure of opposite doping type to that of the first doping structure is formed in the second region, and a side of the first tunneling layer facing the silicon substrate is spaced apart from a side of the second doping structure facing away from the silicon substrate along a second direction, and the second direction is a direction perpendicular to the plane where the silicon substrate is located.

9. The method for preparing a solar cell according to claim 8, wherein the second doping structure comprises a second tunneling layer and a second doped crystalline silicon layer stacked in sequence, and the second tunneling layer is in contact with the silicon substrate;

Forming a first doping structure on the back surface includes:

forming the first tunneling layer, the first doped crystalline silicon layer and the first mask layer stacked in sequence, wherein the first mask layer is in contact with a surface of the first doped crystalline silicon layer facing away from the first tunneling layer;

Removing the first doping structure and a portion of the silicon substrate in the second region of the back surface, and forming a second doping structure having a doping type opposite to that of the first doping structure in the second region, comprising:

Etching the first doped crystalline silicon layer, the first tunneling layer and a portion of the silicon substrate in the second region;

forming the second tunneling layer, the second doped crystalline silicon layer, and the second mask layer stacked in sequence on the back surface, wherein the second mask layer is in contact with a side of the second doped crystalline silicon layer facing away from the second tunneling layer;

removing the second mask layer in the first area of the back surface by using laser;

10. The method for preparing a solar cell according to claim 9, characterized in that:

Etching the first doped crystalline silicon layer, the first tunneling layer and a portion of the silicon substrate in the second region, comprising:

The silicon substrate is etched 13 μm-18 μm from the back surface to the front surface along the second direction, so that the distance between the first tunneling layer facing the silicon substrate and the second doped crystalline silicon layer facing away from the silicon substrate along the second direction is 10 μm-15 μm.