CN1201645C - Manufacturing method of highly integrated laminated base material - Google Patents

Abstract

The invention discloses a laminated substrate, which is formed by alternately stacking a plurality of dielectric layers and a plurality of circuit layers. The laminated substrate structure of the embodiment is characterized in that the pattern of the circuit layer between the dielectric layers is different from the design of the traditional annular ring pad, and the annular ring pad without the through hole is designed by adopting an embedded structure with better adhesive force and high reliability. The invention also discloses a manufacturing method of the laminated substrate, which is to manufacture the dielectric layer with the patterned circuit and the dielectric layer with the through hole, and after the dielectric layer with the patterned circuit and the dielectric layer with the through hole are manufactured, the dielectric layer with the patterned circuit and the dielectric layer with the through hole are synchronously aligned and pressed to finish the manufacturing of the laminated substrate.

Description

Manufacturing method of highly integrated laminated base material

technical field

The invention relates to a laminated substrate structure and a manufacturing method thereof, in particular to a packaging substrate or a printed circuit board structure and a manufacturing method thereof.

Background technique

Due to the progress and demand of electronic technology, various electronic related products are all developed in the direction of miniaturization and high density. In the field of packaging, the research and development of technologies such as Ball Grid Array (BGA) and Chip Scale Package (CSP) are oriented towards the market's demand for miniaturized and high-density products. In terms of printed circuit boards, in order to reduce the circuit area of the entire printed circuit board, the technology of multi-layer structure is also applied. However, no matter it is used for the substrate of the ball grid array package, the package in the chip size package, or the production of the printed circuit board (PCB), it is unavoidable to use conductive via holes as the connection between the layers of the circuit. Therefore, the thin lines and small-sized via holes on the build-up substrate will further increase the packaging density and the integration level of the printed circuit board.

The existing manufacturing methods of laminated substrates can be mainly divided into two types: lamination process and build up process. The lamination process is to provide multiple insulating layers first, then make a circuit layer on the surface of the insulating layer, and perform drilling, electroplating, and plugging processes on each insulating layer to produce a plated through hole (Plating Through Hole, PTH), so that the circuit layers on the two surfaces of the insulation can be electrically connected through the plated via holes formed by the via hole process. After the via holes are made in each insulating layer, conductive lines are then made on the laminated surface copper layer, and then a predetermined number of insulating layers are aligned with the surface copper layer and laminated to form a laminated substrate by repeating. Make complicated processes such as conductive lines to complete the substrate or circuit board.

When using the existing lamination process to manufacture laminated substrates, it is necessary to make via holes on the insulating layer, plate the via holes, and plug the insulating material. The process is cumbersome and time-consuming. In addition, when the size of the via hole in the insulating layer is close to 100 microns, the process difficulty and unit cost will be greatly increased, and when the size of the via hole is smaller than 100 microns, the industry is still unable to launch mass-produced products. Therefore, when the plated via hole is smaller than 100 microns, it will face the problem of mass production technology bottleneck.

In addition to the lamination process, the build-up process is also widely used in the industry. As the name implies, the build-up process is mainly to sequentially fabricate the dielectric layer, the interlayer via holes in the dielectric layer, and the circuit layer on the surface of the dielectric layer from bottom to top to form a build-up substrate. Among them, the dielectric layer in the laminated substrate is mainly formed by pressing, coating, etc. After the dielectric layer is formed, an opening is formed in the dielectric layer by image forming/etching process or laser/plasma etching. (opening), and fill the conductor material into the opening or form an interlayer via hole by electroplating, etc., and after the interlayer via hole is made, difficult chemical surface treatment and wiring are performed on the surface of the dielectric layer layer production. The laminated substrate can be produced by repeating the above complicated and difficult steps of making the dielectric layer, the interlayer via hole, the chemical surface treatment and the circuit layer.

In the build-up substrate produced by the build-up process, each dielectric layer and circuit layer must be fabricated sequentially from bottom to top, making the entire process too lengthy, and the production of each layer of dielectric layer and circuit layer will be directly processed. It affects the yield rate of the entire laminated substrate, so it is not easy to control the process yield rate. When using the build-up method to manufacture laminated substrates, in addition to the problems of too long process and low process yield, there are also problems such as high process cost and equipment investment cost, or sometimes the reliability is reduced due to difficult process control.

FIG. 1 is a schematic diagram of a via land at a contact position between a circuit layer and a via hole in a conventional build-up substrate. Referring to FIG. 1 , the circuit 100 a and the via annular pad 102 a are separated from the circuit 100 b and the via annular pad 102 b by a dielectric layer (not shown). Wherein, the dimensions of the via ring pads 102a, 102b are usually designed to be larger than the line widths of the lines 100a, 100b, so as to ensure that the dielectric layer can be used between the two circuit layers. The via hole 104 in is electrically connected. However, the via hole ring pad 102a and the via hole ring pad 102b usually reduce the layout space of the circuit layer, resulting in that the circuit integration degree in the build-up substrate cannot be effectively improved.

Contents of the invention

Therefore, the object of the present invention is to provide a build-up substrate, the contact position between the circuit layer and the via hole adopts a landless design, so as to improve the circuit integration in the build-up substrate.

The object of the present invention is to provide a laminated substrate with good electrical performance and thermal performance.

The purpose of the present invention is to propose a method for manufacturing a laminated substrate, which has the characteristics of high process yield, high production capacity, simple manufacturing method, high integration and low manufacturing cost.

In order to achieve the above object of the present invention, a laminated substrate is proposed, which is composed of multiple dielectric layers and multiple circuit layers stacked alternately. Wherein, there are a plurality of via holes in the dielectric layer, and the circuit layer enhances the via holes in the dielectric layer to be electrically connected to each other. The laminated base material of this embodiment is characterized in that the circuit layer between the dielectric layers The pattern is a via-free ring pad design. The circuit layer pattern designed without the via hole ring pad can effectively improve the circuit integration in the build-up substrate.

The laminated base material of the present invention further includes at least one pad opening layer disposed on the two outermost dielectric layers. Wherein, the pad opening layer has a plurality of openings corresponding to the via holes in the two outermost dielectric layers, and the pad opening layer is, for example, a dielectric layer or a solder mask layer (solder mask) as required. Or this layer need not be applied.

In order to achieve the above-mentioned purpose of the present invention, a kind of laminated base material manufacturing method is proposed, first carry out the making of the dielectric layer with patterned circuit and the dielectric layer with via hole, when the dielectric layer with patterned circuit and After the dielectric layer with the via hole is fabricated, it is aligned and pressed to complete the fabrication of the laminated substrate. Wherein, the dielectric layer with the patterned circuit and the dielectric layer with the via hole are, for example, bonded by vacuum thermal bonding. In addition, after the dielectric layer with the patterned circuit and the dielectric layer with the via hole are aligned and pressed together, for example, a curing step (curing) can be performed to combine the dielectric layer with the patterned circuit and the dielectric layer with the conductive hole. The dielectric material in the dielectric layer of the via hole is cured.

In order to achieve the above-mentioned purpose of the present invention, a kind of laminated base material manufacturing method is proposed, first carry out the dielectric layer with patterned line, the dielectric layer with via hole and the making that selectively applies welding pad opening layer, when having After the dielectric layer of the patterned circuit, the dielectric layer with via holes, and the opening layer of the pad are fabricated, they are aligned and pressed to complete the fabrication of the laminated substrate. Wherein, the dielectric layer with the patterned circuit and the dielectric layer with the via hole are, for example, bonded by vacuum thermal bonding. In addition, after the dielectric layer with the patterned circuit and the dielectric layer with the via hole are aligned and pressed together, for example, a curing step (curing) can be performed to combine the dielectric layer with the patterned circuit and the dielectric layer with the conductive hole. The dielectric material in the dielectric layer of the through hole solidifies and completes the electrical conduction at the proper position of the conduction line.

The present invention firstly provides a first support, then forms a patterned line on the first support, and finally forms a first dielectric layer on the first support to cover the patterned line, so that the first A dielectric layer with patterned lines is formed on the support body.

The present invention firstly provides a second support body, then forms a plurality of via hole columns on the second support body, and finally forms a second dielectric layer on the second support body, wherein the via hole columns protrude from the second dielectric layer. The surface of the electrical layer, so that the dielectric layer with via holes can be completed on the second support.

The patterned circuits of the present invention are formed by, for example, metal etching, pattern plating, semi-additive, or full-additive methods. In addition, the first dielectric layer and the second dielectric layer are formed by, for example, coating, spraying or bonding.

The openings in the pad opening layer of the present invention are formed by, for example, mechanical drilling, laser drilling, or punching.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below and described in detail in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a via ring pad at the contact position between the circuit layer and the via hole in the existing laminated substrate;

2A to 2D are schematic cross-sectional diagrams showing the fabrication process of a dielectric layer with patterned circuits in a build-up substrate according to the first embodiment of the present invention;

3A to FIG. 3D are schematic cross-sectional views showing the fabrication process of the dielectric layer with via holes in the build-up substrate according to the first embodiment of the present invention;

4A and FIG. 4B are schematic cross-sectional schematic diagrams showing the manufacturing process of a pad opening layer in a laminated base material according to the first embodiment of the present invention;

FIG. 5A and FIG. 5B are schematic cross-sectional views showing the lamination process of laminated substrates according to the first embodiment of the present invention;

6A to FIG. 6D are schematic cross-sectional diagrams illustrating the fabrication process of a dielectric layer with patterned circuits in a build-up substrate according to a second embodiment of the present invention; and

7 is a schematic diagram showing a landless design at the contact position between the circuit layer and the via post in the substrate structure according to the first embodiment and the second embodiment of the present invention.

【Description of figure number】

100a, 100b, 700a, 700b: lines

102a, 102b: Via grommet pads

104, 702: via hole

200: Dielectric layer with patterned lines

202, 302, 602: support body

204, 304, 604, 608: conductor layer

204a, 608a: patterned circuit

206, 306, 606: patterned photoresist

208, 308, 610: dielectric layer

300: Dielectric layer with via post

304a: Via post

400: dielectric layer

400a: pad opening layer

402, 607: opening

Detailed ways

first embodiment

2A to 2D are schematic cross-sectional views showing the fabrication process of the dielectric layer with patterned circuits in the build-up substrate according to the first embodiment of the present invention. The patterned circuit in the laminated substrate of this embodiment is formed by, for example, metal etching, patterned electroplating, semi-additive method, or full-additive method. In this embodiment, metal etching is used for illustration. First, referring to FIG. 2A , a supporter 202 is provided, and then a conductor layer 204 is formed on the supporter 202 . Wherein, the material of the conductor layer 204 is, for example, copper, and the conductor layer 204 is formed on the support body 202 by, for example, sputtering, pressure bonding or deposition.

Next, referring to FIG. 2B and FIG. 2C , a patterned photoresist 206 is formed on the conductor layer 204 , and the patterned photoresist 206 is used to define the pattern of the conductor layer 204 below it. Wherein, the patterned photoresist 206 is formed on the conductive layer 204 through steps such as photoresist coating, exposure, and development. After the patterned photoresist 206 is formed, the conductive layer 204 under it is etched with the patterned photoresist 206 as a mask, and the conductive layer 204 not covered by the patterned photoresist 206 is removed to form a patterned circuit 204a . After that, the patterned photoresist 206 is stripped off.

Referring to FIG. 2D , after forming the patterned circuit 204a, a dielectric layer 208 is then formed on the support body 202 to cover the patterned circuit 204a. Wherein, the patterned circuit 204 a and the dielectric layer 208 form a dielectric layer 200 with embedded patterned circuits.

3A to 3D are schematic cross-sectional diagrams illustrating the fabrication process of the dielectric layer with the via post in the build-up substrate according to the first embodiment of the present invention. First, referring to FIG. 3A , a support body 302 is provided, and then a conductor layer 304 is formed on the support body 302 . Wherein, the material of the conductor layer 304 is, for example, copper, and the conductor layer 304 is formed on the support body 302 by, for example, sputtering, pressure bonding or deposition.

Next, please refer to FIG. 3B and FIG. 3C , and then a patterned photoresist 306 is formed on the conductor layer 304 , and the patterned photoresist 306 is used to define the pattern of the conductor layer 304 below it, for example. Wherein, the patterned photoresist 306 is formed on the conductive layer 304 through steps such as photoresist coating, exposure, and development. After the patterned photoresist 306 is formed, the conductive layer 304 under the patterned photoresist 306 is used as a mask to etch, and the conductive layer 304 not covered by the patterned photoresist 306 is removed to form a via hole column 304a. After that, the patterned photoresist 306 is stripped off.

Referring to FIG. 3D , after forming the via post 304 a , a dielectric layer 308 is then formed on the support body 302 to cover the via post 304 a. Wherein, the via post 304 a and the dielectric layer 308 form a dielectric layer 300 with a via post. It can be clearly seen from FIG. 3D that the size of the via post 304a can vary depending on the process requirements.

4A and 4B are schematic cross-sectional views showing the manufacturing process of the pad opening layer in the laminated base material according to the first embodiment of the present invention. Please refer to FIG. 4A and FIG. 4B at the same time. First, a dielectric layer 400 is provided, and then an opening 402 is formed in the dielectric layer 400 to form a pad opening layer 400a. Wherein, the opening 402 in the pad opening layer 400 a is formed by mechanical drilling, laser drilling or punching, for example.

FIG. 5A and FIG. 5B are schematic cross-sectional views showing the lamination process of laminated substrates according to the first embodiment of the present invention. First, please refer to FIG. 5A and FIG. 5B at the same time, and align a plurality of completed dielectric layers 200 with patterned lines, dielectric layers 300 with via holes and pad opening layers 400a, as shown in FIG. 5A as shown. After alignment, the dielectric layer 200 with patterned lines, the dielectric layer 300 with via holes and the pad opening layer 400a are pressed together to complete the fabrication of the laminated substrate. Wherein, the dielectric layer 200 with patterned lines, the dielectric layer 300 with via holes, and the pad opening layer 400 a are bonded together by, for example, vacuum thermal bonding.

Also referring to FIG. 5A and FIG. 5B , the pad opening layer 400 a is an optional component in the fabrication process of the laminated substrate. In other words, in this embodiment, only a plurality of dielectric layers 200 with patterned lines and a plurality of dielectric layers 300 with via holes can be aligned and bonded. In this way, the welding pad opening layer 400a can be omitted in the manufacturing process of the laminated base material, which simplifies the overall process.

second embodiment

This embodiment is the same as the first embodiment in the fabrication of the dielectric layer with via holes and the pad opening layer, but the difference between this embodiment and the first embodiment lies in the dielectric layer with patterned lines way of making.

6A to 6D are schematic cross-sectional diagrams illustrating the fabrication process of the dielectric layer with patterned circuits in the build-up substrate according to the second embodiment of the present invention. First, referring to FIG. 6A , a support body 602 is provided, and then a conductor layer 604 is formed on the support body 602 . Wherein, the material of the conductor layer 604 is, for example, copper, and the conductor layer 604 is formed on the support body 602 by, for example, sputtering, pressure bonding or deposition.

Next, referring to FIG. 6B and FIG. 6C , a patterned photoresist 606 is formed on the conductive layer 604 , and the patterned photoresist 606 has a plurality of openings 607 . Wherein, the patterned photoresist 606 is formed on the conductor layer 604 through steps such as photoresist coating, exposure, and development. After the patterned photoresist 606 is formed, the conductive layer 608 is filled in the opening 607 of the patterned photoresist 606. Since the opening 607 is a predetermined pattern, the conductive layer 608 filled in the opening 607 will be consistent with the above predetermined pattern. unanimous. Afterwards, the patterned photoresist 606 is stripped off to expose the underlying conductor layer 604 .

Referring to FIG. 6C and FIG. 6D , after the patterned photoresist 606 is stripped, a non-selective micro-etching step is then performed to remove the conductor layer 604 . During the removal process of the conductive layer 604 , part of the thickness of the conductive layer 608 is also etched away to form a patterned circuit 608 a. After the patterned circuit 608a is formed, a dielectric layer 610 is then formed on the support 602 to cover the patterned circuit 608a. Wherein, the patterned circuit 608 a and the dielectric layer 610 constitute a dielectric layer 600 with patterned circuits.

The process of the above-mentioned Figures 6A to 6D can be used to manufacture thin lines in the build-up substrate, and this thin line process (Figure 6A to Figure 6D) can effectively increase the circuit density in the build-up substrate, and also for the The layout flexibility of the wiring layers in the buildup substrate helps.

7 is a schematic diagram showing a landless design at the contact position between the circuit layer and the via post in the substrate structure according to the first embodiment and the second embodiment of the present invention. Referring to FIG. 7 , the circuit 700 a is separated from the circuit 700 b through a dielectric layer (not shown), and the circuit 700 a and the circuit 700 b are electrically connected through a via post 702 .

Referring to FIG. 1 and FIG. 7 at the same time, in this embodiment, the circuit 700a and the circuit 700b are directly electrically connected to the via post 702, and the existing design of the via ring pads 102a and 102b (shown in FIG. 1). Therefore, the layout space of the circuit layer in this embodiment is not limited by the via hole ring pads 102a, 102b and will not be reduced.

In summary, the laminated base material and its manufacturing method of the present invention have at least the following advantages:

1. In the laminated substrate of the present invention, the contact position between the circuit layer and the via hole is designed with a non-via-hole ring pad, which can greatly increase the circuit integration in the laminated substrate.

2. In the laminated base material of the present invention, the via column adopts a solid via design, so it has good electrical performance and heat dissipation performance.

3. In the manufacturing method of the laminated base material of the present invention, the laminated base material can be produced only through the pattern process (pattern process) and simultaneous lamination, so the manufacturing time can be effectively shortened, and the production capacity can be increased.

4. In the manufacturing method of the laminated base material of the present invention, the laminated base material can be produced only through the pattern process (pattern process) and simultaneous lamination, so the existing investment in other equipment can be saved.

5. In the manufacturing method of the laminated base material of the present invention, before each layer (the dielectric layer with the patterned circuit, the dielectric layer with the via hole column and the pad opening layer) is laminated, each layer can be separately laminated. The layer is confirmed, so the yield rate of the laminated substrate is easier to control and effectively reduces the production cost.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any skilled person in the art can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (10)

1. A method for manufacturing a laminated base material, comprising: providing a first support body; forming a patterned circuit on the first support; forming a first dielectric layer on the first support, the first dielectric layer covers the patterned circuit, so as to form a dielectric layer with patterned circuit on the first support; providing a second support body; forming a plurality of via holes on the second support; forming a second dielectric layer on the second support, the via pillars protrude from the second dielectric layer, so as to form a dielectric layer with via pillars on the second support; and aligning and pressing a plurality of dielectric layers with patterned lines and a plurality of dielectric layers with via holes, so that the via holes penetrate the first dielectric layer and electrically connect with the patterned lines sexual connection. 2. The method for manufacturing a laminated substrate according to claim 1, characterized in that: after the dielectric layers with patterned circuits are aligned and pressed together with the dielectric layers with via holes, further comprising: A curing step to cure the first dielectric layer and the second dielectric layer and simultaneously complete the electrical conduction connection of the conductive sites. 3. The method for manufacturing a laminated substrate according to claim 1, wherein the method for forming the patterned circuit comprises: forming a conductor layer on the first support; forming a patterned photoresist on the conductor layer; and Using the patterned photoresist as a mask, the conductive layer not covered by the patterned photoresist is removed to form the patterned circuit. 4. The method for manufacturing a laminated substrate according to claim 1, wherein the method for forming the patterned circuit comprises: forming a first conductor layer on the first support; forming a patterned photoresist on the conductor layer, the patterned photoresist has a plurality of openings; forming a second conductor layer in the openings; removing the patterned photoresist; and The first conductor layer not covered by the second conductor layer is removed to form the patterned circuit. 5 . The method for manufacturing a laminated substrate as claimed in claim 1 , wherein the lamination of the dielectric layers with patterned lines and the dielectric layers with via holes is vacuum thermocompression. 6 . 6. A method for manufacturing a laminated base material, comprising: providing a first support body; forming a patterned circuit on the first support; forming a first dielectric layer on the first support, the first dielectric layer covers the patterned circuit, so as to form a dielectric layer with patterned circuit on the first support; providing a second support body; forming a plurality of via holes on the second support; forming a second dielectric layer on the second support body, the via holes protrude from the second dielectric layer, so as to form a dielectric layer with via hole columns on the second support body; providing at least one pad opening layer having a plurality of openings; and Align and press a plurality of dielectric layers with patterned lines, a plurality of dielectric layers with via holes and the pad opening layer, so that the via holes penetrate the first dielectric layer and It is electrically connected with the patterned circuit. 7. The method for manufacturing a laminated substrate according to claim 6, wherein the dielectric layers with patterned lines, the dielectric layers with via holes, and the pad opening layer are aligned and pressed together After the bonding, a curing step is also included to cure the first dielectric layer and the second dielectric layer and simultaneously complete the electrical conduction connection of the conductive positions. 8. The method for manufacturing a laminated substrate according to claim 6, wherein the method for forming the patterned circuit comprises: forming a conductor layer on the first support; forming a patterned photoresist on the conductor layer; and Using the patterned photoresist as a mask, the conductive layer not covered by the patterned photoresist is removed to form the patterned circuit. 9. The method for manufacturing a laminated substrate according to claim 6, wherein the method for forming the patterned circuit comprises: forming a first conductor layer on the first support; forming a patterned photoresist on the conductor layer, the patterned photoresist has a plurality of openings; forming a second conductor layer in the openings; removing the patterned photoresist; and The first conductor layer not covered by the second conductor layer is removed to form the patterned circuit. 10. The method for manufacturing a laminated substrate as claimed in claim 6, wherein the method for forming the via holes comprises: forming a conductor layer on the second support; forming a patterned photoresist on the conductor layer; and Using the patterned photoresist as a mask, the conductive layer not covered by the patterned photoresist is removed to form the via holes.

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