CN120111880A - Method for manufacturing dynamic random access memory - Google Patents
Method for manufacturing dynamic random access memory Download PDFInfo
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- CN120111880A CN120111880A CN202311767974.8A CN202311767974A CN120111880A CN 120111880 A CN120111880 A CN 120111880A CN 202311767974 A CN202311767974 A CN 202311767974A CN 120111880 A CN120111880 A CN 120111880A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
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Abstract
本发明公开一种动态随机存取存储器的制造方法，其包括以下步骤。在基底上形成第一晶体管与第二晶体管以及在基底中形成用以隔离第一晶体管与第二晶体管的隔离结构。在基底上形成介电层，其中介电层暴露出第一晶体管的源极/漏极区中的邻近隔离结构者以及第二晶体管的源极/漏极区中的邻近隔离结构者。在暴露出的源极/漏极区上成长第一外延层以及在第二外延层。在第一外延层与第二外延层之间的隔离结构上形成绝缘结构。在第一外延层上形成第一接触结构，以及在第二外延层上形成第二接触结构，其中第一接触结构与第二接触结构通过绝缘结构而分隔开。在介电层上形成第一电容器与第二电容器。
The present invention discloses a method for manufacturing a dynamic random access memory, which includes the following steps. A first transistor and a second transistor are formed on a substrate, and an isolation structure for isolating the first transistor from the second transistor is formed in the substrate. A dielectric layer is formed on the substrate, wherein the dielectric layer exposes adjacent isolation structures in the source/drain region of the first transistor and adjacent isolation structures in the source/drain region of the second transistor. A first epitaxial layer and a second epitaxial layer are grown on the exposed source/drain region. An insulating structure is formed on the isolation structure between the first epitaxial layer and the second epitaxial layer. A first contact structure is formed on the first epitaxial layer, and a second contact structure is formed on the second epitaxial layer, wherein the first contact structure and the second contact structure are separated by the insulating structure. A first capacitor and a second capacitor are formed on the dielectric layer.
Description
Technical Field
The present invention relates to a method for manufacturing a memory, and more particularly to a method for manufacturing a dynamic random access memory (dynamic random access memory, DRAM).
Background
A dynamic random access memory is developed, which includes a transistor and a capacitor. In such a dynamic random access memory, a capacitor is used as a storage node (storage node). Generally, a capacitor may be disposed over a transistor, and the capacitor is electrically connected to the transistor through a contact (contact) connected between the capacitor and source/drain regions of the transistor.
In the current manufacturing process of the dram, a conductive material is generally formed between two adjacent active regions, and then an etching process is performed on the conductive material to form the contact windows in the two active regions respectively. However, in order to avoid the contact windows in two adjacent active regions contacting each other to cause a short circuit, the etching degree is generally increased to avoid the conductive material remaining between the two active regions. As such, the active region is often damaged by overetching. In addition, if the etching degree is reduced to avoid damage to the active regions, a short circuit may be generated due to the conductive material remaining between the two active regions.
Disclosure of Invention
The invention provides a method for manufacturing a dynamic random access memory, wherein in the process of forming contact structures for electrically connecting a capacitor and a transistor in two adjacent active (active) regions, an insulating part formed on an isolation structure can be used as an etching stop layer, so that damage to the active regions caused by overetching during an etching manufacturing process can be effectively avoided, and the contact structures in the adjacent active regions can be effectively and completely separated.
The manufacturing method of the dynamic random access memory comprises the following steps. Forming a first transistor and a second transistor on a substrate and forming an isolation structure in the substrate to isolate the first transistor from the second transistor. A first bit line structure electrically connected to the first transistor is formed on a side of the first transistor remote from the isolation structure, and a second bit line structure electrically connected to the second transistor is formed on a side of the second transistor remote from the isolation structure. A dielectric layer is formed over the substrate, wherein the dielectric layer exposes adjacent ones of the source/drain regions of the first transistor and adjacent ones of the isolation structures of the second transistor. A first epitaxial layer is grown on the source/drain regions of the first transistor and a second epitaxial layer is grown on the source/drain regions of the second transistor. An insulating structure is formed over the isolation structure between the first epitaxial layer and the second epitaxial layer. A first contact structure is formed on the first epitaxial layer and a second contact structure is formed on the second epitaxial layer, wherein the first contact structure and the second contact structure are separated by the insulating structure. A first capacitor and a second capacitor are formed on the dielectric layer, wherein the first capacitor is electrically connected with the first contact structure and the second capacitor is electrically connected with the second contact structure.
In an embodiment of the method for manufacturing a dynamic random access memory of the present invention, the method for forming the insulating structure, the first contact structure and the second contact structure includes the following steps. A first insulating portion is formed over the isolation structure between the first epitaxial layer and the second epitaxial layer. A conductive layer is formed on the first epitaxial layer, the second epitaxial layer, and the first insulating portion. A first mask layer and a second mask layer are formed over the conductive layer, wherein the first mask layer is located on sidewalls of portions of the dielectric layer that cover the first transistor, and the second mask layer is located on sidewalls of portions of the dielectric layer that cover the second transistor. And removing the conductive layer on the first insulating part by taking the dielectric layer, the first mask layer and the second mask layer as etching masks so as to form a first conductive part on the first epitaxial layer and a second conductive part on the second epitaxial layer. A second insulating portion is formed on the first insulating portion. And removing the first mask layer and the second mask layer. A first contact is formed on the first conductive portion and a second contact is formed on the second conductive portion. The first insulating portion and the second insulating portion form the insulating structure, the first conductive portion and the first contact window form the first contact structure, and the second conductive portion and the second contact window form the second contact structure.
In an embodiment of the method for manufacturing a dynamic random access memory of the present invention, the method for forming the first insulating portion includes the following steps. An insulating material layer is conformally formed over the dielectric layer, the first epitaxial layer, the isolation structure, and the second epitaxial layer. An etch process is performed to remove the layer of insulating material on the surface of the dielectric layer, on the top surface of the first epitaxial layer, and on the top surface of the second epitaxial layer.
In an embodiment of the method for manufacturing a dynamic random access memory of the present invention, the method for forming the conductive layer includes the following steps. A layer of conductive material is formed on the substrate, wherein the layer of conductive material covers the dielectric layer, the first epitaxial layer, the second epitaxial layer, and the first insulating portion. An etching process is performed to remove the conductive material layer on the top surface of the dielectric layer and portions of the conductive material layer on the first epitaxial layer, the second epitaxial layer, and the first insulating portion.
In an embodiment of the method for manufacturing a dynamic random access memory of the present invention, the method for forming the first mask layer and the second mask layer includes the following steps. A masking material layer is conformally formed over the dielectric layer and the conductive layer. An etching process is performed to remove the mask material layer on the surface of the dielectric layer and a portion of the mask material layer on the conductive layer.
In an embodiment of the method for manufacturing a dynamic random access memory of the present invention, the method for forming the second insulating portion includes the following steps. An insulating material layer is formed over the substrate, wherein the insulating material layer covers the dielectric layer, the first mask layer, the second mask layer, the first conductive portion, the second conductive portion, and the first insulating portion. An etch process is performed to remove the layer of insulating material on the top surface of the dielectric layer, the top surface of the first mask layer, and the top surface of the second mask layer.
In an embodiment of the method for manufacturing a dynamic random access memory of the present invention, the method for forming the first contact and the second contact includes the following steps. A barrier material layer is conformally formed over the dielectric layer, the first conductive portion, the second conductive portion, and the second insulating portion. A layer of conductive material is formed over the barrier material layer. The barrier material layer and the conductive material layer on the top surface of the dielectric layer and the top surface of the second insulating portion are removed to form a contact layer and a barrier layer surrounding the sidewalls and bottom surface of the contact layer. The contact layer and the barrier layer form the first contact window and the second contact window.
In an embodiment of the method for manufacturing a dynamic random access memory of the present invention, the first transistor and the second transistor each include a gate, a gate dielectric layer, and the source/drain regions. The gate is formed in the substrate. The gate dielectric layer is formed between the gate and the substrate. The source/drain regions are formed in the substrate on both sides of the gate electrode.
In an embodiment of the method for fabricating a dynamic random access memory of the present invention, the first bit line structure includes a first bit line and a first bit line contact window formed between the first bit line and the source/drain region of the first transistor, and the second bit line structure includes a second bit line and a second bit line contact window formed between the second bit line and the source/drain region of the second transistor.
In an embodiment of the method for manufacturing a dynamic random access memory of the present invention, the first capacitor and the second capacitor each comprise a cup-shaped capacitor.
Based on the above, in the method for manufacturing the dynamic random access memory of the present invention, the insulating portion is formed on the isolation structure between the two adjacent active regions, so that the insulating portion can be used as an etching stop layer in the process of forming the contact structure for electrically connecting the capacitor and the transistor in the two active regions, thereby effectively avoiding damage to the active regions due to overetching, and effectively completely separating the contact structures in the adjacent active regions.
Drawings
Fig. 1A to 1H are schematic cross-sectional views of a manufacturing process of a dynamic random access memory according to an embodiment of the invention.
Symbol description
100 Substrate
100A first active region
100B second active region
102 Isolation structure
104A, 104b gate electrode
106A, 106b gate dielectric layer
108A, 108b, 110a, 110b doped regions
112A first bit line structure
112B second bit line structure
114 Dielectric layer
116A first epitaxial layer
116B second epitaxial layer
118 Insulating material layer
120 First insulating portion
122 Conductive layer
124 Masking material layer
124A first mask layer
124B second mask layer
126A first conductive portion
126B second conductive portion
128 Second insulating portion
129 Insulating structure
130A first contact
130B second contact window
132A, 132b contact layer
134A, 134b barrier layer
136A first contact structure
136B second contact structure
138 Insulating layer
Bc1 first bit line contact
Bc2 second bit line contact
BL1 first bit line
BL2 second bit line
C1 first capacitor
C2 second capacitor
E1 lower electrode
E2:upper electrode
TR1 first transistor
TR2 second transistor
Detailed Description
The following examples are set forth in detail in connection with the accompanying drawings, but are not intended to limit the scope of the invention. Moreover, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like elements will be described with like reference numerals throughout the following description.
As used herein, the terms "comprising," "including," "having," and the like are open-ended terms, i.e., including, but not limited to.
When elements are described in terms of "first," "second," and the like, they are merely used to distinguish one element from another, and do not limit the order or importance of the elements. Thus, in some cases, a first element may also be termed a second element, which may also be termed a first element, without departing from the scope of the present invention.
In addition, directional terms such as "upper", "lower", etc. are used only with reference to the directions of the drawings, and are not intended to limit the present invention. Thus, it will be understood that "upper" may be used interchangeably with "lower" and that when an element such as a layer or film is placed "on" another element, the element may be placed directly on the other element, or intervening elements may be present. On the other hand, when an element is referred to as being "directly on" another element, there are no intervening elements present therebetween.
Fig. 1A to 1H are schematic cross-sectional views of a manufacturing process of a dynamic random access memory according to an embodiment of the invention.
First, referring to fig. 1A, a substrate 100 is provided. In the present embodiment, the substrate 100 is a silicon substrate, but the present invention is not limited thereto. Next, an isolation structure 102 is formed in the substrate 100 to define a first active region 100a and a second active region 100b. In the present embodiment, the isolation structure 102 is a shallow trench isolation (shallow trench isolation, STI) structure, but the present invention is not limited thereto.
Then, a first transistor TR1 is formed on the substrate 100 in the first active region 100a, and a second transistor TR2 is formed on the substrate 100 in the second active region 100 b. In the present embodiment, the first transistor TR1 and the second transistor TR2 are each transistors having a buried gate, but the present invention is not limited thereto.
In this embodiment, the first transistor TR1 may include a gate 104a formed in the substrate 100, a gate dielectric layer 106a formed between the gate 104a and the substrate 100, and a doped region 108a and a doped region 110a formed in the substrate 100 on both sides of the gate 104a, wherein the doped region 108a is far from the isolation structure 102, the doped region 110a is adjacent to the isolation structure 102, and the doped region 108a and the doped region 110a may serve as source/drain regions of the first transistor TR 1. In addition, in the present embodiment, the second transistor TR2 may include a gate 104b formed in the substrate 100, a gate dielectric layer 106b formed between the gate 104b and the substrate 100, and a doped region 108b and a doped region 110b formed in the substrate 100 on both sides of the gate 104b, wherein the doped region 108b is far from the isolation structure 102, the doped region 110b is adjacent to the isolation structure 102, and the doped region 108b and the doped region 110b may serve as source/drain regions of the second transistor TR 2. The above-described structures of the first transistor TR1 and the second transistor TR2 are merely exemplary, and the present invention is not limited thereto.
Next, a first bit line structure 112a is formed over the doped region 108a, and a second bit line structure 112b is formed over the doped region 108 b. In the present embodiment, the first bit line structure 112a includes a first bit line BL1 and a first bit line contact BC1 formed between the first bit line BL1 and the doped region 108a, such that the first bit line BL1 can be electrically connected to the first transistor TR1 through the first bit line contact BC 1. In addition, in the present embodiment, the second bit line structure 112b includes a second bit line BL2 and a second bit line contact BC2 formed between the second bit line BL2 and the doped region 108b, such that the second bit line BL2 can be electrically connected to the second transistor TR2 through the second bit line contact BC 2. The above-described architectures of the first bit line structure 112a and the second bit line structure 112b are merely exemplary, and the present invention is not limited thereto.
The methods for forming the first transistor TR1, the second transistor TR2, the first bit line structure 112a and the second bit line structure 112b are well known to those skilled in the art, and will not be described herein.
After forming the first bit line structure 112a and the second bit line structure 112b, a dielectric layer 114 is formed on the substrate 100. Dielectric layer 114 may act as an inter-layer dielectric (ILD) layer. In the present embodiment, the dielectric layer 114 covers the first bit line structure 112a, the second bit line structure 112b, and portions of the first transistor TR1 and the second transistor TR2, and exposes the isolation structure 102, the doped region 110a of the first transistor TR1 adjacent to the isolation structure 102, and the doped region 110b of the second transistor TR1 adjacent to the isolation structure 102.
Next, referring to fig. 1B, an epitaxial growth process (epitaxially growing process) is performed to form a first epitaxial layer 116a and a second epitaxial layer 116B on the doped region 110a and the doped region 110B exposed by the dielectric layer 114, respectively. Since the material of the isolation structure 102 is typically silicon oxide or the like, the epitaxial layer formed during the epitaxial growth process is not formed on the isolation structure 102. Furthermore, the epitaxial layer formed may have a curved top surface, i.e., the thickness of the epitaxial layer may decrease from the central portion toward the edge portion, based on the characteristics of the epitaxial growth process. Furthermore, depending on the time of epitaxial growth, the edge portion of the epitaxial layer may extend slightly onto the top surface of the isolation structure 102. Importantly, in this embodiment, the time of the epitaxial growth must be controlled to avoid the first epitaxial layer 116a and the second epitaxial layer 116b being formed to extend too far to contact each other on the top surface of the isolation structure 102. That is, in the present embodiment, the first epitaxial layer 116a and the second epitaxial layer 116b may be separated from each other by the isolation structure 102. In this embodiment, the maximum thickness of each of the first epitaxial layer 116a and the second epitaxial layer 116b is, for example, between 9nm and 13 nm.
After forming the first epitaxial layer 116a and the second epitaxial layer 116b, a layer of insulating material 118 is conformally formed over the dielectric layer 114, the first epitaxial layer 116a, the isolation structure 102, and the second epitaxial layer 116 b. In the present embodiment, the material of the insulating material layer 118 is silicon oxide, but the present invention is not limited thereto.
Then, referring to fig. 1C, an etching process is performed to remove the insulating material layer 118 on the surface of the dielectric layer 114, the top surface of the first epitaxial layer 116a, and the top surface of the second epitaxial layer 116, and to leave the insulating material layer 118 between the first epitaxial layer 116a and the second epitaxial layer 116 b. As such, the insulating material layer 118 remaining between the first epitaxial layer 116a and the second epitaxial layer 116b forms a first insulating portion 120 on the isolation structure 112. Thus, the first insulating portion 120 isolates the first epitaxial layer 116a from the second epitaxial layer 116 b. In the etching process described above, the top portions of the first epitaxial layer 116a and the second epitaxial layer 116b may be slightly removed depending on the etching time.
Next, referring to fig. 1D, a conductive layer 122 is formed on the first epitaxial layer 116a, the second epitaxial layer 116b, and the first insulating portion 120. The conductive layer 122 is used to form a contact window for connecting the capacitor and the transistor. In the present embodiment, the material of the conductive layer 122 is polysilicon, but the present invention is not limited thereto. The method of forming the conductive layer 122 may include the following steps. A conductive material layer is formed on the substrate 100 to cover the dielectric layer 114, the first epitaxial layer 116a, the second epitaxial layer 116b, and the first insulating portion 120. Thereafter, an etching process is performed to remove the conductive material layer on the top surface of the dielectric layer 114 and portions of the conductive material layer on the first epitaxial layer 116a, the second epitaxial layer 116b and the first insulating portion 120. In this way, the remaining conductive material layer forms the conductive layer 122. The thickness of the conductive layer 122 may be determined according to practical requirements, and the present invention is not limited thereto.
After forming the conductive layer 122, a mask material layer 124 is conformally formed over the dielectric layer 114 and the conductive layer 122. In the present embodiment, the material of the mask material layer 1242 is silicon nitride, but the present invention is not limited thereto.
Then, referring to fig. 1E, an etching process is performed to remove the mask material layer 124 on the surface of the dielectric layer 114 and a portion of the mask material layer 114 on the conductive layer 122. In this way, the first mask layer 124a and the second mask layer 124b are formed on the conductive layer 122. The first mask layer 124a is located on a sidewall of the portion of the dielectric layer 114 covering the first transistor TR1, and the second mask layer 124b is located on a sidewall of the portion of the dielectric layer 114 covering the second transistor TR 2. That is, a first mask layer 124a is formed on the sidewalls of the dielectric layer 114 and over the doped region 110a, and a second mask layer 124b is formed on the sidewalls of the dielectric layer 114 and over the doped region 110 b.
After forming the first mask layer 124a and the second mask layer 124b, an etching process is performed using the dielectric layer 114, the first mask layer 124a and the second mask layer 124b as etching masks, so as to form the exposed conductive layer 122, thereby forming a first conductive portion 126a on the first epitaxial layer 116a and a second conductive portion 126b on the second epitaxial layer 116 b. During the etching process, the corners of the first epitaxial layer 116a and the second epitaxial layer 116b may be slightly removed. However, even in the case where the corners of the first epitaxial layer 116a and the second epitaxial layer 116b are slightly removed, the first active region 100a and the second active region 100b are not damaged.
Next, referring to fig. 1F, an insulating material layer (not shown) is formed on the substrate 100 to cover the dielectric layer 114, the first mask layer 124a, the second mask layer 124b, the first conductive portion 126a, the second conductive portion 126b, the first epitaxial layer 116a, the second epitaxial layer 116b and the first insulating portion 120. In the present embodiment, the material of the insulating material layer is silicon oxide, but the present invention is not limited thereto, as long as the material of the insulating material layer is different from the materials of the first mask layer 124a and the second mask layer 124 b. Then, an etching process is performed to remove the insulating material layer on the top surface of the dielectric layer 114, the top surface of the first mask layer 124a, and the top surface of the second mask layer 124 b. In this way, the second insulating portion 128 is formed on the first insulating portion 120. In this embodiment, the first insulating portion 120 and the second insulating portion 128 form an insulating structure 129 for separating the contact structures in the adjacent first active region 100a and the second active region 100b, which will be described in detail later.
After the second insulating portion 128 is formed, the first mask layer 124a and the second mask layer 124b are removed to expose the first conductive portion 126a and the second conductive portion 126b. Since the material of the second insulating portion 128 is different from the materials of the first mask layer 124a and the second mask layer 124b, the second insulating portion 128 is not seriously affected in removing the first mask layer 124a and the second mask layer 124 b.
Then, referring to fig. 1G, a first contact 130a is formed on the first conductive portion 126a, and a second contact 130b is formed on the second conductive portion 126 b. In the present embodiment, the first contact 130a includes a contact layer 132a and a barrier layer 134a surrounding the sidewall and the bottom of the contact layer 132a, and the second contact 130b includes a contact layer 132b and a barrier layer 134b surrounding the sidewall and the bottom of the contact layer 132b, but the present invention is not limited thereto. The material of the contact layer 132a and the contact layer 132b may be tungsten, and the material of the barrier layer 134a and the barrier layer 134b may be titanium nitride, but the present invention is not limited thereto. In this embodiment, the method for forming the first contact 130a and the second contact 130b may include the following steps. A barrier material layer is conformally formed over the dielectric layer 114, the first conductive portion 126a, the second conductive portion 126b, and the second insulating portion 128, then a conductive material layer is formed over the barrier material layer, and then the barrier material layer and the conductive material layer are removed over the top surface of the dielectric layer 114 and over the top surface of the second insulating portion 128.
In the present embodiment, the first conductive portion 126a and the first contact window 130a form a first contact structure 136a on the first epitaxial layer 116a, and the second conductive portion 126b and the second contact window 130b form a second contact structure 136b on the second epitaxial layer 116 b. The first contact structure 136a and the second contact structure 136b are separated by the second insulating portion 128 of the insulating structure 129. As such, the first epitaxial layer 116a and the first contact structure 136a in the first active region 100a electrically connected to the doped region 110a may be separated from the second epitaxial layer 116b and the second contact structure 136b in the second active region 100b electrically connected to the doped region 110b by the insulating structure 129.
Then, referring to fig. 1H, a first capacitor C1 electrically connected to the first contact structure 136a and a second capacitor C2 electrically connected to the second contact structure 136b are formed on the dielectric layer 114. In the present embodiment, the first capacitor C1 and the second capacitor C2 are cup-shaped capacitors, but the present invention is not limited thereto. The first and second capacitors C1 and C2 may each include a lower electrode E1, an upper electrode E2, and an insulating layer 138 formed between the lower electrode E1 and the upper electrode E2. Thus, the DRAM of the present invention is formed.
In the method for manufacturing the dynamic random access memory of the present invention, since the first insulating portion 120 is formed on the isolation structure 102 before the first conductive portion 126a and the second conductive portion 126b are formed, the first insulating portion 120 can be used as an etching stop layer in the process of etching the conductive layer 122, as shown in fig. 1E, without excessively etching the conductive layer 122, so that the first insulating portion 120 completely separates the first conductive portion 126a from the second conductive portion 126b, and damage to the first active region 100a and the second active region 100b is effectively avoided.
In addition, in the method for manufacturing the dynamic random access memory of the present invention, before forming the first insulating portion 120, an epitaxial growth process is performed to grow the first epitaxial layer 116a and the second epitaxial layer 116b on both sides of the isolation structure 102. The first epitaxial layer 116a and the second epitaxial layer 116b can be simply separated by the nature of the epitaxial growth process itself, so that additional process steps are not required to separate the two, and the first insulating portion 120 can be accurately formed on the isolation structure 102 between the first epitaxial layer 116a and the second epitaxial layer 116b in the subsequent steps.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified and altered by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW112147423 | 2023-12-06 | ||
| TW112147423A TWI874024B (en) | 2023-12-06 | 2023-12-06 | Manufacturing method of dynamic random access memory |
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| CN120111880A true CN120111880A (en) | 2025-06-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202311767974.8A Pending CN120111880A (en) | 2023-12-06 | 2023-12-19 | Method for manufacturing dynamic random access memory |
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| TW (1) | TWI874024B (en) |
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| TWI368315B (en) * | 2008-08-27 | 2012-07-11 | Nanya Technology Corp | Transistor structure, dynamic random access memory containing the transistor structure, and method of making the same |
| TWI578447B (en) * | 2015-10-14 | 2017-04-11 | 華邦電子股份有限公司 | Memory device and method of manufacturing the same |
| TWI696177B (en) * | 2019-10-02 | 2020-06-11 | 力晶積成電子製造股份有限公司 | Bit line structure for two-transistor static random access memory |
| TWI725767B (en) * | 2020-03-12 | 2021-04-21 | 力晶積成電子製造股份有限公司 | Memory structure and manufacturing method therefore |
| TWI749727B (en) * | 2020-08-24 | 2021-12-11 | 力晶積成電子製造股份有限公司 | Dynamic random access memory and method of forming the same |
| KR20240064189A (en) * | 2022-11-04 | 2024-05-13 | 삼성전자주식회사 | Memory core circuit having cell on periphery (CoP) structure and memory device including the same |
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2023
- 2023-12-06 TW TW112147423A patent/TWI874024B/en active
- 2023-12-19 CN CN202311767974.8A patent/CN120111880A/en active Pending
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| Publication number | Publication date |
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| TW202525009A (en) | 2025-06-16 |
| TWI874024B (en) | 2025-02-21 |
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