CN120106003B

CN120106003B - A method for repairing and improving power electromigration introduced by a power switching unit

Info

Publication number: CN120106003B
Application number: CN202510227605.2A
Authority: CN
Inventors: 游小春; 贺青
Original assignee: Tongji University
Current assignee: Tongji University
Priority date: 2025-02-27
Filing date: 2025-02-27
Publication date: 2025-10-31
Anticipated expiration: 2045-02-27
Also published as: CN120106003A

Abstract

The invention belongs to the field of integrated circuit design, and particularly relates to a method for repairing and improving power electromigration introduced by a power switch unit in an integrated circuit. The power supply layout above the power supply switch unit is arranged by adopting the scheme that one or more power supply VDD wires are arranged on M3 and M5 layers, one or more gate power supply longitudinal VDD_gate wires are distributed on the M3 and M5 longitudinal metal layers by taking normally open power supply VDD as the center, VSS wires are arranged nearby each VDD_gate wire in a matched mode, and the M2 layer is provided with a transverse VDD_gate wire, and the M2 layer transverse VDD_gate wire and the M3 layer longitudinal VDD_gate wire are connected through a through hole V23. The method directly improves the EM phenomenon above the power switch unit, prevents the EM violations from the power layout, and improves the robustness of the power supply, so that the whole power supply network is more robust.

Description

Method for repairing and improving electromigration of power supply introduced by power switch unit

Technical Field

The invention belongs to the field of integrated circuit design, and particularly relates to a method for repairing and improving power electromigration introduced by a power switch unit in an integrated circuit.

Background

Electrons collide with metal atoms when moving in the metal conductor, and the collision causes the metal atoms to move, that is, a shift phenomenon of the metal atoms. Over time, the metal atoms on the metal interconnect line undergo a large amount of movement, thereby causing localized metal atoms to accumulate or run off, which macroscopically manifests itself as deformation and fracture of the metal interconnect line. The metal atoms on the metal interconnection line are lost in a large quantity, so that the circuit break is generated at the place where the atoms are lost, the lost metal atoms are accumulated at other positions of the metal interconnection line, the interconnection line at the accumulated positions is widened or deformed, and at the moment, if the metal atoms are contacted with other metal interconnection lines, a short circuit is formed. This displacement of atoms caused by electromigration is referred to as electromigration (Electro Migration), and a series of phenomena that occur after the displacement of atoms.

The chip has electron migration, that is, EM phenomenon, as long as the chip is used. It is apparent that the deformation of the metal interconnect lines due to the EM phenomenon is irreversible. Thus, the longer the chip is used, the more the effects accumulated by the EM are, the more serious the degree of metal deformation, i.e. the greater the likelihood of open and short circuit of the metal interconnect. When the effects of EM build-up are sufficiently large, eventually leading to metal interconnect opens and shorts, the chip fails. The EM phenomenon is thus related to the lifetime of the chip and the depth of stability, as well as the fact that, in theory, the lifetime of the chip is limited.

The EM phenomenon is classified into PEM and SEM according to the carrier distinction. Electromigration that occurs on the PG (Power & group) interconnect is referred to as PEM, and electromigration that occurs on the signal line is referred to as SEM.

The low Power consumption is an important performance target of the digital chip, the low Power consumption of the chip is endless, and a Power Shutdown (PSO) technology is one of the low Power consumption technologies, and the technology achieves the purpose of reducing the Power consumption by shutting Off the Power supply voltage of a certain area or a certain sub-module which is temporarily not needed in the chip. One of the special standard units required for the Power-off technology is a Power switch unit (Power SWITCH CELL). The input of the power switch unit is normally open voltage, the output is turn-off control voltage, and the Power Electromigration (PEM) phenomenon caused by the large current output by the power switch unit is obvious abnormally, so that EM violations are easy to generate. Therefore, it is very important to the power supply structure or strategy above the power switching unit. The power supply is unreasonable in structure, PEM violations are easy to emerge, the number is large, the later repair difficulty is large, and the repair efficiency is low.

The existing EM violation solving method mainly realizes repairing by widening the violation net to increase the maximum current density bearing capacity, inserting a buffer unit to reduce the actual current density on the violation net and the like, and then adopts program automation for repairing so as to improve the repairing efficiency, reduce the manual repairing workload and mainly solve the SEM problem on the signal net in a concentrated way.

Although the common EM improvement repair methods in the industry can improve and repair EM violations in theory, for EM violations on low-layer metal M2 generated by a power switch unit due to the characteristic of high self current, the number of violations is large and difficult to repair, and for later periods of physical implementation, script repair cannot be realized, next manual repair is difficult to realize, and even if forced repair is performed, efficiency is extremely low and project progress is seriously affected. Secondly, manual repair cannot be quickly reproduced, if physical implementation is carried out again because of a certain unreliability factor, all EM repair actions only have to be repeated again, which is quite complicated and inefficient, and finally only can be repaired next to each other, and a plurality of iterations are required for truly repairing cleanly, which definitely further increases the design period.

Disclosure of Invention

Aiming at the problems existing in the prior art, the invention provides a method for repairing and improving the power supply electromigration introduced by a power supply switch unit, which mainly solves the problem of power supply electromigration violation caused by introducing the power supply switch unit in low-power physical implementation and improves the power supply electromigration phenomenon on low-layer metal above the power supply switch unit. The invention is suitable for repairing PEM problems above the power switch unit.

Technical proposal

A method for repairing and improving the electromigration of a power supply introduced by a power switch unit adopts the following scheme to arrange a power supply layout above the power switch unit:

one or more power supply VDD wires are arranged on M3 and M5 layers;

VSS wiring is matched and arranged near each VDD_gate wiring to form a VDD_gate and VSS power supply pair, so that the voltage network is uniformly distributed;

One or more gating power supply longitudinal VDD_gated net are distributed on the M3 and M5 longitudinal metal layers by taking the normally open power supply VDD as the center;

the M2 layer is provided with a transverse VDD_connected net, and the transverse VDD_connected net of the M2 layer and the longitudinal VDD_connected net of the M3 layer are connected through a through hole V23;

the output current is respectively output from the left side and the right side of the transverse M2 above the center of the power switch unit;

and the layout of the power supply network and the place where the power supply switch unit exists are used for carrying out power supply layout according to the scheme. Where no power switching unit is present, the conventional layout is followed.

Further, the implementation flow of the power supply layout is as follows:

step 1, firstly, positioning all power switch units according to unit types;

and 2, performing power layout according to the power supply structure of the power supply switch unit provided by the invention based on the physical position of the switch unit.

And 3, after the layout of all the power switch units is completed, wiring barriers (route blockage) are arranged above all the switch units again based on the physical positions of the switch units, and subsequent tools are prevented from wiring.

And 4, performing power layout on the rest areas at the same intervals according to the conventional power supply pairs (VDD_connected and VSS).

And 5, after all areas are powered on, removing all wiring obstacles so as to avoid influencing the subsequent signal layout and wiring behaviors.

Advantageous effects

The repairing and improving scheme of the EM violation proposed by the invention is also aimed at the current density, and has the advantages that the current is split through changing the power structure above the power switch unit and the change of the power structure, so that the effect of rapidly reducing the current density is realized, and the EM phenomenon on the voltage net is obviously improved. Through the change of the power supply structure, the EM phenomenon on the lower metal M2 above all power supply switch units is directly improved, the EM violations are prevented from the power supply layout, after the layout wiring is finished, the corresponding EM violations are not existed, the ECO burden in the later design stage is greatly lightened, and the design period is accelerated. In addition, the power supply structure also improves the robustness of the power supply, so that the whole power supply network is more robust.

Drawings

FIG. 1 is a schematic diagram of a conventional PG layout of a power switching unit;

FIG. 2 is a schematic diagram of the whole principle of the repairing method according to the embodiment of the invention;

FIG. 3 is a schematic diagram of an embodiment of an M1 layer power SWITCH CELL power I/O pin layout;

FIG. 4 is a schematic diagram of the power layouts M1, VIA12, M2 above the power switch unit according to the embodiment of the invention;

FIG. 5 is a schematic diagram of the power layouts M2, VIA23, M3 above the power switch unit according to the embodiment of the invention;

FIG. 6 is a schematic diagram of a power layout M3 above a power switch unit according to an embodiment of the invention;

FIG. 7 is a schematic diagram of the power layouts M3, VIA34, M4 above the power switch unit according to the embodiment of the invention;

FIG. 8 is a schematic diagram of the power layouts M4, VIA45, M5 above the power switch unit according to the embodiment of the invention;

FIG. 9 is a schematic diagram of a power layout M5 above a power switch unit according to an embodiment of the invention;

FIG. 10 is a schematic diagram of a power layout process according to the present invention.

Detailed Description

The technical scheme provided by the application is further described below with reference to specific embodiments and attached drawings. The advantages and features of the present application will become more apparent in conjunction with the following description.

Multiple layers of metal are often required in an IC physical implementation, with M _n representing the metal n-th layer and VIA _n,n+1 representing a VIA connecting between the metal n-th layer and the n+1 layer, in order to distinguish between the different metal layers. For example, M1 represents a first layer of metal, M2 represents a second layer of metal, VIA23 represents a VIA connecting between metal M2 and metal M3, and so on. The conventional power supply structure is characterized in that PG pins of units from the top layer to the bottom layer are downwards connected through holes, and the winding main directions of every two adjacent metal layers are crisscrossed from the third layer, namely the winding main directions of the odd layers are longitudinal, and the winding main directions of the even layers are transverse. The layout of the power supply structure is generally that each layer of metal on the middle and upper layers is uniformly distributed in the whole design area, adjacent layers form criss-cross power supply networks, the middle and lower layers penetrate downwards through power supply short wires or direct through holes to power supply tracks or power supply pins of the layers M2 and M1 (both the layers M2 and M1 are transverse), and therefore the power supply structure is actually a network shape in a three-dimensional space, and therefore the power supply structure is also called a power supply network layout.

As shown in fig. 1, a conventional power network layout of a power switching unit is shown, and in a low-power design, the power switching unit (power SWITCH CELL) controls the on-off of VDD power to the output power vdd_connected, and the power network layout near the power switching unit has a great influence on IREM (voltage drop, electromigration).

In the prior art, based on the input power supply VDD pin position of the power supply switching unit and the IREM of the normally-open power supply VDD, the VDD power supply is arranged above the VDD pin position as much as possible. And the output power vdd_connected is arranged beside (left in fig. 1).

The input end of the power switch unit is connected with VDD, and the connection line between the VDD_gate and the power switch unit is VDD_gate net, which comprises a transverse VDD_gate net and a longitudinal VDD_gate net;

specifically, VDD is one or more, and is arranged in M3 and M5 layers;

The transverse VDD_gated net is arranged on the M2 layer;

The number of the longitudinal VDD_connected net is one or more, and the longitudinal VDD_connected net is longitudinally arranged on the M3 layer and the M5 layer;

When the power switch unit is turned on, the output current flows to the output power supply vdd_gate through the vdd_gate net of the M2 layer. Since the current output from the power switch unit is large and is output from the low-layer metal M2 with a very narrow width, a large amount of output current flows along the vdd_gate of the M2 layer toward the vdd_gate high-layer power supply on the left side, so that a very small section of vdd_gate is easy to generate PEM violations, and even if the arrangement is very wide in the longitudinal direction vdd_gate of M3 and M5, it is still difficult to improve such PEM violations.

For the above design scenario, the following processing manner is adopted in this embodiment (as shown in fig. 2)

The power supply layout above the power supply switch unit is arranged according to a symmetrical structure, and is specific:

one or more power supply VDD wires are arranged on M3 and M5 layers;

the M2 layer is arranged with a transverse VDD_connected net, and the M2 layer transverse VDD_connected net and the M3 layer longitudinal VDD_connected net are connected through a through hole V23.

The output current is output from the lateral direction M2 above the center of the power switch unit to the left and right sides, respectively.

Furthermore, the VDD/longitudinal VDD_gate of the M3 layer and the M5 layer are parallel and aligned, through holes V34 and V45 are added at intervals in the wiring direction, and the through holes V34 and V45 are connected through a small section of transverse M4 connection line.

Further, the local transverse power line above the power switch unit is widened, wherein M2 is 2 times of line width, and M4 is short and wide. Only partially widening is performed above the power switch unit to reduce the use of winding resources and reduce the probability of DRC violations.

In the non-power switch unit area, the low-layer power interconnection line M2 to the middle-layer power supply M5 are directly connected through the through holes, so that the use of winding resources is reduced.

Further, the wiring (including VSS, VDD and VDD gates) on the M3 layer adopts a wider combination of a plurality of power lines, and the combination width is consistent with the width and coordinate position of the upper M5.

The M3 layer belongs to a main wiring layer of the signal wiring and also belongs to a low-layer wiring layer (the minimum line width allowed by the manufacturing process is smaller), and the disassembly of the power supply is facilitated by adopting the combination of a plurality of power supply lines. When the signal line wiring resources are tensed, a few M3 thin lines PG net can be cut off properly, so that the tense of the wiring resources is solved, the IR and EM cannot be influenced too much, and the wiring resources can be reserved for the later ECO or resources for solving DRC violations are arranged.

In summary, the layout of the layers of the power supply network near the power supply switch unit of the chip is as follows (as shown in FIG. 3-FIG. 9)

As shown in FIG. 3, the layout of the metal M1 layer comprises all pins of the power switch unit, namely the layout of an input power supply VDD pin, an output power supply VDD_gated pin and a ground power supply VSS pin of the power switch unit, and all the output pins of the unit are positioned on the metal M1 layer.

As shown in FIG. 4, M2 is arranged in the same way as M1, the main wiring layers are all transverse, the upper and lower layers of M1 and M2 are parallel, and the middle is connected through a plurality of through holes VIA 12.

Starting from the M3 layer, the directions of the main wiring layers of the adjacent layers are all vertically and horizontally alternated.

The M2 and M3 layers of the power network above the power switch unit are shown in FIG. 5, wherein the VDD_gate of the M2 layer is doubled in local width (no extra DRC violations are introduced) to increase the maximum current density carrying capacity;

as shown in fig. 6, a plurality of power supply combinations with wider layout on the M3 layer are arranged, and the combination width is consistent with the width and coordinate position of the upper M5. The M3 layer belongs to a main wiring layer of the signal wiring and also belongs to a low-layer wiring layer (the minimum line width allowed by the manufacturing process is smaller), and the disassembly of the power supply is facilitated by adopting a plurality of power supply combinations. When the signal line wiring resources are tensed, the thin lines PG net of a plurality of M3 can be reduced, so that the tense of the wiring resources is solved, the IR and the EM cannot be greatly influenced, and the method is equivalent to reserving a bit of wiring resources for the later ECO or solving resources on DRC violations.

As shown in fig. 7, the layout of the short transverse line is adopted for M4, and the width is widened to be twice or three times of the line width, so that the use of M4 wiring resources can be reduced, and the robustness of the power supply structure above the power switch unit can be ensured. As many VIA34 as possible connect M3 with M4.

As shown in fig. 8 and 9, the wider longitudinal PG power supply is arranged in the M5 layer, the power supply interconnection is continuously reinforced, and the width is consistent with the combined width and coordinate position of the PG net of the lower M3. The M5 layer belongs to a middle layer wiring layer, compared with the M3 layer, the wiring cost of the signal wire is reduced relatively, and a single wider power supply PG is adopted.

Since only the M3, M5 power supplies (wider power net combination or wider power net) are boosted over power SWITCH CELL, and the total area of power SWITCH CELL is only a small fraction of the total design area, this PG boost does not consume much of the winding resources.

By changing the power supply PG structure to lower the current density, and increasing PG of M2, M3, M5 to increase the upper limit of the allowable current density, the PEM improvement mentioned in FIG. 1 can be used to achieve the instant effect.

The power supply layout implementation flow is as follows:

step 1, firstly, positioning all power switch units according to unit types;

When a certain memory subsystem is physically implemented, IREM inspection analysis is performed by using the power layout structure shown in FIG. 1, and a large number of power supply EM violations related to the gate power supply VDD_gate exist on the lower metal M2 above the power supply switch unit, wherein the worst case is up to 200% (EM is measured by taking the percentage of the actual current and the maximum bearing current as a measure index, 100% or less is the requirement, and 100% or more is the exceeding of the standard, the EM violations occur, and the greater the percentage, the more serious the violations).

After the scheme of the invention is adopted, the related power supply EM is reduced to be within 80 percent, so that not only is all PEM violations repaired, but also the PEM of the whole PG network is greatly improved, and the robustness of the power supply network is enhanced.

The above description is only illustrative of the preferred embodiments of the application and is not intended to limit the scope of the application in any way. Any alterations or modifications of the application, which are obvious to those skilled in the art based on the teachings disclosed above, are intended to be equally effective embodiments, and are intended to be within the scope of the appended claims.

The following terms explain:

Claims

1. A method for repairing and improving power electromigration introduced by a power switching unit, characterized in that the power supply layout above the power switching unit is arranged as follows:

The power supply VDD wiring consists of one or more wires, arranged on layers M3 and M5.

On the vertical metal layers of M3 and M5, one or more gated power vertical VDD_gated nets are distributed on the left and right sides with the normally open power supply VDD as the center.

VSS wiring is arranged near each VDD_gated wiring to form a VDD_gated and VSS power supply pair, so that the voltage network is evenly distributed.

The horizontal VDD_gated net is arranged in layer M2, and the horizontal VDD_gated net of layer M2 and the vertical VDD_gated net of layer M3 are connected through via V23;

The output current is output from the horizontal M2 above the center of the power switch unit to the left and right sides respectively;

For the layout of the power network, where there are power switch units, the power layout shall be carried out according to the above scheme; where there are no power switch units, the conventional layout shall be followed.

2. The method for repairing and improving power electromigration introduced by a power switch unit as described in claim 1, characterized in that the local horizontal power lines above the power switch unit are widened: M2 is selected as twice the line width, and M4 is selected as a short-width line; the widening is only performed locally above the power switch unit.

3. The method for repairing and improving power electromigration introduced by a power switching unit as described in claim 2, characterized in that, in the non-power switching unit area, the low-level power interconnect M2 to the middle-level power M5 is directly connected through vias to reduce the use of winding resources.

4. The method for repairing and improving power electromigration introduced by the power switch unit as described in claim 1, characterized in that the wiring on the M3 layer adopts a combination of multiple wide power lines, and the combined width is consistent with the width and coordinate position of the M5 above.

5. The method for repairing and improving power electromigration introduced by a power switching unit as described in claim 1, characterized in that the VDD/vertical VDD_gated net of the M3 layer and the M5 layer are parallel and aligned; in the wiring direction, vias V34 and V45 are added at intervals, and the vias V34 and V45 are connected by a short horizontal M4 line.

6. A method for repairing and improving power electromigration introduced by a power switching unit as described in any one of claims 1-5, characterized in that the power layout implementation process is as follows:

Step 1: First, locate all power switch units by unit type;

Step 2, then based on the physical location of the switching unit, according to any of claims 1-5

A power layout scheme is provided above the power switch unit as described above;

Step 3: After completing the layout of all power switch units, based on the physical location of the switch units, install wiring obstacles above all switch units to prevent subsequent tools from wiring in these areas.

Step 4: Then, for the remaining area, perform the power supply layout at the same intervals as usual.

Step 5: After powering on all areas, remove all wiring obstacles to avoid affecting subsequent signal layout and wiring.