CN120089598A - High resistance resistor structure and design method thereof - Google Patents
High resistance resistor structure and design method thereof Download PDFInfo
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- CN120089598A CN120089598A CN202311632207.6A CN202311632207A CN120089598A CN 120089598 A CN120089598 A CN 120089598A CN 202311632207 A CN202311632207 A CN 202311632207A CN 120089598 A CN120089598 A CN 120089598A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
- H01L21/2236—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase from or into a plasma phase
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Abstract
The invention provides a high-resistance resistor structure and a design method thereof, wherein the high-resistance resistor structure comprises the steps of providing initial layout data of a pseudo-polysilicon layer, generating a corresponding metal high-resistance layer according to the pseudo-polysilicon layer, wherein the metal high-resistance layer is positioned on an insulating medium layer covering the pseudo-polysilicon layer, screening a metal resistor with a layout area larger than or equal to a preset value in the metal high-resistance layer as a first metal resistor, dividing the first pseudo-polysilicon corresponding to the first metal resistor into at least two second pseudo-polysilicon arranged at intervals, and taking layout data of the second pseudo-polysilicon as optimized layout data of the pseudo-polysilicon corresponding to the first metal resistor. The invention improves the flatness of the surface of the pseudo polysilicon after grinding, further improves the uniformity of the metal high-resistance resistor in-plane and local part, improves the performance of the metal high-resistance resistor, expands the process window of the corresponding grinding process, and is beneficial to improving the yield and the process stability.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-resistance resistor structure and a design method thereof.
Background
The high-resistance resistor is widely applied to an analog circuit due to the important function of voltage division and current limiting. In a process including a polysilicon gate structure, polysilicon is typically ion doped to form a high resistance resistor. In a process including a metal gate structure, a titanium nitride (TiN) film is generally used to prepare a high-resistance resistor (metal high-resistance resistor), and the resistance value of the high-resistance resistor can be regulated and controlled by the resistivity, the area and the thickness of the TiN film.
Taking design and preparation of a metal high-resistance resistor as an example, the design and preparation scheme comprises the steps of sequentially growing a silicon oxide film and a titanium nitride film on the surface of a substrate after a metal grid structure is formed on the substrate, and forming the titanium nitride film into a required high-resistance resistor layer through photoetching and etching processes. For the high-resistance resistor with a part of narrower process window, the problems of mismatch resistance, signal attenuation, noise increase, power loss and the like are easy to exist, so that yield loss is caused.
Disclosure of Invention
The invention aims to provide a high-resistance resistor structure and a design method thereof, which are used for improving the uniformity of the whole and part of the high-resistance resistor so as to improve the performance and the preparation yield of the high-resistance resistor.
In order to solve the above technical problems, the design method of the high-resistance resistor structure provided by the invention comprises the following steps:
providing initial layout data of a pseudo polysilicon layer;
Generating a corresponding metal high-resistance layer according to the pseudo-polysilicon layer, wherein the metal high-resistance layer is positioned on an insulating medium layer covering the pseudo-polysilicon layer;
And screening a metal resistor with a layout area larger than or equal to a preset value in the metal high-resistance layer as a first metal resistor, dividing first pseudo polysilicon corresponding to the first metal resistor into at least two second pseudo polysilicon arranged at intervals, and taking layout data of the second pseudo polysilicon as optimized layout data of the pseudo polysilicon layer corresponding to the first metal resistor.
Optionally, when the corresponding metal high-resistance layer is generated according to the pseudo-polysilicon layer, the layout area of the metal resistance layer is larger than or equal to the initial layout area of the corresponding pseudo-polysilicon layer.
Optionally, the dummy polysilicon layer and the metal gate layer belong to the same layer of the layout structure, and the dummy polysilicon in the dummy polysilicon layer and the metal resistor in the metal high-resistance layer are rectangular.
Optionally, the preset value is 0.2 square micrometers.
Optionally, the sum of the layout areas of the second dummy polysilicon after the division is greater than or equal to 20% of the layout area of the corresponding first dummy polysilicon.
Optionally, the width of the first dummy polysilicon is greater than or equal to 0.2 micron, the width of the second dummy polysilicon is greater than or equal to 0.025 micron, and the spacing between adjacent second dummy polysilicon in the width direction is greater than or equal to 0.08 micron.
Optionally, the length of the first dummy polysilicon is greater than or equal to 1 micron, the length of the second dummy polysilicon is greater than or equal to 0.1 micron, and the distance between adjacent second dummy polysilicon in the length direction is greater than or equal to 0.02 micron.
Optionally, the layout area of the second dummy polysilicon is 0.01 square micrometers to 0.05 square micrometers.
Optionally, at least two of the second dummy polysilicon have the same shape and size, and are uniformly arranged under the corresponding first metal resistor.
In accordance with another aspect of the present invention, there is also provided a high resistance structure including:
A substrate;
At least two pseudo polysilicon arranged at intervals and arranged on the substrate;
an insulating medium layer covering the substrate and the pseudo polysilicon;
And the metal high-resistance resistor is positioned on the insulating medium layer, and one metal high-resistance resistor corresponds to at least two pseudo polycrystalline silicon positioned below the metal high-resistance resistor.
In summary, the method generates the corresponding metal high-resistance layer according to the initial layout data of the pseudo-polysilicon layer, the metal high-resistance layer is arranged on the insulating medium layer covering the pseudo-polysilicon layer, the metal resistor in the metal high-resistance layer is used as a high-resistance structure, the metal resistor with the layout area larger than or equal to a preset value in the metal high-resistance layer is screened as a first metal resistor, the first pseudo-polysilicon corresponding to the first metal resistor is divided into at least two second pseudo-polysilicon arranged at intervals, and the layout data of the second pseudo-polysilicon is used as the optimized layout data of the pseudo-polysilicon corresponding to the first metal resistor. Therefore, in the invention, the first pseudo polysilicon with larger area (size) is screened out and is divided into at least two second pseudo polysilicon which are smaller and are arranged at intervals, so as to balance the grinding process load effect of the area, thereby improving the flatness (uniformity) of the surface of the pseudo polysilicon after grinding when the pseudo polysilicon is ground, further improving the local uniformity and the overall uniformity of the metal high-resistance resistor, improving the performance of the metal high-resistance resistor, expanding the process window of the corresponding grinding process, and being beneficial to improving the yield and the process stability. In addition, the optimization can be performed in the layout data processing stage, no adverse effect is caused on the metal high-resistance layer and other subsequent layouts, meanwhile, the process and the process variation are not involved at all, and the method has high operability and practicability.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation on the scope of the invention.
FIG. 1 is a flow chart of a design method of a high-resistance resistor structure according to a first embodiment;
Fig. 2a to fig. 2f are schematic structural diagrams corresponding to the corresponding steps of the design method of the high-resistance structure according to the first embodiment.
In the accompanying drawings:
10-substrate, 11-isolation dielectric layer, 20-dummy polysilicon layer, 21-dummy polysilicon, 22-first dummy polysilicon, 23-second dummy polysilicon, 30-insulating dielectric layer, 40-metal high resistance layer, 41-metal resistor and 42-first metal resistor.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.
Example 1
Fig. 1 is a flowchart of a design method of a high-resistance resistor structure according to a first embodiment.
As shown in fig. 1, a method for designing a high-resistance resistor structure according to an embodiment includes:
s01, providing initial layout data of a pseudo polysilicon layer;
S02, generating a corresponding metal high-resistance layer according to the pseudo-polysilicon layer, wherein the metal high-resistance layer is positioned on a dielectric layer covering the pseudo-polysilicon layer;
And S03, screening a metal resistor with a layout area larger than or equal to a preset value in the metal high-resistance layer as a first metal resistor, dividing a first pseudo polysilicon corresponding to the first metal resistor into at least two second pseudo polysilicon arranged at intervals, and taking layout data of the second pseudo polysilicon as optimized layout data of the pseudo polysilicon corresponding to the first metal resistor.
Fig. 2a to 2f are schematic structural diagrams corresponding to the corresponding steps of the method for designing a high-resistance resistor structure according to the present embodiment, and the method for designing a high-resistance resistor structure will be described in detail with reference to fig. 2a to 2 f.
First, referring to fig. 2a, step S01 is performed to provide initial layout data of the dummy polysilicon layer 20.
The initial layout data is typically provided by the customer to the Fab, which designs the layout of each layer and each structure according to the initial layout data for delivery to the reticle supplier for preparation of the corresponding reticle. For easy understanding, the present embodiment converts two-dimensional layout data into a corresponding stereoscopic film structure (schematic cross-sectional view).
With continued reference to fig. 2a, the dummy polysilicon layer 20 and the metal gate layer (not shown, dummy gate structure) belong to the same layer of the layout structure (three-dimensional film structure), are all disposed on the substrate 10, and are isolated by using an isolation dielectric layer. The dummy polysilicon in the dummy polysilicon layer 20 and the metal gate in the metal gate layer may have similar structures, for example, including a number of polysilicon (e.g., dummy polysilicon 21) and a dielectric layer (not shown) surrounding the dummy polysilicon 21 along sidewalls (e.g., sidewall layers), bottom walls (e.g., gate dielectric layers). Wherein, the several dummy polysilicon 21 of the dummy polysilicon layer 20 may have the same thickness, and the cross-sectional shape (top view) of the dummy polysilicon 21 may be rectangular or a combination of several rectangles. In this embodiment, the dummy polysilicon 21 may have a rectangular shape, and fig. 2a shows three dummy polysilicon 21 of different sizes (e.g., different widths).
Next, referring to fig. 2b, a corresponding metal high-resistance layer 40 is formed according to the dummy polysilicon layer 20, and the metal high-resistance layer 40 is located on the insulating dielectric layer 30 covering the dummy polysilicon layer 20, and the metal resistor 41 in the metal high-resistance layer 40 is used as the high-resistance resistor.
Before forming the metal high-resistance layer 40, the structure of the insulating dielectric layer 30 may be formed first, the insulating dielectric layer 30 covers the surfaces of the dummy polysilicon layer 20 and the metal gate layer, and then the layout of the metal high-resistance layer 40 is formed on the structure of the insulating dielectric layer 30, and the layout data of the metal high-resistance layer 40 corresponds to the layout data of the dummy polysilicon layer 20. Specifically, similar to the dummy polysilicon layer 20, the metal high resistance layer 40 may include a plurality of metal resistors 41 (metal high resistance resistors) disposed at intervals, the plurality of metal resistors 41 having the same thickness, each metal resistor 41 having a shape and size close to those of the underlying (corresponding) dummy polysilicon 21 for subsequent electrical extraction. In the present embodiment, the metal resistor 41 and the corresponding dummy polysilicon 21 are rectangular and have similar dimensions (areas), and fig. 2b shows the metal resistor 41 corresponding to the dummy polysilicon 21 with three different dimensions.
The preparation process corresponding to the layout design process may include, for example, removing polysilicon in the metal gate layer to form a gate trench, filling a metal gate material layer (including a corresponding work function layer and a metal layer) above the isolation dielectric layer 11 and the dummy polysilicon layer 20 in the gate trench, performing a polishing process to remove the metal gate material layer outside the gate trench (i.e., removing the metal gate material layer on the isolation dielectric layer 11 and the dummy polysilicon layer 20 and polishing the surface of the dummy polysilicon), sequentially forming an insulating dielectric layer 30 (e.g., silicon oxide) and a high-resistance metal material layer (e.g., titanium nitride) to cover the metal gate layer and the dummy polysilicon layer 20, and performing a photolithography and etching process on the high-resistance metal material layer to form a corresponding metal resistor.
Next, referring to fig. 2c, a metal resistor with a layout area greater than or equal to a preset value in the metal high-resistance layer 40 is selected as the first metal resistor 42, the first dummy polysilicon 22 corresponding to the first metal resistor 42 is divided into at least two second dummy polysilicon 23 arranged at intervals, and the layout data of the second dummy polysilicon 23 is used as the optimized layout data of the dummy polysilicon corresponding to the first metal resistor 42.
As is clear from the above-mentioned preparation process corresponding to layout information, the metal resistor 41 is covered on the insulating dielectric layer 30, the insulating dielectric layer 30 is covered on the dummy polysilicon 21, and the surface flatness of the dummy polysilicon 21 is determined by the polishing effect, so that the polishing effect (surface flatness) of the dummy polysilicon 21 is improved, and the uniformity in the metal resistor surface and locally) and the uniformity (overall) between different metal resistors, that is, the performance and the preparation yield of the metal resistor, can be improved. For this reason, in the present embodiment, a metal resistor with a larger size (area) (for example, a preset value) is selected from the metal high-resistance layer 40 as the first metal resistor 42, then the dummy polysilicon corresponding to the first metal resistor 42 is selected as the first dummy polysilicon 22, and the first dummy polysilicon 22 is divided into at least two second dummy polysilicon 23 arranged at intervals, so as to improve the polishing load effect when polishing the dummy polysilicon 21, and to improve the flatness (uniformity) of the surface of the dummy polysilicon 21 after polishing. It should be appreciated that the first dummy polysilicon 22 is selected to have a larger size than other regions (metal gate or smaller dummy polysilicon 21), to be more prone to surface irregularities (loading effect) after the grinding process, and that the first metal resistor 42 has a larger size than other regions (smaller metal resistor) to be more affected by the surface irregularities of the insulating dielectric layer 30.
In the present embodiment, the dummy polysilicon 21 and the metal resistor 41 may each have a rectangular shape, and have the same length direction and width direction as those of the metal gate layer. The layout area of the first metal resistor 42 may be greater than or equal to 0.2 square micrometers, that is, the layout area of the first dummy polysilicon 22 is greater than or equal to 0.2 square micrometers, after the first dummy polysilicon 22 is divided into at least two second dummy polysilicon 23, the second dummy polysilicon 23 are still arranged at intervals in the area where the original first dummy polysilicon 22 is located, and of course, the sum of the layout areas of the divided second dummy polysilicon is smaller Yu Yuandi by the layout area of the dummy polysilicon 22, but is greater than or equal to 20% of the layout area of the corresponding first dummy polysilicon, and the size and the interval distance of the second dummy polysilicon 23 still need to conform to the corresponding feature size and design rule.
In an example, referring to the top view (only the dummy polysilicon layer is shown) shown in fig. 2d, the width direction (X-direction) and the length direction (Y-direction) of the first polysilicon are the same as the width direction and the length direction of the metal gate, the width of the first dummy polysilicon 22 (the first metal resistor 42) may be greater than or equal to 0.2 micrometer, the first dummy polysilicon 22 is divided along the width direction, the width of the second dummy polysilicon 23 is greater than or equal to 0.025 micrometer, and the spacing between adjacent second dummy polysilicon 23 along the width direction after the division is greater than or equal to 0.08 micrometer.
In an example, referring to the top view shown in fig. 2e (only the dummy polysilicon layer is shown), the length of the first dummy polysilicon 22 is greater than or equal to 1 micron, the first dummy polysilicon 22 is divided along the length direction, the length of the second dummy polysilicon 23 is greater than or equal to 0.1 micron, and the spacing distance between adjacent second dummy polysilicon 23 along the length direction after separation is greater than or equal to 0.02 micron.
In an example, referring to the top view shown in fig. 2f (only the dummy polysilicon layer is shown), the area of the first dummy polysilicon 22 is greater than or equal to 0.2 square microns, the first dummy polysilicon 22 is divided along the length direction and/or the width direction, the area of the second dummy polysilicon 23 may be between 0.01 square microns and 0.05 square microns, and the divided second dummy polysilicon 23 is arranged in an array.
In particular, the length, width or area of each of the second dummy polysilicon 23 divided by the first dummy polysilicon 22 may be set according to actual polishing conditions, respectively, to further improve in-plane uniformity.
Taking the optimized layout information of the second pseudo polysilicon and the layout information of the unselected (not adjusted) pseudo polysilicon as the layout information of the pseudo polysilicon layer, performing mask data inspection on the layout information of the pseudo polysilicon layer, and providing the mask to a mask provider for preparing a mask after confirming the mask data inspection. In the process, the optimization can be performed in the layout data processing stage, no adverse effect is caused on the metal high-resistance layer and other subsequent layouts, and the surface flatness of the metal high-resistance resistor can be improved without involving the change of the process, so that the local and whole uniformity of the metal high-resistance resistor is improved, the performance of the metal high-resistance resistor is improved, the process window of the corresponding grinding process is expanded, and the yield and the process stability are improved.
Example two
The second embodiment provides a high-resistance resistor structure.
The high-resistance resistor structure provided in the second embodiment comprises a substrate, a pseudo-polysilicon layer, an insulating dielectric layer and a metal high-resistance layer. The dummy polysilicon layer is arranged on the substrate and comprises at least two dummy polysilicon layers which are arranged at intervals, and isolation medium layers are arranged between the dummy polysilicon layers of the dummy polysilicon layer for isolation. The insulating dielectric layer covers the surfaces of the substrate, the dummy polysilicon and the isolation dielectric layer. The metal high-resistance layer is arranged on the insulating medium layer and comprises a plurality of metal high-resistance resistors (metal resistors), wherein the metal high-resistance resistor at least comprises one metal high-resistance resistor with larger size (area), and at least two pseudo polycrystalline silicon arranged at intervals are arranged below the insulating medium layer and correspond to the metal high-resistance resistor. Of course, there is also a part of a metal high-resistance resistor with smaller size, and only one pseudo polysilicon corresponds to the lower part of the resistor.
In summary, the method generates the corresponding metal high-resistance layer according to the initial layout data of the pseudo-polysilicon layer, the metal high-resistance layer is arranged on the insulating medium layer covering the pseudo-polysilicon layer, the metal resistor in the metal high-resistance layer is used as a high-resistance structure, the metal resistor with the layout area larger than or equal to a preset value in the metal high-resistance layer is screened as a first metal resistor, the first pseudo-polysilicon corresponding to the first metal resistor is divided into at least two second pseudo-polysilicon arranged at intervals, and the layout data of the second pseudo-polysilicon is used as the optimized layout data of the pseudo-polysilicon corresponding to the first metal resistor. Therefore, in the invention, the first pseudo polysilicon with larger area (size) is screened out and is divided into at least two second pseudo polysilicon which are smaller and are arranged at intervals, so as to balance the grinding process load effect of the area, thereby improving the flatness (uniformity) of the surface of the pseudo polysilicon after grinding when the pseudo polysilicon is ground, further improving the local uniformity and the overall uniformity of the metal high-resistance resistor, improving the performance of the metal high-resistance resistor, expanding the process window of the corresponding grinding process, and being beneficial to improving the yield and the process stability. In addition, the optimization can be performed in the layout data processing stage, no adverse effect is caused on the metal high-resistance layer and other subsequent layouts, meanwhile, the process and the process variation are not involved at all, and the method has high operability and practicability.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. The design method of the high-resistance resistor structure is characterized by comprising the following steps of:
providing initial layout data of a pseudo polysilicon layer;
Generating a corresponding metal high-resistance layer according to the pseudo-polysilicon layer, wherein the metal high-resistance layer is positioned on an insulating medium layer covering the pseudo-polysilicon layer;
And screening a metal resistor with a layout area larger than or equal to a preset value in the metal high-resistance layer as a first metal resistor, dividing first pseudo polysilicon corresponding to the first metal resistor into at least two second pseudo polysilicon arranged at intervals, and taking layout data of the second pseudo polysilicon as optimized layout data of the pseudo polysilicon layer corresponding to the first metal resistor.
2. The method for designing a high-resistance resistor structure according to claim 1, wherein when a corresponding metal high-resistance layer is generated according to the dummy polysilicon layer, a layout area of the metal resistance layer is larger than or equal to an initial layout area of the corresponding dummy polysilicon layer.
3. The method for designing a high-resistance resistor structure according to claim 1, wherein the dummy polysilicon layer and the metal gate layer belong to the same layer of the layout structure, and the dummy polysilicon in the dummy polysilicon layer and the metal resistor in the metal high-resistance layer are rectangular.
4. A method of designing a high resistance resistor structure according to claim 3, wherein the predetermined value is 0.2 square microns.
5. The method of designing a high-resistance resistor structure according to claim 4, wherein a sum of layout areas of the second dummy polysilicon after division is greater than or equal to 20% of the layout area of the corresponding first dummy polysilicon.
6. The method of claim 4, wherein the width of the first dummy polysilicon is greater than or equal to 0.2 μm, the width of the second dummy polysilicon is greater than or equal to 0.025 μm, and the spacing between adjacent second dummy polysilicon in the width direction is greater than or equal to 0.08 μm.
7. The method of claim 4, wherein the first dummy polysilicon has a length greater than or equal to 1 micron, the second dummy polysilicon has a length greater than or equal to 0.1 micron, and the adjacent second dummy polysilicon has a spacing in the length direction greater than or equal to 0.02 micron.
8. The method for designing a high-resistance resistor structure according to any one of claims 4 to 7, wherein the layout area of the second dummy polysilicon is 0.01 to 0.05 square micrometers.
9. The method of claim 1, wherein at least two of the second dummy polysilicon have the same shape and size and are uniformly disposed under the corresponding first metal resistor.
10. A high resistance resistor structure, comprising:
A substrate;
At least two pseudo polysilicon arranged at intervals and arranged on the substrate;
an insulating medium layer covering the substrate and the pseudo polysilicon;
And the metal high-resistance resistor is positioned on the insulating medium layer, and one metal high-resistance resistor corresponds to at least two pseudo polycrystalline silicon positioned below the metal high-resistance resistor.
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| CN202311632207.6A CN120089598A (en) | 2023-11-30 | 2023-11-30 | High resistance resistor structure and design method thereof |
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| CN202311632207.6A CN120089598A (en) | 2023-11-30 | 2023-11-30 | High resistance resistor structure and design method thereof |
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