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CN120029951A - SRIO multi-channel communication method and system based on FC equipment - Google Patents

SRIO multi-channel communication method and system based on FC equipment Download PDF

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Publication number
CN120029951A
CN120029951A CN202410702013.7A CN202410702013A CN120029951A CN 120029951 A CN120029951 A CN 120029951A CN 202410702013 A CN202410702013 A CN 202410702013A CN 120029951 A CN120029951 A CN 120029951A
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data
module
srio
framing
sending
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Inventor
马文林
孙佳
胡佳佳
李昱琨
吴炎奇
何逸君
徐磊
付文生
崔艳杰
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Nanjing Quanxin Cable Technology Co Ltd
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Nanjing Quanxin Cable Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/382Information transfer, e.g. on bus using universal interface adapter
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/4031Coupling between buses using bus bridges with arbitration
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/50Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

本发明提供一种基于FC设备的SRIO多通道通信方法与系统,利用FPGA为协议转换提供的可编程和并行处理数据的优越平台,提供一种基于FC设备的SRIO多通道通信方法与系统,基于FC设备的SRIO多通道的通信,借助FPGA技术实现高效的协议转换。本发明提出的基于FC设备的SRIO多通道通信方法与系统中,通过多通道排序的应用,进一步优化通信效率,提供更高性能和低延迟的通信解决方案,适用于各种高性能的通讯系统,满足日益增长的数据交换与通讯需求。

The present invention provides a SRIO multi-channel communication method and system based on FC equipment, and utilizes the superior platform of programmable and parallel data processing provided by FPGA for protocol conversion, and provides a SRIO multi-channel communication method and system based on FC equipment, and realizes efficient protocol conversion by means of FPGA technology based on SRIO multi-channel communication of FC equipment. In the SRIO multi-channel communication method and system based on FC equipment proposed by the present invention, through the application of multi-channel sorting, the communication efficiency is further optimized, and a communication solution with higher performance and low latency is provided, which is applicable to various high-performance communication systems and meets the growing data exchange and communication needs.

Description

SRIO multichannel communication method and system based on FC equipment
Technical Field
The invention relates to the technical field of FC network communication, in particular to an SRIO multichannel communication method and system based on FC equipment.
Background
Currently, the demands of communication systems for high performance, multi-Channel, low latency continue to grow, and SERIAL RAPID IO (SRIO) and Fibre Channel (FC) communication protocols respectively play an important role in different fields.
The SRIO communication protocol is a high-performance serial bus protocol, and is intended to implement fast and reliable data communication between a plurality of processors, DSPs (digital signal processors), FPGAs (field programmable gate arrays), and other devices. The SRIO protocol supports multi-channel communication, the bandwidth of each channel can reach more than 10Gbps, the requirement of high-speed data transmission is met, and the SRIO protocol is commonly used for high-performance computing and embedded systems. The FC communication protocol is widely applied to storage networks, data centers and high-performance storage, has the advantages of channel and network, has the capabilities of high bandwidth, high reliability, high stability, electromagnetic interference resistance and the like, and adopts an optical fiber medium as main connecting equipment so as to meet the requirements of long-distance transmission and electromagnetic interference prevention.
Conventional protocol conversion methods typically require dedicated hardware or multiple processing units, which increases system complexity and cost, for example, conversion between FC protocols and SRIO protocols, and protocol conversion systems that rely on dedicated hardware are often difficult to maintain and upgrade, requiring the entire hardware unit to be upgraded and replaced when new protocols are required to support or improve the performance of existing protocols. Meanwhile, the use of a plurality of processing units for protocol conversion may result in resource waste. Different processing units may be activated at different points in time, resulting in uneven utilization of the overall system resources, which in turn affects the performance and efficiency of the system. Although the data format and signal conversion between the FC and SRIO protocols can be directly processed by means of hardware conversion (such as a dedicated hardware conversion device or a conversion chip) to achieve high-performance and low-delay conversion, the above-mentioned disadvantages of maintenance upgrade and resource utilization exist at the same time, and complex hardware design and implementation are involved.
Disclosure of Invention
In view of the drawbacks and deficiencies of the prior art, according to a first aspect of the present invention, there is provided an SRIO multi-channel communication system based on FC devices, comprising:
The SRIO_IP core is used for receiving SRIO frame data input and converting the SRIO frame data input into AXIS interface data output;
the SRIO_CTRL control module is used for controlling conversion between an SRIO protocol frame and AXIS interface data, and comprises the steps of analyzing the AXIS interface data, framing the data frames based on data of different FC types, dividing and grouping the data based on the analysis result of a received FC data packet, converting the data into AXIS interface data, and sending the AXIS interface data to the SRIO_IP core;
the arbitration module comprises a sending arbitration module and a receiving arbitration module, and is respectively used for request arbitration of a sending direction and a receiving direction;
the flow_ctrl transmitting/receiving control module is used for controlling the transmission of the data frames after framing and analyzing and buffering the received FC data packets;
the SRIO_CTRL control module comprises a T port serving as a transmitting side module, an I port serving as a receiving side, a sequencing module and a framing module, wherein the FLOW_CTRL transmitting/receiving control module comprises a plurality of transmitting modules corresponding to different FC types;
in the data sending direction, the T port is used for analyzing the AXIS interface data output data and extracting frame header information of SRIO frame data as a descriptor, wherein the descriptor comprises a TID, a type, an address and a data length;
the sequencing module is used for mapping the address and the channel according to the descriptor, sequencing according to TID fields under different channels, sending the analyzed data into a designated RAM for caching, judging the FC type of the protocol frame, and adding the FC type into the descriptor;
The framing module is used for framing the data according to the protocol frame format corresponding to the FC type through the FC type in the pre-reading descriptor, sending the framed data into the arbitration module, arbitrating by the sending arbitration module, and sending the data out of the sending module corresponding to the FC type;
In the data receiving direction, the flow_ctrl sending/receiving control module receives an FC data packet from an FC switching network, and obtains data and a descriptor after analysis;
After the receiving arbitration module performs arbitration of the receiving module, the framing module pre-reads the descriptor obtained by analysis, searches the address according to the relation between the channel and the address, segments and packages the data according to the length of the data to obtain a plurality of data packages corresponding to the SRIO frame head, and finally obtains a data frame conforming to an AXIS protocol through I port conversion and sends the data frame to the SRIO_IP core;
The SRIO_IP core, the SRIO_CTRL control module, the arbitration module and the flow_CTRL sending/receiving control module are all configured inside the FPGA of the FC device.
As an alternative embodiment, the sorting module is configured to obtain channel numbers based on a mapping relationship between addresses and channel numbers, thereby determining one channel number corresponding to each frame data. The mapping relation is configured through a blueprint, and after the FPGA of the FC equipment is powered on, the blueprint flash information is read for configuration.
As an alternative embodiment, the sorting module is configured to sort and buffer data in the following manner:
defining a description field of incomplete transactions in each pair of source ID/target ID in the SRIO HELLO frame, sequencing the HELLO frame according to the field, and TID epsilon [0,255];
setting 3 pointers, namely p_wr, p_rd and p_rd_next respectively, wherein p_wr is a write pointer, p_rd is a read pointer and p_rd_next is a pre-read pointer;
Using TID as data RAM address, HELLO frame payload as data RAM content, sequentially storing in data RAM;
taking TID as an address of a mark RAM, taking 1 or 0 as the content of the mark RAM, and initially marking the content as 0, marking the corresponding content as 1 when a HELLO frame corresponding to the TID is received, and resetting the content marking corresponding to the TID when data is sent to a lower level;
When judging that the corresponding mark contents of the positions pointed by the p_rd and the p_rd_next are 1, sending the data RAM contents on the p_rd position to a lower stage, adding 1 to the p_rd and the p_rd_next, and simultaneously clearing the mark contents;
And stopping sending until the write pointer p_wr catches up with p_rd when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, sending the residual data content on the p_rd position to the lower stage, adding 2 to the p_rd and p_rd_next pointers simultaneously, and exceeding the pointer position where data is not received for a long time, and after exceeding, continuing judging the data receiving condition according to the previous flow to finish the cyclic sequencing operation.
As an optional implementation manner, after the ordering module finishes the ordering of the data, the data is sent to the Payload fifo of the flow_ctrl sending/receiving control module for buffering according to different channels, where:
the FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read descriptors in Payload fifo to judge whether cached data corresponds to FC ASM protocol data, FC 818 protocol data or data sent by both paths;
After the framing module reads the data, the FC ASM framing module and the FC 818 framing module carry out framing according to respective protocol frame formats, the framing is sent into the sending arbitration module for arbitration after finishing framing, and the data is sent out through the corresponding sending modules after the arbitration is finished;
wherein, the FC ASM protocol frames under all channels arbitrate together and the FC 818 protocol frames under all channels arbitrate together.
According to a second aspect of the object of the present invention, there is also provided an SRIO multi-channel communication method based on an FC device, comprising the steps of:
In the data transmission direction, after receiving SRIO frame data input, the SRIO_IP core is converted into AXIS interface data output;
The T port analyzes AXIS interface data output data, and extracts frame header information of SRIO frame data as a descriptor, wherein the descriptor comprises a TID, a type, an address and a data length;
The sequencing module maps the address and the channel according to the descriptor, sequences the analyzed data according to TID fields under different channels, sends the analyzed data into a designated RAM for caching, judges the FC type of the protocol frame and adds the FC type into the descriptor;
The FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read descriptors, judge that the cached data corresponds to FC ASM protocol data, FC 818 protocol data or data transmitted by both paths, then framing the FC ASM framing module and the FC 818 framing module according to respective protocol frame formats, sending the FC ASM framing module and the FC 818 framing module into a transmission arbitration module for arbitration after framing is finished, and respectively transmitting the FC ASM framing module and the FC 818 framing module through the corresponding transmission module after the data is arbitrated;
In the data receiving direction, a first sending module based on an FC ASM protocol and a second sending module based on an FC 818 protocol in a flow_CTRL sending/receiving control module receive FC data packets from an FC switching network, and data and descriptors are obtained after analysis;
After the receiving arbitration module performs arbitration of the receiving module, the framing module pre-reads the descriptor obtained by analysis, searches the address according to the relation between the channel and the address, segments and packs the data according to the length of the data to obtain a plurality of data packets corresponding to the SRIO frame head, and finally obtains a data frame conforming to the AXIS protocol through I port conversion and sends the data frame to the SRIO_IP core.
As an optional implementation manner, the sorting module obtains channel numbers based on a mapping relation between addresses and channel numbers, so that one channel number corresponding to each frame of data is determined, wherein the mapping relation is configured through a blueprint, and after an FPGA of the FC device is powered on, the blueprint flash information is read for configuration.
As an alternative embodiment, the sorting module is configured to sort and buffer data in the following manner:
defining a description field of incomplete transactions in each pair of source ID/target ID in the SRIO HELLO frame, sequencing the HELLO frame according to the field, and TID epsilon [0,255];
setting 3 pointers, namely p_wr, p_rd and p_rd_next respectively, wherein p_wr is a write pointer, p_rd is a read pointer and p_rd_next is a pre-read pointer;
Using TID as data RAM address, HELLO frame payload as data RAM content, sequentially storing in data RAM;
taking TID as an address of a mark RAM, taking 1 or 0 as the content of the mark RAM, and initially marking the content as 0, marking the corresponding content as 1 when a HELLO frame corresponding to the TID is received, and resetting the content marking corresponding to the TID when data is sent to a lower level;
When judging that the corresponding mark contents of the positions pointed by the p_rd and the p_rd_next are 1, sending the data RAM contents on the p_rd position to a lower stage, adding 1 to the p_rd and the p_rd_next, and simultaneously clearing the mark contents;
And stopping sending until the write pointer p_wr catches up with p_rd when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, sending the residual data content on the p_rd position to the lower stage, adding 2 to the p_rd and p_rd_next pointers simultaneously, and exceeding the pointer position where data is not received for a long time, and after exceeding, continuing judging the data receiving condition according to the previous flow to finish the cyclic sequencing operation.
In combination with the SRIO multi-channel communication method and system based on the FC equipment, the invention aims to provide the SRIO multi-channel communication method and system based on the FC equipment by utilizing the FPGA to provide a superior platform for programmable and parallel data processing for protocol conversion, and the SRIO multi-channel communication based on the FC equipment realizes efficient protocol conversion by virtue of the FPGA technology. In the SRIO multichannel communication method and system based on the FC equipment, the communication efficiency is further optimized through the application of multichannel sequencing, a communication solution with higher performance and low delay is provided, the method and system are suitable for various high-performance communication systems, and the ever-increasing data exchange and communication requirements are met.
It should be understood that all combinations of the foregoing concepts, as well as additional concepts described in more detail below, may be considered a part of the inventive subject matter of the present disclosure as long as such concepts are not mutually inconsistent. In addition, all combinations of claimed subject matter are considered part of the disclosed inventive subject matter.
The foregoing and other aspects, embodiments, and features of the present teachings will be more fully understood from the following description, taken together with the accompanying drawings. Other additional aspects of the invention, such as features and/or advantages of the exemplary embodiments, will be apparent from the description which follows, or may be learned by practice of the embodiments according to the teachings of the invention.
Drawings
The drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Embodiments of various aspects of the invention will now be described, by way of example, with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of an SRIO multi-channel communication system based on FC devices according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a sorting flow in a single channel according to an embodiment of the present invention.
FIG. 3 is a block diagram of a multi-channel data framing and arbitration scheme according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a transmission direction data processing flow according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a receiving direction data processing flow according to an embodiment of the present invention.
Detailed Description
For a better understanding of the technical content of the present invention, specific examples are set forth below, along with the accompanying drawings.
Aspects of the invention are described in this disclosure with reference to the drawings, in which are shown a number of illustrative embodiments. The embodiments of the present disclosure are not necessarily intended to include all aspects of the invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, may be implemented in any of a number of ways, as the disclosed concepts and embodiments are not limited to any implementation. Additionally, some aspects of the disclosure may be used alone or in any suitable combination with other aspects of the disclosure.
SRIO multichannel communication system based on FC equipment
The exemplary FC device-based SRIO multi-channel communication system illustrated in connection with fig. 1 includes an srio_ip core, an srio_ctrl control module, an arbitration module, and a flow_ctrl transmit/receive control module.
As shown in fig. 1, the srio_ip core is configured to receive SRIO frame data input and convert the SRIO frame data input into an AXIS interface data output.
The SRIO_CTRL control module is used for controlling conversion between the SRIO protocol frame and the AXIS interface data, and comprises the steps of analyzing the AXIS interface data, framing the data frames based on the data of different FC types, dividing the data into data and framing the data based on the analysis result of the received FC data packet, converting the data into the AXIS interface data, and sending the AXIS interface data to the SRIO_IP core.
The arbitration module comprises a sending arbitration module and a receiving arbitration module, and is respectively used for request arbitration of a sending direction and a receiving direction.
And the flow_ctrl sending/receiving control module is used for controlling the sending of the data frames after framing and analyzing and buffering the received FC data packets.
As shown in fig. 1, the srio_ctrl control module includes a T port as a transmitting side module, an I port as a receiving side, a sorting module, and a framing module.
The flow_ctrl transmission/reception control module includes a plurality of transmission modules corresponding to different FC types.
In the data sending direction, the T port is used for analyzing the output data of the AXIS interface data and extracting the frame header information of the SRIO frame data as a descriptor, wherein the descriptor comprises TID, type, address and data length.
The ordering module is used for mapping the address and the channel according to the descriptor, ordering according to TID fields under different channels, sending the analyzed data into a designated RAM for caching, judging the FC type of the protocol frame, and adding the FC type into the descriptor.
And the framing module is used for framing the data according to the protocol frame format corresponding to the FC type through the FC type in the pre-reading descriptor, sending the framed data into the arbitration module, arbitrating by the sending arbitration module, and sending the data out of the sending module corresponding to the FC type.
In the data receiving direction, the flow_ctrl sending/receiving control module receives the FC data packet from the FC switching network, and obtains the data and the descriptor after parsing.
After the receiving arbitration module performs arbitration of the receiving module, the framing module pre-reads the descriptor obtained by analysis, searches the address according to the relation between the channel and the address, segments and packages the data according to the length of the data to obtain a plurality of data packages corresponding to the SRIO frame head, and finally obtains a data frame conforming to the AXIS protocol through I port conversion and sends the data frame to the SRIO_IP core.
As in the example shown in fig. 1, the srio_ip core, the srio_ctrl control module, the arbitration module, and the flow_ctrl transmit/receive control module are all configured inside the FPGA of the FC device.
As a preferred embodiment, the sorting module is arranged to obtain channel numbers based on a mapping relationship of addresses and channel numbers, thereby determining one channel number for each frame data. The mapping relation is configured through a blueprint, and after the FPGA of the FC equipment is powered on, the blueprint flash information is read for configuration.
As an optional implementation manner, the framing module includes an FC ASM framing module and an FC 818 framing module;
the FC ASM framing module is used for framing the FC ASM protocol frames of the fed data according to the FC ASM protocol;
And the FC 818 framing module is used for framing the FC 818 protocol frames of the sent data according to the FC 818 protocol.
As shown in fig. 1 and 3, taking FC 818ip and FC ASM ip as examples, the sending modules of different FC types include a first sending module based on FC ASM protocol and a second sending module based on FC 818 protocol.
As shown in connection with fig. 2, the sorting module is arranged to sort and buffer data in the following manner:
defining a description field of incomplete transactions in each pair of source ID/target ID in the SRIO HELLO frame, sequencing the HELLO frame according to the field, and TID epsilon [0,255];
setting 3 pointers, namely p_wr, p_rd and p_rd_next respectively, wherein p_wr is a write pointer, p_rd is a read pointer and p_rd_next is a pre-read pointer;
Using TID as data RAM address, HELLO frame payload as data RAM content, sequentially storing in data RAM;
taking TID as an address of a mark RAM, taking 1 or 0 as the content of the mark RAM, and initially marking the content as 0, marking the corresponding content as 1 when a HELLO frame corresponding to the TID is received, and resetting the content marking corresponding to the TID when data is sent to a lower level;
When judging that the corresponding mark contents of the positions pointed by the p_rd and the p_rd_next are 1, sending the data RAM contents on the p_rd position to a lower stage, adding 1 to the p_rd and the p_rd_next, and simultaneously clearing the mark contents;
And stopping sending until the write pointer p_wr catches up with p_rd when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, sending the residual data content on the p_rd position to the lower stage, adding 2 to the p_rd and p_rd_next pointers simultaneously, and exceeding the pointer position where data is not received for a long time, and after exceeding, continuing judging the data receiving condition according to the previous flow to finish the cyclic sequencing operation.
With reference to fig. 1 and 3, after the ordering module finishes ordering the data, the data is sent to the Payload fifo of the flow_ctrl sending/receiving control module for buffering according to different channels, where:
the FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read descriptors in Payload fifo to judge whether cached data corresponds to FC ASM protocol data, FC 818 protocol data or data sent by both paths;
After the framing module reads the data, the FC ASM framing module and the FC 818 framing module carry out framing according to respective protocol frame formats, the framing is sent into the sending arbitration module for arbitration after finishing framing, and the data is sent out through the corresponding sending modules after the arbitration is finished;
wherein, the FC ASM protocol frames under all channels arbitrate together and the FC 818 protocol frames under all channels arbitrate together.
The T module is further configured to determine a packet to be sent back to the srio_ip core according to whether the received data packet is of a non-write type or a write type.
SRIO multichannel communication method based on FC equipment
Referring to examples shown in fig. 1, 2,3,4, and 5, the SRIO multi-channel communication method based on the FC device according to the present disclosure includes the following steps:
In the data transmission direction, after receiving SRIO frame data input, the SRIO_IP core is converted into AXIS interface data output;
The T port analyzes AXIS interface data output data, and extracts frame header information of SRIO frame data as a descriptor, wherein the descriptor comprises a TID, a type, an address and a data length;
The sequencing module maps the address and the channel according to the descriptor, sequences the analyzed data according to TID fields under different channels, sends the analyzed data into a designated RAM for caching, judges the FC type of the protocol frame and adds the FC type into the descriptor;
The FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read descriptors, judge that the cached data corresponds to FC ASM protocol data, FC 818 protocol data or data transmitted by both paths, then framing the FC ASM framing module and the FC 818 framing module according to respective protocol frame formats, sending the FC ASM framing module and the FC 818 framing module into a transmission arbitration module for arbitration after framing is finished, and respectively transmitting the FC ASM framing module and the FC 818 framing module through the corresponding transmission module after the data is arbitrated;
In the data receiving direction, a first sending module based on an FC ASM protocol and a second sending module based on an FC 818 protocol in a flow_CTRL sending/receiving control module receive FC data packets from an FC switching network, and data and descriptors are obtained after analysis;
After the receiving arbitration module performs arbitration of the receiving module, the framing module pre-reads the descriptor obtained by analysis, searches the address according to the relation between the channel and the address, segments and packs the data according to the length of the data to obtain a plurality of data packets corresponding to the SRIO frame head, and finally obtains a data frame conforming to the AXIS protocol through I port conversion and sends the data frame to the SRIO_IP core.
As an optional implementation manner, the sorting module obtains channel numbers based on the mapping relation between addresses and channel numbers, so that one channel number corresponding to each frame of data is determined, the mapping relation is configured through a blueprint, and after the FPGA of the FC device is powered on, the blueprint flash information is read for configuration.
As an alternative embodiment, as shown in connection with fig. 2, the sorting module is arranged to sort and buffer data in the following way:
defining a description field of incomplete transactions in each pair of source ID/target ID in the SRIO HELLO frame, sequencing the HELLO frame according to the field, and TID epsilon [0,255];
setting 3 pointers, namely p_wr, p_rd and p_rd_next respectively, wherein p_wr is a write pointer, p_rd is a read pointer and p_rd_next is a pre-read pointer;
Using TID as data RAM address, HELLO frame payload as data RAM content, sequentially storing in data RAM;
taking TID as an address of a mark RAM, taking 1 or 0 as the content of the mark RAM, and initially marking the content as 0, marking the corresponding content as 1 when a HELLO frame corresponding to the TID is received, and resetting the content marking corresponding to the TID when data is sent to a lower level;
When judging that the corresponding mark contents of the positions pointed by the p_rd and the p_rd_next are 1, sending the data RAM contents on the p_rd position to a lower stage, adding 1 to the p_rd and the p_rd_next, and simultaneously clearing the mark contents;
And stopping sending until the write pointer p_wr catches up with p_rd when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, sending the residual data content on the p_rd position to the lower stage, adding 2 to the p_rd and p_rd_next pointers simultaneously, and exceeding the pointer position where data is not received for a long time, and after exceeding, continuing judging the data receiving condition according to the previous flow to finish the cyclic sequencing operation.
Example 1
In this example, the overall logic of an FC device based SRIO multichannel communication system is shown in fig. 1.
Data transmission
As shown in fig. 1, the direction from SRIO IP to FLOW CTRL is the data transmission direction, i.e., the data transmission direction from left to right in the drawing.
The data flows into the FPGA through the SRIO protocol frame, is converted into a data stream through the SRIO_IP core, is sent into a T port, is subjected to frame analysis, and extracts descriptor information in a frame header, wherein channel number mapping is performed by utilizing address information in the frame header (it is understood that the mapping relationship is configured by blueprint configuration, and the blueprint flash information is read for configuration after the FPGA is powered on), so that channel numbers are obtained, and therefore, each frame of data corresponds to one channel number.
The analyzed data are respectively sorted according to TID (TID is a descriptor in a frame header, each channel is incremental) according to different channel numbers in a sorting module, after sorting is completed, the data enter an arbitration module to arbitrate, one data are distributed to two paths to carry out different FC protocol framing (FC ASM and FC 818 protocols are taken as examples to describe, other FC protocol frames can be replaced), and finally the data are transmitted to opposite terminal equipment through a transmitting module to complete data transmission in a transmitting direction.
Data reception
As shown in connection with fig. 1, the direction from FLOW CTRL to srio_ip core, i.e., the right-to-left direction in the illustration, is the data reception direction.
After the data from the FC switching network is received by the receiving module, the analysis of protocol frames is completed, after the analysis is completed, the arbitration module performs arbitration of two paths of data, the data is sent to the framing module after the arbitration is completed, respective data packet segmentation and framing are respectively performed according to different FC types, the data length is segmented into payload conforming to the SRIO data length, each payload corresponds to one frame head, the data is converted into data frames conforming to an AXIS protocol through an I port and sent to an SRIO_IP core, and finally the data frames are sent out by the SRIO_IP core, so that the data transmission in the receiving direction is completed.
Ordering of
In connection with fig. 1 and 2, in an embodiment of the present invention, TID is a description field of outstanding transactions in each pair of source ID/target ID in an SRIO HELLO frame, according to which HELLO frames are ordered.
3 Pointers, p_wr, p_rd, p_rd_next are set, where p_wr is the write pointer, p_rd is the read pointer, and p_rd_next is the pre-read pointer.
In the example shown in fig. 2, described with TID e 0,255, HELLO frames payload are sequentially stored in the data RAM as the contents of the data RAM, using TID as the data RAM address.
Similarly, when a HELLO frame corresponding to a TID is received, the corresponding content flag is 1, and when data is sent to a lower level, the content flag corresponding to the TID is cleared;
When the corresponding mark content of the positions pointed by p_rd and p_rd_next is judged to be 1, the data RAM content on the p_rd position is sent to the lower stage, the p_rd and p_rd_next are added with 1, the mark content is cleared, when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, the sending is stopped until the write pointer p_wr catches up with p_rd (representing that the overtime/fifo is fast full, the difference value can be set), the residual data content on the p_rd position is sent to the lower stage, then the pointers of p_rd and p_rd_next are added with 2 simultaneously, and the pointer position without receiving data for a long time is passed.
After the data is passed, the data receiving condition is judged according to the previous flow, and the cycle is completed.
In connection with the embodiment of the present invention, the advantage of using the ordering method is that, due to the design defect of hardware, the TID under a single channel may not be continuous all the time, and jump may occur, as shown in c in fig. 2, when TID is 254, it is not received (blue mark is received, white mark is not received), at this time, if the reference clock used is changed due to the counting timeout, the time deviation of the counting timeout will be larger, and by using the way of calculating the difference between the write pointer and the read pointer, the excessive time deviation can be avoided, and at the same time, a buffer margin is reserved for waiting to receive the missing TID.
Data framing and arbitration
The data framing and arbitration flow under the multi-channel is shown in fig. 3, and after the data is ordered, the data is sent into Payload fifo for buffering according to different channels.
The FC ASM framing module and the FC 818 framing module pre-read the descriptors in the Payload fifo to determine whether the data is FC ASM data, FC 818 data, or two-way data (two-way data requires that one data be copied twice and sent to ASM and 818 respectively).
After the framing module reads the data, framing is carried out according to the respective protocol frame format, after framing is completed, a completion signal is sent to the arbitration module, asm protocol frames under all channels are arbitrated together, 818 protocol frames under all channels are arbitrated together, and after the data is arbitrated, the data frames are sent out through asm ip and 818 ip.
In examples of the invention, arbitration may be implemented using existing algorithms. For example, an equalization algorithm is adopted, the weights in the algorithm can be configured (the weights are high, the number of times to be read is large), or an adaptive mode of port flow is adopted (the weight in the next time T is determined according to the flow in the time T, and when the weights of all channels are the same during initialization, the polling mode is adopted for reading).
Data transmission
The data processing flow in the transmission direction is shown in fig. 4.
In the transmitting direction, one frame 256B SRIO frame data flows in, then enters the SRIO_IP core and is converted into AXIS interface data to be output, the data enters the T module, the module converts the AXIS interface data into a common data stream, and meanwhile, information in the SRIO frame header is extracted to be used as a subsequent descriptor, wherein the information comprises TID, type, address and data length information.
The data and descriptors are placed in the cache separately. Meanwhile, the T module also decides whether to carry out a packet returning to the SRIO_IP core according to the type.
The lower order module pre-reads the descriptor, maps the address and the channel of the descriptor, and sends the 256B data into the appointed RAM for caching according to the TID fields under different channels.
After the sorting is completed, the 256B data and the new descriptor are respectively stored in a cache, judgment is carried out according to the data content, and the FC type is added to the descriptor.
And (3) writing data into different framing modules according to the type of the FC (fiber channel), and when the framing modules read n 256 data packets with the length of one FC frame, writing the data frames after framing into a buffer memory and waiting for arbitration.
When the arbitration hits, the corresponding data frame is read out and sent out through FC ASM ip and FC818 ip.
In the special case, in the sorting module, two pointers are used to determine whether to send out data, and then the data sending out mode of the last frame is according to eop fields in the data descriptor, since the SRIO protocol frame does not contain sop and eop, the start and end of the defined frame are added in the data, wherein 4B is used to represent sop,4B is used to represent eop, and in addition, the format, type, length, line number and other information of the FC 818 image are defined in the data.
Data reception
The flow of the reception direction data processing is shown in fig. 5.
In the receiving direction, there is a frame payload length 2096B of FC ASM packet, after being parsed by FC ASM ip, the frame header obtains information such as SID, DID, MSG ID, frame length, etc., where MSG ID is a channel number for use, and descriptors and data are stored in different buffers respectively.
After arbitration and selection by the arbitration module, the descriptors are pre-read by the framing module, the addresses are found according to the relation between the channel numbers and the SRIO addresses, and the data are segmented into 8 256B and 1 48B data packets conforming to the SRIO protocol according to the length of the data payload. It should be understood that the 9 data packets respectively correspond to the frame heads of 9 SRIOs, the TID field is managed according to the channel number, and finally, the data frames which are read by the I port and converted into the data frames conforming to the AXIS protocol are sent out to the srio_ip core, and finally, the data frames are sent out by the srio_ip core, so that the data transmission in the receiving direction is completed.
While the invention has been described with reference to preferred embodiments, it is not intended to be limiting. Those skilled in the art will appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the present invention. Accordingly, the scope of the invention is defined by the appended claims.

Claims (11)

1.一种基于FC设备的SRIO多通道通信系统,其特征在于,包括:1. An SRIO multi-channel communication system based on FC equipment, characterized by comprising: SRIO_IP核,用于接收SRIO帧数据输入,转换成AXIS接口数据输出;SRIO_IP core, used to receive SRIO frame data input and convert it into AXIS interface data output; SRIO_CTRL控制模块,用于SRIO协议帧与AXIS接口数据之间的转换控制,包括对AXIS接口数据解析并基于不同FC类型的数据进行数据帧组帧,以及基于接收FC数据包的解析结果进行数据切分与组包后,转换成AXIS接口数据送出至SRIO_IP核;SRIO_CTRL control module, used for conversion control between SRIO protocol frames and AXIS interface data, including parsing AXIS interface data and framing data frames based on data of different FC types, and splitting and assembling data based on the parsing results of received FC data packets, and converting them into AXIS interface data and sending them to SRIO_IP core; 仲裁模块,包括发送仲裁模块和接收仲裁模块,分别用于发送方向与接收方向的请求仲裁;The arbitration module includes a sending arbitration module and a receiving arbitration module, which are used for request arbitration in the sending direction and the receiving direction respectively; FLOW_CTRL发送/接收控制模块,用于组帧后数据帧的发送控制,以及接收到的FC数据包的解析与缓冲;FLOW_CTRL send/receive control module, used for sending control of data frames after framing, and parsing and buffering of received FC data packets; 其中,所述SRIO_CTRL控制模块包括作为发送侧模块的T端口、作为接收侧的I端口、排序模块以及组帧模块;所述FLOW_CTRL发送/接收控制模块包括多个对应于不同FC类型的发送模块;The SRIO_CTRL control module includes a T port as a sending side module, an I port as a receiving side, a sorting module and a framing module; the FLOW_CTRL sending/receiving control module includes a plurality of sending modules corresponding to different FC types; 在数据发送方向,所述T端口用于解析AXIS接口数据输出数据并提取SRIO帧数据的帧头信息作为描述符,所述描述符包括TID、类型、地址和数据长度;In the data transmission direction, the T port is used to parse the AXIS interface data output data and extract the frame header information of the SRIO frame data as a descriptor, and the descriptor includes TID, type, address and data length; 所述排序模块用于根据描述符进行地址与通道的映射,并根据不同的通道下的TID字段排序,将解析得到的数据送入指定的RAM中缓存,并判断协议帧的FC类型、将FC类型加入到描述符中;The sorting module is used to map addresses and channels according to the descriptor, sort according to the TID fields under different channels, send the parsed data to the specified RAM for buffering, determine the FC type of the protocol frame, and add the FC type to the descriptor; 组帧模块,用于通过预读取描述符中的FC类型将数据分别依据FC类型对应的协议帧格式进行组帧,组帧后的数据被送入到仲裁模块中,由所述发送仲裁模块进行仲裁后,从FC类型对应的发送模块发送出去;A framing module, used to frame the data according to the protocol frame format corresponding to the FC type by pre-reading the FC type in the descriptor, and the framed data is sent to the arbitration module, and after arbitration by the sending arbitration module, it is sent out from the sending module corresponding to the FC type; 在数据接收方向,所述FLOW_CTRL发送/接收控制模块接收来自FC交换网络的FC数据包,解析后获得数据和描述符;In the data receiving direction, the FLOW_CTRL sending/receiving control module receives FC data packets from the FC switching network and obtains data and descriptors after parsing; 所述接收仲裁模块进行接收模块的仲裁后,由所述组帧模块预读取解析得到的描述符,依据通道与地址的关系查找到地址,并依据数据的长度将数据进行切分和组包,获得对应SRIO帧头的多个数据包,最后通过I端口转换获得符合AXIS协议的数据帧,送出至SRIO_IP核;After the receiving arbitration module arbitrates the receiving module, the framing module pre-reads the parsed descriptor, finds the address according to the relationship between the channel and the address, and divides and packages the data according to the length of the data to obtain multiple data packets corresponding to the SRIO frame header, and finally obtains the data frame that complies with the AXIS protocol through I port conversion and sends it to the SRIO_IP core; 其中,所述SRIO_IP核、SRIO_CTRL控制模块、仲裁模块以及FLOW_CTRL发送/接收控制模块均被配置在FC设备的FPGA内部。The SRIO_IP core, SRIO_CTRL control module, arbitration module and FLOW_CTRL sending/receiving control module are all configured inside the FPGA of the FC device. 2.根据权利要求1所述的基于FC设备的SRIO多通道通信系统,其特征在于,所述排序模块被设置成基于地址与通道号的映射关系获得通道号,由此确定每一帧数据对应的一个通道号。2. The SRIO multi-channel communication system based on FC devices according to claim 1 is characterized in that the sorting module is configured to obtain the channel number based on a mapping relationship between the address and the channel number, thereby determining a channel number corresponding to each frame of data. 3.根据权利要求2所述的基于FC设备的SRIO多通道通信系统,其特征在于,所述映射关系被通过蓝图配置,FC设备的FPGA上电后读取蓝图flash信息进行配置。3. The SRIO multi-channel communication system based on FC equipment according to claim 2, characterized in that the mapping relationship is configured through a blueprint, and the FPGA of the FC equipment reads the blueprint flash information for configuration after being powered on. 4.根据权利要求1所述的基于FC设备的SRIO多通道通信系统,其特征在于,所述组帧模块包括FC ASM组帧模块以及FC 818组帧模块;4. The SRIO multi-channel communication system based on FC equipment according to claim 1, characterized in that the framing module includes an FC ASM framing module and an FC 818 framing module; FC ASM组帧模块,用于根据FC ASM协议对送入的数据进行FC ASM协议帧组帧;FC ASM framing module, used for framing the input data into FC ASM protocol frames according to the FC ASM protocol; FC 818组帧模块,用于根据FC 818协议对送入的数据进行FC 818协议帧组帧。The FC 818 framing module is used to perform FC 818 protocol frame framing on the input data according to the FC 818 protocol. 5.根据权利要求1所述的基于FC设备的SRIO多通道通信系统,其特征在于,所述不同FC类型的发送模块包括基于FC ASM协议的第一发送模块以及基于FC 818协议的第二发送模块。5 . The SRIO multi-channel communication system based on FC devices according to claim 1 , wherein the sending modules of different FC types include a first sending module based on FC ASM protocol and a second sending module based on FC 818 protocol. 6.根据权利要求1所述的基于FC设备的SRIO多通道通信系统,其特征在于,所述排序模块被设置成按照以下方式进行排序与数据缓存:6. The SRIO multi-channel communication system based on FC devices according to claim 1, characterized in that the sorting module is configured to perform sorting and data caching in the following manner: 定义TID表示SRIO HELLO帧中每对源ID/目标ID中未完成事务的描述字段,依据该字段对HELLO帧进行排序,TID∈[0,255];Define TID to represent the description field of the unfinished transaction in each source ID/destination ID pair in the SRIO HELLO frame, and sort the HELLO frames according to this field, TID∈[0,255]; 设置3个指针,分别为p_wr、p_rd、p_rd_next,其中p_wr是写指针,p_rd是读指针,p_rd_next是预读指针;Set up three pointers, namely p_wr, p_rd, and p_rd_next, where p_wr is the write pointer, p_rd is the read pointer, and p_rd_next is the pre-read pointer; 以TID作为数据RAM地址,HELLO帧payload作为数据RAM的内容,依次存储在数据RAM中;The TID is used as the data RAM address, and the HELLO frame payload is used as the content of the data RAM, which are stored in the data RAM in sequence; 以TID作为标记RAM的地址,1或者0作为标记RAM的内容,初始为标记为0,当收到TID对应的HELLO帧时,对应内容标记为1,数据被发送到下级时,将该TID对应的内容标记清零;Use TID as the address of the tag RAM, 1 or 0 as the content of the tag RAM, the initial tag is 0, when the HELLO frame corresponding to the TID is received, the corresponding content is marked as 1, and when the data is sent to the lower level, the content tag corresponding to the TID is cleared; 其中,当判断到p_rd、p_rd_next指向的位置的对应标记内容均为1的时候,将p_rd位置上的数据RAM内容发往下级,p_rd、p_rd_next均加1,同时清除标记内容;Among them, when it is determined that the corresponding mark contents of the positions pointed to by p_rd and p_rd_next are both 1, the data RAM content at the p_rd position is sent to the lower level, p_rd and p_rd_next are both increased by 1, and the mark contents are cleared at the same time; 当p_rd对应的标记内容为1,p_rd_next对应的标记内容为0,则停止发送,直至写指针p_wr即将追上p_rd,,将p_rd位置上的残余数据内容发往下级,然后p_rd、p_rd_next指针同时加2,越过长时间未收到数据的指针位置;在越过之后,继续按照之前的流程判断数据接收情况,完成循环排序操作。When the tag content corresponding to p_rd is 1 and the tag content corresponding to p_rd_next is 0, stop sending until the write pointer p_wr is about to catch up with p_rd, send the remaining data content at the p_rd position to the lower level, and then add 2 to the p_rd and p_rd_next pointers at the same time to pass the pointer position where no data has been received for a long time; after passing, continue to judge the data reception status according to the previous process to complete the circular sorting operation. 7.根据权利要求1所述的基于FC设备的SRIO多通道通信系统,其特征在于,所述排序模块完成数据的排序后,被按照不同的通道送入到FLOW_CTRL发送/接收控制模块的Payloadfifo中进行缓存,其中:7. The SRIO multi-channel communication system based on FC equipment according to claim 1 is characterized in that after the sorting module completes the sorting of data, the data is sent to the Payloadfifo of the FLOW_CTRL sending/receiving control module according to different channels for caching, wherein: 所述组帧模块中的FC ASM组帧模块与FC 818组帧模块分别预读取Payload fifo中的描述符,以判断缓存的数据对应是FC ASM协议数据、FC 818协议数据或者两路均发送的数据;The FC ASM framing module and the FC 818 framing module in the framing module pre-read the descriptors in the Payload fifo respectively to determine whether the cached data corresponds to FC ASM protocol data, FC 818 protocol data, or data sent by both paths; 组帧模块读取数据后,FC ASM组帧模块与FC 818组帧模块依据各自的协议帧格式进行组帧,组帧完成后送入发送仲裁模块中进行仲裁,数据完成仲裁后,分别通过对应的发送模块发送出去;After the framing module reads the data, the FC ASM framing module and the FC 818 framing module framing the data according to their respective protocol frame formats. After framing is completed, the data is sent to the sending arbitration module for arbitration. After the data is arbitrated, it is sent out through the corresponding sending modules. 其中,所有通道下的FC ASM协议帧一起仲裁,所有通道下的FC 818协议帧一起仲裁。The FC ASM protocol frames under all channels are arbitrated together, and the FC 818 protocol frames under all channels are arbitrated together. 8.根据权利要求7所述的基于FC设备的SRIO多通道通信系统,其特征在于,所述T模块还被配置用于依据接收到的数据包为非写类型或者写类型带回包决定回包给SRIO_IP核。8. The SRIO multi-channel communication system based on FC devices according to claim 7, characterized in that the T module is further configured to decide whether to return the packet to the SRIO_IP core according to whether the received data packet is a non-write type or a write type return packet. 9.一种基于权利要求1-8中任意一项所述的基于FC设备的SRIO多通道通信系统的基于FC设备的SRIO多通道通信方法,其特征在于,包括以下步骤:9. A SRIO multi-channel communication method based on FC devices based on the SRIO multi-channel communication system based on FC devices according to any one of claims 1 to 8, characterized in that it comprises the following steps: 在数据发送方向,SRIO_IP核接收到SRIO帧数据输入后,转换成AXIS接口数据输出;In the data sending direction, after the SRIO_IP core receives the SRIO frame data input, it converts it into AXIS interface data output; T端口解析AXIS接口数据输出数据,提取SRIO帧数据的帧头信息作为描述符,所述描述符包括TID、类型、地址和数据长度;The T port parses the AXIS interface data output data and extracts the frame header information of the SRIO frame data as a descriptor, wherein the descriptor includes TID, type, address and data length; 排序模块根据描述符进行地址与通道的映射,并根据不同的通道下的TID字段排序,将解析得到的数据送入指定的RAM中缓存,并判断协议帧的FC类型、将FC类型加入到描述符中;The sorting module maps addresses and channels according to the descriptor, sorts according to the TID fields under different channels, sends the parsed data to the specified RAM for cache, determines the FC type of the protocol frame, and adds the FC type to the descriptor; 组帧模块中的FC ASM组帧模块与FC 818组帧模块分别预读取描述符,判断缓存的数据对应是FC ASM协议数据、FC 818协议数据或者两路均发送的数据;然后由FC ASM组帧模块与FC 818组帧模块依据各自的协议帧格式进行组帧,组帧完成后送入发送仲裁模块中进行仲裁,数据完成仲裁后,分别通过对应的发送模块发送出去;其中,所有通道下的FC ASM协议帧一起仲裁,所有通道下的FC 818协议帧一起仲裁;The FC ASM framing module and the FC 818 framing module in the framing module pre-read the descriptors respectively to determine whether the cached data corresponds to FC ASM protocol data, FC 818 protocol data, or data sent by both channels; then the FC ASM framing module and the FC 818 framing module framing the data according to their respective protocol frame formats, and after framing is completed, the data is sent to the sending arbitration module for arbitration. After the data is arbitrated, it is sent out through the corresponding sending modules respectively; among them, the FC ASM protocol frames under all channels are arbitrated together, and the FC 818 protocol frames under all channels are arbitrated together; 在数据接收方向,FLOW_CTRL发送/接收控制模块中基于FC ASM协议的第一发送模块以及基于FC 818协议的第二发送模块接收来自FC交换网络的FC数据包,解析后获得数据和描述符;In the data receiving direction, the first sending module based on the FC ASM protocol and the second sending module based on the FC 818 protocol in the FLOW_CTRL sending/receiving control module receive FC data packets from the FC switching network and obtain data and descriptors after parsing; 接收仲裁模块进行接收模块的仲裁后,由所述组帧模块预读取解析得到的描述符,依据通道与地址的关系查找到地址,并依据数据的长度将数据进行切分和组包,获得对应SRIO帧头的多个数据包,最后通过I端口转换获得符合AXIS协议的数据帧,送出至SRIO_IP核。After the receiving arbitration module arbitrates the receiving module, the framing module pre-reads the parsed descriptor, finds the address according to the relationship between the channel and the address, and divides and packages the data according to the length of the data to obtain multiple data packets corresponding to the SRIO frame header. Finally, the data frame that complies with the AXIS protocol is obtained through I port conversion and sent to the SRIO_IP core. 10.根据权利要求9所述的基于FC设备的SRIO多通道通信方法,其特征在于,所述排序模块基于地址与通道号的映射关系获得通道号,由此确定每一帧数据对应的一个通道号,其中的映射关系被通过蓝图配置,FC设备的FPGA上电后读取蓝图flash信息进行配置。10. The SRIO multi-channel communication method based on FC equipment according to claim 9 is characterized in that the sorting module obtains the channel number based on the mapping relationship between the address and the channel number, thereby determining a channel number corresponding to each frame of data, wherein the mapping relationship is configured through a blueprint, and the FPGA of the FC equipment reads the blueprint flash information for configuration after power-on. 11.根据权利要求9或者10所述的基于FC设备的SRIO多通道通信方法,其特征在于,所述排序模块被设置成按照以下方式进行排序与数据缓存:11. The SRIO multi-channel communication method based on FC equipment according to claim 9 or 10, characterized in that the sorting module is configured to perform sorting and data caching in the following manner: 定义TID表示SRIO HELLO帧中每对源ID/目标ID中未完成事务的描述字段,依据该字段对HELLO帧进行排序,TID∈[0,255];Define TID to represent the description field of the unfinished transaction in each source ID/destination ID pair in the SRIO HELLO frame, and sort the HELLO frames according to this field, TID∈[0,255]; 设置3个指针,分别为p_wr、p_rd、p_rd_next,其中p_wr是写指针,p_rd是读指针,p_rd_next是预读指针;Set up three pointers, namely p_wr, p_rd, and p_rd_next, where p_wr is the write pointer, p_rd is the read pointer, and p_rd_next is the pre-read pointer; 以TID作为数据RAM地址,HELLO帧payload作为数据RAM的内容,依次存储在数据RAM中;The TID is used as the data RAM address, and the HELLO frame payload is used as the content of the data RAM, which are stored in the data RAM in sequence; 以TID作为标记RAM的地址,1或者0作为标记RAM的内容,初始为标记为0,当收到TID对应的HELLO帧时,对应内容标记为1,数据被发送到下级时,将该TID对应的内容标记清零;Use TID as the address of the tag RAM, 1 or 0 as the content of the tag RAM, the initial tag is 0, when the HELLO frame corresponding to the TID is received, the corresponding content is marked as 1, and when the data is sent to the lower level, the content tag corresponding to the TID is cleared; 其中,当判断到p_rd、p_rd_next指向的位置的对应标记内容均为1的时候,将p_rd位置上的数据RAM内容发往下级,p_rd、p_rd_next均加1,同时清除标记内容;Among them, when it is determined that the corresponding mark contents of the positions pointed to by p_rd and p_rd_next are both 1, the data RAM content at the p_rd position is sent to the lower level, p_rd and p_rd_next are both increased by 1, and the mark contents are cleared at the same time; 当p_rd对应的标记内容为1,p_rd_next对应的标记内容为0,则停止发送,直至写指针p_wr即将追上p_rd,,将p_rd位置上的残余数据内容发往下级,然后p_rd、p_rd_next指针同时加2,越过长时间未收到数据的指针位置;在越过之后,继续按照之前的流程判断数据接收情况,完成循环排序操作。When the tag content corresponding to p_rd is 1 and the tag content corresponding to p_rd_next is 0, stop sending until the write pointer p_wr is about to catch up with p_rd, send the remaining data content at the p_rd position to the lower level, and then add 2 to the p_rd and p_rd_next pointers at the same time to pass the pointer position where no data has been received for a long time; after passing, continue to judge the data reception status according to the previous process to complete the circular sorting operation.
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