Disclosure of Invention
In view of the drawbacks and deficiencies of the prior art, according to a first aspect of the present invention, there is provided an SRIO multi-channel communication system based on FC devices, comprising:
The SRIO_IP core is used for receiving SRIO frame data input and converting the SRIO frame data input into AXIS interface data output;
the SRIO_CTRL control module is used for controlling conversion between an SRIO protocol frame and AXIS interface data, and comprises the steps of analyzing the AXIS interface data, framing the data frames based on data of different FC types, dividing and grouping the data based on the analysis result of a received FC data packet, converting the data into AXIS interface data, and sending the AXIS interface data to the SRIO_IP core;
the arbitration module comprises a sending arbitration module and a receiving arbitration module, and is respectively used for request arbitration of a sending direction and a receiving direction;
the flow_ctrl transmitting/receiving control module is used for controlling the transmission of the data frames after framing and analyzing and buffering the received FC data packets;
the SRIO_CTRL control module comprises a T port serving as a transmitting side module, an I port serving as a receiving side, a sequencing module and a framing module, wherein the FLOW_CTRL transmitting/receiving control module comprises a plurality of transmitting modules corresponding to different FC types;
in the data sending direction, the T port is used for analyzing the AXIS interface data output data and extracting frame header information of SRIO frame data as a descriptor, wherein the descriptor comprises a TID, a type, an address and a data length;
the sequencing module is used for mapping the address and the channel according to the descriptor, sequencing according to TID fields under different channels, sending the analyzed data into a designated RAM for caching, judging the FC type of the protocol frame, and adding the FC type into the descriptor;
The framing module is used for framing the data according to the protocol frame format corresponding to the FC type through the FC type in the pre-reading descriptor, sending the framed data into the arbitration module, arbitrating by the sending arbitration module, and sending the data out of the sending module corresponding to the FC type;
In the data receiving direction, the flow_ctrl sending/receiving control module receives an FC data packet from an FC switching network, and obtains data and a descriptor after analysis;
After the receiving arbitration module performs arbitration of the receiving module, the framing module pre-reads the descriptor obtained by analysis, searches the address according to the relation between the channel and the address, segments and packages the data according to the length of the data to obtain a plurality of data packages corresponding to the SRIO frame head, and finally obtains a data frame conforming to an AXIS protocol through I port conversion and sends the data frame to the SRIO_IP core;
The SRIO_IP core, the SRIO_CTRL control module, the arbitration module and the flow_CTRL sending/receiving control module are all configured inside the FPGA of the FC device.
As an alternative embodiment, the sorting module is configured to obtain channel numbers based on a mapping relationship between addresses and channel numbers, thereby determining one channel number corresponding to each frame data. The mapping relation is configured through a blueprint, and after the FPGA of the FC equipment is powered on, the blueprint flash information is read for configuration.
As an alternative embodiment, the sorting module is configured to sort and buffer data in the following manner:
defining a description field of incomplete transactions in each pair of source ID/target ID in the SRIO HELLO frame, sequencing the HELLO frame according to the field, and TID epsilon [0,255];
setting 3 pointers, namely p_wr, p_rd and p_rd_next respectively, wherein p_wr is a write pointer, p_rd is a read pointer and p_rd_next is a pre-read pointer;
Using TID as data RAM address, HELLO frame payload as data RAM content, sequentially storing in data RAM;
taking TID as an address of a mark RAM, taking 1 or 0 as the content of the mark RAM, and initially marking the content as 0, marking the corresponding content as 1 when a HELLO frame corresponding to the TID is received, and resetting the content marking corresponding to the TID when data is sent to a lower level;
When judging that the corresponding mark contents of the positions pointed by the p_rd and the p_rd_next are 1, sending the data RAM contents on the p_rd position to a lower stage, adding 1 to the p_rd and the p_rd_next, and simultaneously clearing the mark contents;
And stopping sending until the write pointer p_wr catches up with p_rd when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, sending the residual data content on the p_rd position to the lower stage, adding 2 to the p_rd and p_rd_next pointers simultaneously, and exceeding the pointer position where data is not received for a long time, and after exceeding, continuing judging the data receiving condition according to the previous flow to finish the cyclic sequencing operation.
As an optional implementation manner, after the ordering module finishes the ordering of the data, the data is sent to the Payload fifo of the flow_ctrl sending/receiving control module for buffering according to different channels, where:
the FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read descriptors in Payload fifo to judge whether cached data corresponds to FC ASM protocol data, FC 818 protocol data or data sent by both paths;
After the framing module reads the data, the FC ASM framing module and the FC 818 framing module carry out framing according to respective protocol frame formats, the framing is sent into the sending arbitration module for arbitration after finishing framing, and the data is sent out through the corresponding sending modules after the arbitration is finished;
wherein, the FC ASM protocol frames under all channels arbitrate together and the FC 818 protocol frames under all channels arbitrate together.
According to a second aspect of the object of the present invention, there is also provided an SRIO multi-channel communication method based on an FC device, comprising the steps of:
In the data transmission direction, after receiving SRIO frame data input, the SRIO_IP core is converted into AXIS interface data output;
The T port analyzes AXIS interface data output data, and extracts frame header information of SRIO frame data as a descriptor, wherein the descriptor comprises a TID, a type, an address and a data length;
The sequencing module maps the address and the channel according to the descriptor, sequences the analyzed data according to TID fields under different channels, sends the analyzed data into a designated RAM for caching, judges the FC type of the protocol frame and adds the FC type into the descriptor;
The FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read descriptors, judge that the cached data corresponds to FC ASM protocol data, FC 818 protocol data or data transmitted by both paths, then framing the FC ASM framing module and the FC 818 framing module according to respective protocol frame formats, sending the FC ASM framing module and the FC 818 framing module into a transmission arbitration module for arbitration after framing is finished, and respectively transmitting the FC ASM framing module and the FC 818 framing module through the corresponding transmission module after the data is arbitrated;
In the data receiving direction, a first sending module based on an FC ASM protocol and a second sending module based on an FC 818 protocol in a flow_CTRL sending/receiving control module receive FC data packets from an FC switching network, and data and descriptors are obtained after analysis;
After the receiving arbitration module performs arbitration of the receiving module, the framing module pre-reads the descriptor obtained by analysis, searches the address according to the relation between the channel and the address, segments and packs the data according to the length of the data to obtain a plurality of data packets corresponding to the SRIO frame head, and finally obtains a data frame conforming to the AXIS protocol through I port conversion and sends the data frame to the SRIO_IP core.
As an optional implementation manner, the sorting module obtains channel numbers based on a mapping relation between addresses and channel numbers, so that one channel number corresponding to each frame of data is determined, wherein the mapping relation is configured through a blueprint, and after an FPGA of the FC device is powered on, the blueprint flash information is read for configuration.
As an alternative embodiment, the sorting module is configured to sort and buffer data in the following manner:
defining a description field of incomplete transactions in each pair of source ID/target ID in the SRIO HELLO frame, sequencing the HELLO frame according to the field, and TID epsilon [0,255];
setting 3 pointers, namely p_wr, p_rd and p_rd_next respectively, wherein p_wr is a write pointer, p_rd is a read pointer and p_rd_next is a pre-read pointer;
Using TID as data RAM address, HELLO frame payload as data RAM content, sequentially storing in data RAM;
taking TID as an address of a mark RAM, taking 1 or 0 as the content of the mark RAM, and initially marking the content as 0, marking the corresponding content as 1 when a HELLO frame corresponding to the TID is received, and resetting the content marking corresponding to the TID when data is sent to a lower level;
When judging that the corresponding mark contents of the positions pointed by the p_rd and the p_rd_next are 1, sending the data RAM contents on the p_rd position to a lower stage, adding 1 to the p_rd and the p_rd_next, and simultaneously clearing the mark contents;
And stopping sending until the write pointer p_wr catches up with p_rd when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, sending the residual data content on the p_rd position to the lower stage, adding 2 to the p_rd and p_rd_next pointers simultaneously, and exceeding the pointer position where data is not received for a long time, and after exceeding, continuing judging the data receiving condition according to the previous flow to finish the cyclic sequencing operation.
In combination with the SRIO multi-channel communication method and system based on the FC equipment, the invention aims to provide the SRIO multi-channel communication method and system based on the FC equipment by utilizing the FPGA to provide a superior platform for programmable and parallel data processing for protocol conversion, and the SRIO multi-channel communication based on the FC equipment realizes efficient protocol conversion by virtue of the FPGA technology. In the SRIO multichannel communication method and system based on the FC equipment, the communication efficiency is further optimized through the application of multichannel sequencing, a communication solution with higher performance and low delay is provided, the method and system are suitable for various high-performance communication systems, and the ever-increasing data exchange and communication requirements are met.
It should be understood that all combinations of the foregoing concepts, as well as additional concepts described in more detail below, may be considered a part of the inventive subject matter of the present disclosure as long as such concepts are not mutually inconsistent. In addition, all combinations of claimed subject matter are considered part of the disclosed inventive subject matter.
The foregoing and other aspects, embodiments, and features of the present teachings will be more fully understood from the following description, taken together with the accompanying drawings. Other additional aspects of the invention, such as features and/or advantages of the exemplary embodiments, will be apparent from the description which follows, or may be learned by practice of the embodiments according to the teachings of the invention.
Detailed Description
For a better understanding of the technical content of the present invention, specific examples are set forth below, along with the accompanying drawings.
Aspects of the invention are described in this disclosure with reference to the drawings, in which are shown a number of illustrative embodiments. The embodiments of the present disclosure are not necessarily intended to include all aspects of the invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, may be implemented in any of a number of ways, as the disclosed concepts and embodiments are not limited to any implementation. Additionally, some aspects of the disclosure may be used alone or in any suitable combination with other aspects of the disclosure.
SRIO multichannel communication system based on FC equipment
The exemplary FC device-based SRIO multi-channel communication system illustrated in connection with fig. 1 includes an srio_ip core, an srio_ctrl control module, an arbitration module, and a flow_ctrl transmit/receive control module.
As shown in fig. 1, the srio_ip core is configured to receive SRIO frame data input and convert the SRIO frame data input into an AXIS interface data output.
The SRIO_CTRL control module is used for controlling conversion between the SRIO protocol frame and the AXIS interface data, and comprises the steps of analyzing the AXIS interface data, framing the data frames based on the data of different FC types, dividing the data into data and framing the data based on the analysis result of the received FC data packet, converting the data into the AXIS interface data, and sending the AXIS interface data to the SRIO_IP core.
The arbitration module comprises a sending arbitration module and a receiving arbitration module, and is respectively used for request arbitration of a sending direction and a receiving direction.
And the flow_ctrl sending/receiving control module is used for controlling the sending of the data frames after framing and analyzing and buffering the received FC data packets.
As shown in fig. 1, the srio_ctrl control module includes a T port as a transmitting side module, an I port as a receiving side, a sorting module, and a framing module.
The flow_ctrl transmission/reception control module includes a plurality of transmission modules corresponding to different FC types.
In the data sending direction, the T port is used for analyzing the output data of the AXIS interface data and extracting the frame header information of the SRIO frame data as a descriptor, wherein the descriptor comprises TID, type, address and data length.
The ordering module is used for mapping the address and the channel according to the descriptor, ordering according to TID fields under different channels, sending the analyzed data into a designated RAM for caching, judging the FC type of the protocol frame, and adding the FC type into the descriptor.
And the framing module is used for framing the data according to the protocol frame format corresponding to the FC type through the FC type in the pre-reading descriptor, sending the framed data into the arbitration module, arbitrating by the sending arbitration module, and sending the data out of the sending module corresponding to the FC type.
In the data receiving direction, the flow_ctrl sending/receiving control module receives the FC data packet from the FC switching network, and obtains the data and the descriptor after parsing.
After the receiving arbitration module performs arbitration of the receiving module, the framing module pre-reads the descriptor obtained by analysis, searches the address according to the relation between the channel and the address, segments and packages the data according to the length of the data to obtain a plurality of data packages corresponding to the SRIO frame head, and finally obtains a data frame conforming to the AXIS protocol through I port conversion and sends the data frame to the SRIO_IP core.
As in the example shown in fig. 1, the srio_ip core, the srio_ctrl control module, the arbitration module, and the flow_ctrl transmit/receive control module are all configured inside the FPGA of the FC device.
As a preferred embodiment, the sorting module is arranged to obtain channel numbers based on a mapping relationship of addresses and channel numbers, thereby determining one channel number for each frame data. The mapping relation is configured through a blueprint, and after the FPGA of the FC equipment is powered on, the blueprint flash information is read for configuration.
As an optional implementation manner, the framing module includes an FC ASM framing module and an FC 818 framing module;
the FC ASM framing module is used for framing the FC ASM protocol frames of the fed data according to the FC ASM protocol;
And the FC 818 framing module is used for framing the FC 818 protocol frames of the sent data according to the FC 818 protocol.
As shown in fig. 1 and 3, taking FC 818ip and FC ASM ip as examples, the sending modules of different FC types include a first sending module based on FC ASM protocol and a second sending module based on FC 818 protocol.
As shown in connection with fig. 2, the sorting module is arranged to sort and buffer data in the following manner:
defining a description field of incomplete transactions in each pair of source ID/target ID in the SRIO HELLO frame, sequencing the HELLO frame according to the field, and TID epsilon [0,255];
setting 3 pointers, namely p_wr, p_rd and p_rd_next respectively, wherein p_wr is a write pointer, p_rd is a read pointer and p_rd_next is a pre-read pointer;
Using TID as data RAM address, HELLO frame payload as data RAM content, sequentially storing in data RAM;
taking TID as an address of a mark RAM, taking 1 or 0 as the content of the mark RAM, and initially marking the content as 0, marking the corresponding content as 1 when a HELLO frame corresponding to the TID is received, and resetting the content marking corresponding to the TID when data is sent to a lower level;
When judging that the corresponding mark contents of the positions pointed by the p_rd and the p_rd_next are 1, sending the data RAM contents on the p_rd position to a lower stage, adding 1 to the p_rd and the p_rd_next, and simultaneously clearing the mark contents;
And stopping sending until the write pointer p_wr catches up with p_rd when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, sending the residual data content on the p_rd position to the lower stage, adding 2 to the p_rd and p_rd_next pointers simultaneously, and exceeding the pointer position where data is not received for a long time, and after exceeding, continuing judging the data receiving condition according to the previous flow to finish the cyclic sequencing operation.
With reference to fig. 1 and 3, after the ordering module finishes ordering the data, the data is sent to the Payload fifo of the flow_ctrl sending/receiving control module for buffering according to different channels, where:
the FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read descriptors in Payload fifo to judge whether cached data corresponds to FC ASM protocol data, FC 818 protocol data or data sent by both paths;
After the framing module reads the data, the FC ASM framing module and the FC 818 framing module carry out framing according to respective protocol frame formats, the framing is sent into the sending arbitration module for arbitration after finishing framing, and the data is sent out through the corresponding sending modules after the arbitration is finished;
wherein, the FC ASM protocol frames under all channels arbitrate together and the FC 818 protocol frames under all channels arbitrate together.
The T module is further configured to determine a packet to be sent back to the srio_ip core according to whether the received data packet is of a non-write type or a write type.
SRIO multichannel communication method based on FC equipment
Referring to examples shown in fig. 1, 2,3,4, and 5, the SRIO multi-channel communication method based on the FC device according to the present disclosure includes the following steps:
In the data transmission direction, after receiving SRIO frame data input, the SRIO_IP core is converted into AXIS interface data output;
The T port analyzes AXIS interface data output data, and extracts frame header information of SRIO frame data as a descriptor, wherein the descriptor comprises a TID, a type, an address and a data length;
The sequencing module maps the address and the channel according to the descriptor, sequences the analyzed data according to TID fields under different channels, sends the analyzed data into a designated RAM for caching, judges the FC type of the protocol frame and adds the FC type into the descriptor;
The FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read descriptors, judge that the cached data corresponds to FC ASM protocol data, FC 818 protocol data or data transmitted by both paths, then framing the FC ASM framing module and the FC 818 framing module according to respective protocol frame formats, sending the FC ASM framing module and the FC 818 framing module into a transmission arbitration module for arbitration after framing is finished, and respectively transmitting the FC ASM framing module and the FC 818 framing module through the corresponding transmission module after the data is arbitrated;
In the data receiving direction, a first sending module based on an FC ASM protocol and a second sending module based on an FC 818 protocol in a flow_CTRL sending/receiving control module receive FC data packets from an FC switching network, and data and descriptors are obtained after analysis;
After the receiving arbitration module performs arbitration of the receiving module, the framing module pre-reads the descriptor obtained by analysis, searches the address according to the relation between the channel and the address, segments and packs the data according to the length of the data to obtain a plurality of data packets corresponding to the SRIO frame head, and finally obtains a data frame conforming to the AXIS protocol through I port conversion and sends the data frame to the SRIO_IP core.
As an optional implementation manner, the sorting module obtains channel numbers based on the mapping relation between addresses and channel numbers, so that one channel number corresponding to each frame of data is determined, the mapping relation is configured through a blueprint, and after the FPGA of the FC device is powered on, the blueprint flash information is read for configuration.
As an alternative embodiment, as shown in connection with fig. 2, the sorting module is arranged to sort and buffer data in the following way:
defining a description field of incomplete transactions in each pair of source ID/target ID in the SRIO HELLO frame, sequencing the HELLO frame according to the field, and TID epsilon [0,255];
setting 3 pointers, namely p_wr, p_rd and p_rd_next respectively, wherein p_wr is a write pointer, p_rd is a read pointer and p_rd_next is a pre-read pointer;
Using TID as data RAM address, HELLO frame payload as data RAM content, sequentially storing in data RAM;
taking TID as an address of a mark RAM, taking 1 or 0 as the content of the mark RAM, and initially marking the content as 0, marking the corresponding content as 1 when a HELLO frame corresponding to the TID is received, and resetting the content marking corresponding to the TID when data is sent to a lower level;
When judging that the corresponding mark contents of the positions pointed by the p_rd and the p_rd_next are 1, sending the data RAM contents on the p_rd position to a lower stage, adding 1 to the p_rd and the p_rd_next, and simultaneously clearing the mark contents;
And stopping sending until the write pointer p_wr catches up with p_rd when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, sending the residual data content on the p_rd position to the lower stage, adding 2 to the p_rd and p_rd_next pointers simultaneously, and exceeding the pointer position where data is not received for a long time, and after exceeding, continuing judging the data receiving condition according to the previous flow to finish the cyclic sequencing operation.
Example 1
In this example, the overall logic of an FC device based SRIO multichannel communication system is shown in fig. 1.
Data transmission
As shown in fig. 1, the direction from SRIO IP to FLOW CTRL is the data transmission direction, i.e., the data transmission direction from left to right in the drawing.
The data flows into the FPGA through the SRIO protocol frame, is converted into a data stream through the SRIO_IP core, is sent into a T port, is subjected to frame analysis, and extracts descriptor information in a frame header, wherein channel number mapping is performed by utilizing address information in the frame header (it is understood that the mapping relationship is configured by blueprint configuration, and the blueprint flash information is read for configuration after the FPGA is powered on), so that channel numbers are obtained, and therefore, each frame of data corresponds to one channel number.
The analyzed data are respectively sorted according to TID (TID is a descriptor in a frame header, each channel is incremental) according to different channel numbers in a sorting module, after sorting is completed, the data enter an arbitration module to arbitrate, one data are distributed to two paths to carry out different FC protocol framing (FC ASM and FC 818 protocols are taken as examples to describe, other FC protocol frames can be replaced), and finally the data are transmitted to opposite terminal equipment through a transmitting module to complete data transmission in a transmitting direction.
Data reception
As shown in connection with fig. 1, the direction from FLOW CTRL to srio_ip core, i.e., the right-to-left direction in the illustration, is the data reception direction.
After the data from the FC switching network is received by the receiving module, the analysis of protocol frames is completed, after the analysis is completed, the arbitration module performs arbitration of two paths of data, the data is sent to the framing module after the arbitration is completed, respective data packet segmentation and framing are respectively performed according to different FC types, the data length is segmented into payload conforming to the SRIO data length, each payload corresponds to one frame head, the data is converted into data frames conforming to an AXIS protocol through an I port and sent to an SRIO_IP core, and finally the data frames are sent out by the SRIO_IP core, so that the data transmission in the receiving direction is completed.
Ordering of
In connection with fig. 1 and 2, in an embodiment of the present invention, TID is a description field of outstanding transactions in each pair of source ID/target ID in an SRIO HELLO frame, according to which HELLO frames are ordered.
3 Pointers, p_wr, p_rd, p_rd_next are set, where p_wr is the write pointer, p_rd is the read pointer, and p_rd_next is the pre-read pointer.
In the example shown in fig. 2, described with TID e 0,255, HELLO frames payload are sequentially stored in the data RAM as the contents of the data RAM, using TID as the data RAM address.
Similarly, when a HELLO frame corresponding to a TID is received, the corresponding content flag is 1, and when data is sent to a lower level, the content flag corresponding to the TID is cleared;
When the corresponding mark content of the positions pointed by p_rd and p_rd_next is judged to be 1, the data RAM content on the p_rd position is sent to the lower stage, the p_rd and p_rd_next are added with 1, the mark content is cleared, when the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, the sending is stopped until the write pointer p_wr catches up with p_rd (representing that the overtime/fifo is fast full, the difference value can be set), the residual data content on the p_rd position is sent to the lower stage, then the pointers of p_rd and p_rd_next are added with 2 simultaneously, and the pointer position without receiving data for a long time is passed.
After the data is passed, the data receiving condition is judged according to the previous flow, and the cycle is completed.
In connection with the embodiment of the present invention, the advantage of using the ordering method is that, due to the design defect of hardware, the TID under a single channel may not be continuous all the time, and jump may occur, as shown in c in fig. 2, when TID is 254, it is not received (blue mark is received, white mark is not received), at this time, if the reference clock used is changed due to the counting timeout, the time deviation of the counting timeout will be larger, and by using the way of calculating the difference between the write pointer and the read pointer, the excessive time deviation can be avoided, and at the same time, a buffer margin is reserved for waiting to receive the missing TID.
Data framing and arbitration
The data framing and arbitration flow under the multi-channel is shown in fig. 3, and after the data is ordered, the data is sent into Payload fifo for buffering according to different channels.
The FC ASM framing module and the FC 818 framing module pre-read the descriptors in the Payload fifo to determine whether the data is FC ASM data, FC 818 data, or two-way data (two-way data requires that one data be copied twice and sent to ASM and 818 respectively).
After the framing module reads the data, framing is carried out according to the respective protocol frame format, after framing is completed, a completion signal is sent to the arbitration module, asm protocol frames under all channels are arbitrated together, 818 protocol frames under all channels are arbitrated together, and after the data is arbitrated, the data frames are sent out through asm ip and 818 ip.
In examples of the invention, arbitration may be implemented using existing algorithms. For example, an equalization algorithm is adopted, the weights in the algorithm can be configured (the weights are high, the number of times to be read is large), or an adaptive mode of port flow is adopted (the weight in the next time T is determined according to the flow in the time T, and when the weights of all channels are the same during initialization, the polling mode is adopted for reading).
Data transmission
The data processing flow in the transmission direction is shown in fig. 4.
In the transmitting direction, one frame 256B SRIO frame data flows in, then enters the SRIO_IP core and is converted into AXIS interface data to be output, the data enters the T module, the module converts the AXIS interface data into a common data stream, and meanwhile, information in the SRIO frame header is extracted to be used as a subsequent descriptor, wherein the information comprises TID, type, address and data length information.
The data and descriptors are placed in the cache separately. Meanwhile, the T module also decides whether to carry out a packet returning to the SRIO_IP core according to the type.
The lower order module pre-reads the descriptor, maps the address and the channel of the descriptor, and sends the 256B data into the appointed RAM for caching according to the TID fields under different channels.
After the sorting is completed, the 256B data and the new descriptor are respectively stored in a cache, judgment is carried out according to the data content, and the FC type is added to the descriptor.
And (3) writing data into different framing modules according to the type of the FC (fiber channel), and when the framing modules read n 256 data packets with the length of one FC frame, writing the data frames after framing into a buffer memory and waiting for arbitration.
When the arbitration hits, the corresponding data frame is read out and sent out through FC ASM ip and FC818 ip.
In the special case, in the sorting module, two pointers are used to determine whether to send out data, and then the data sending out mode of the last frame is according to eop fields in the data descriptor, since the SRIO protocol frame does not contain sop and eop, the start and end of the defined frame are added in the data, wherein 4B is used to represent sop,4B is used to represent eop, and in addition, the format, type, length, line number and other information of the FC 818 image are defined in the data.
Data reception
The flow of the reception direction data processing is shown in fig. 5.
In the receiving direction, there is a frame payload length 2096B of FC ASM packet, after being parsed by FC ASM ip, the frame header obtains information such as SID, DID, MSG ID, frame length, etc., where MSG ID is a channel number for use, and descriptors and data are stored in different buffers respectively.
After arbitration and selection by the arbitration module, the descriptors are pre-read by the framing module, the addresses are found according to the relation between the channel numbers and the SRIO addresses, and the data are segmented into 8 256B and 1 48B data packets conforming to the SRIO protocol according to the length of the data payload. It should be understood that the 9 data packets respectively correspond to the frame heads of 9 SRIOs, the TID field is managed according to the channel number, and finally, the data frames which are read by the I port and converted into the data frames conforming to the AXIS protocol are sent out to the srio_ip core, and finally, the data frames are sent out by the srio_ip core, so that the data transmission in the receiving direction is completed.
While the invention has been described with reference to preferred embodiments, it is not intended to be limiting. Those skilled in the art will appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the present invention. Accordingly, the scope of the invention is defined by the appended claims.