CN120011303A

CN120011303A - A heterogeneous reconfigurable signal processing SIP chip

Info

Publication number: CN120011303A
Application number: CN202411971543.8A
Authority: CN
Inventors: 陆振林; 刘轶凡; 任永正; 赵轩; 孙世凯; 李沛剑; 刘治良; 赵宇航
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2024-12-30
Filing date: 2024-12-30
Publication date: 2025-05-16

Abstract

The present invention relates to a heterogeneous reconfigurable signal processing SIP chip. The physical reconfigurable microsystem architecture includes three types of sub-microsystems for control-intensive, computation-intensive and data-intensive applications. The first sub-microsystem with CPU as the core is oriented to control-intensive applications, including FLASH to realize core configuration, cache SRAM or DDR to realize operation cache, the second sub-microsystem with FPGA as the core is oriented to data-intensive applications, including cache DDR to realize high-speed operation cache, high-speed interface chip, radio frequency chip and other high-frequency interface chips or two, the third sub-microsystem with DSP as the core is oriented to computation-intensive applications, including DDR to realize high-speed data cache and high-speed interface chip to realize high-speed data transmission.

Description

Heterogeneous reconfigurable signal processing SIP chip

Technical Field

The invention relates to a heterogeneous reconfigurable signal processing SIP chip, and belongs to the technical field of system-in-package.

Background

Along with the gradual trend of moore's law to the limit, soC development faces the risks of yield reduction and cost increase, and system-in-package completes the integration of system functions through the packaging of a plurality of finished bare chips, and has the characteristics of low cost and rapid production, so that the SoC is one of the important directions of technical development.

In the prior art, heterogeneous chips are mainly packaged, the application of SiPs has special characteristics, and each new requirement needs to redevelop the whole substrate once, so that the cost is high.

Disclosure of Invention

The invention solves the technical problems of overcoming the defects of the prior art and providing a heterogeneous reconfigurable signal processing SIP chip which is freely combined and matched according to application requirements to form different signal processing systems.

The invention solves the technical problem by adopting a scheme that the isomerism reconfigurable signal processing SIP chip comprises a substrate, a first subsystem, a second subsystem and a third subsystem;

the bottoms of the first subsystem, the second subsystem and the third subsystem are independently packaged by adopting a substrate with the same size, the same pin number, solder balls with the same size and the same spacing;

the substrate is divided into four identical areas for packaging a first subsystem, a second subsystem and a third subsystem, and a matched peripheral circuit and a connecting circuit are provided for the first subsystem, the second subsystem and the third subsystem to form a SIP chip for signal processing;

the number and the positions of the first subsystem, the second subsystem and the third subsystem can be configured according to actual needs.

Preferably, the first subsystem comprises a CPU, FLASH and a cache;

The FLASH is used for storing a configuration program of the CPU, the cache is used for storing intermediate data in the running process of the CPU, and the CPU completes corresponding signal control functions according to the configured program.

Preferably, the cache is SRAM or DDR.

Preferably, the second subsystem comprises a cache DDR, a data interface chip, an AD and a DA;

The DDR is used for realizing the cache of data, the high-speed interface chip is used for realizing data exchange with the outside, the AD is used for carrying out analog-to-digital conversion on signals, the DA is used for carrying out digital-to-analog conversion on the signals, and the FPGA completes corresponding signal processing functions according to configured programs.

Preferably, the second subsystem comprises a cache DDR, a data interface chip and a radio frequency chip;

The DDR is used for realizing the cache of data, the interface chip is used for realizing the data exchange with the outside, the radio frequency chip is used for receiving radio frequency signals and carrying out radio frequency signal processing, and the FPGA completes corresponding signal processing functions according to configured programs.

Preferably, the third subsystem comprises a DSP, a cache DDR and a data interface chip

The DDR is used for realizing the cache of data, the data interface chip is used for realizing the data exchange between the third subsystem and the outside, and the DSP is used for completing the corresponding calculation processing function according to the configured program.

Preferably, the first subsystem, the second subsystem and the third subsystem adopt packaging forms of plastic packaging or metal cap packaging.

Preferably, the plastic package is used for preferentially packaging the full-wire bonding bare chip from the aspect of packaging cost, the full-inverted packaging is used for the second time, the wire bonding and inverted mixed packaging can be adopted at last, and the metal cap can only be used for fully inverted bare chip from the aspect of process realization;

Preferably, the substrate is packaged in the form of a ceramic BGA package.

Compared with the prior art, the invention has the beneficial effects that:

(1) The isomerism reconfigurable processing SIP chip of the invention enables a single core to have the function of an independent processing part by decoupling functions and frameworks among different cores, and the different cores and the independent matched circuits are independently packaged to form a subsystem, and the different cores are packaged in the packaging process, so that the whole microsystem packaging is realized, and the microsystem is formed.

(2) The subsystem of the invention can realize independent system functions, can be used independently, and the whole subsystem can be combined by different subsystems to realize complex system functions.

(3) The invention adopts the scheme of packaging in the package, realizes the modularized design of the sub-SiP and the reconfigurability of the package in the package by adopting the method of the standard bonding pad interface, simplifies the design flow of the secondary packaging substrate on the basis of meeting the functions, and reduces the cost of the package in the package.

Drawings

FIG. 1 shows the internal components of a first subsystem according to an embodiment of the present invention.

FIG. 2 shows the internal components of a second subsystem according to an embodiment of the present invention.

FIG. 3 shows the internal components of a third sub-system according to an embodiment of the present invention.

FIG. 4 is a first embodiment of a system architecture according to the present invention;

FIG. 5 is a system architecture according to a second embodiment of the present invention;

FIG. 6 is a first implementation of a second sub-subsystem according to an embodiment of the present invention;

FIG. 7 is a second implementation of a second sub-subsystem according to an embodiment of the present invention;

FIG. 8 is a third implementation of a second sub-subsystem according to an embodiment of the present invention;

FIG. 9 is a third embodiment of a system architecture according to the present invention;

Fig. 10 is a system architecture according to a fourth embodiment of the present invention.

Detailed Description

The invention is further illustrated below with reference to examples.

A heterogeneous reconfigurable signal processing SIP chip comprises a substrate, a first subsystem 1, a second subsystem 2 and a third subsystem 3, wherein the SIP chip is shown in figures 1,2 and 3. The three sub-microsystems respectively take a CPU, a DSP and an FPGA as cores.

Preferably, the first subsystem comprises a CPU, FLASH and a cache;

Preferably, the cache is SRAM or DDR. The CPU is used for storing intermediate data in the running process of the CPU, has rich control functions, and is suitable for control intensive applications.

Preferably, the second subsystem comprises a cache DDR, a data interface chip and a radio frequency chip, wherein the data interface chip comprises 8255A, 8250, RS485, PCIE and the like.

Preferably, the substrate is packaged in the form of a ceramic BGA package.

The packaging forms of the cavities of the first subsystem 1, the second subsystem 2 and the third subsystem 3 can be the same or different, but the bottoms of the first subsystem and the second subsystem are all provided with the base plates with the same size and the solder balls with the same size and the same spacing so as to meet the consistency of the interfaces;

The packaging modes which can be adopted by the first subsystem 1, the second subsystem 2 and the third subsystem 3 comprise plastic packaging and metal cap packaging, wherein plastic packaging is adopted when the power consumption of the internal device is smaller, and the metal cap packaging is adopted when the power consumption of the internal device is larger;

The plastic package is used for preferentially packaging the full-lead bonding bare chip from the aspect of packaging cost, the full-inverted packaging is used for the second time, and finally, the lead bonding and inverted mixed packaging can be adopted, and the metal cap can only adopt the full-inverted bare chip from the aspect of process realization;

The reconfigurable microsystem selects 2, 3 or 4 identical or different microsystems 1, 2 and 3 to package according to application requirements, packaging is realized in the packaging, the reconfigurable microsystem architecture adopts ceramic BGA (ball grid array) packaging, the substrate of the reconfigurable microsystem is divided into four identical areas for packaging the microsystems, and the unified packaging substrate can reduce manufacturing cost by increasing quantity.

Example 1

The intelligent decision-making controlled heterogeneous reconfigurable processing SIP chip has an application architecture shown in figure 4, wherein the application architecture comprises 1 first subsystem, 2 second subsystems and 1 third subsystem;

wherein a first subsystem 1 is used to handle control-intensive demands and a second subsystem 2 is used to handle computation-intensive demands.

The types of bare chips contained in the 2 second subsystems are shown in fig. 6 and 7 respectively, the subsystem 2 in fig. 6 comprises a DDR, a high-speed interface, an AD and a DA for processing external analog signals, the subsystem 2 in fig. 7 comprises a DDR, a high-speed interface and a radio frequency chip, the high-speed interface is used for carrying out information transmission on a data board with the outside, and the radio frequency chip is used for communication.

Example 2

An intelligent decision-making controlled heterogeneous reconfigurable processing SIP chip comprises 1 first subsystem and 3 second subsystems in an application architecture, as shown in figure 5.

The 3 second subsystems comprise 1 second subsystem of the bare chip type, as shown in fig. 6 and 2 second subsystems shown in fig. 8, wherein the second subsystem in fig. 6 comprises DDR, high-speed interface, AD and DA for realizing sampling and outputting of external analog signals, and the subsystem 2 in fig. 7 comprises DDR radio frequency chip for multipath signal communication;

example 3

An intelligent decision-making controlled heterogeneous reconfigurable processing SIP chip has an application architecture shown in FIG. 9, wherein the intelligent decision-making controlled heterogeneous reconfigurable processing SIP chip comprises 1 first subsystem and 1 second subsystem;

The second subsystem comprises a bare chip type shown in fig. 2, and the second subsystem of fig. 2 comprises a DDR, a high-speed interface, an AD and a DA for realizing external ultrahigh frequency sampling and output;

Example 4

An intelligent decision-making controlled heterogeneous reconfigurable processing SIP chip has an application architecture shown in FIG. 10, wherein the intelligent decision-making controlled heterogeneous reconfigurable processing SIP chip comprises 1 first subsystem and 1 third subsystem;

Wherein the third subsystem is for computationally intensive demands and the first subsystem is for control of the intensive subsystem;

The physical reconfigurable microsystem also has a plurality of different combination modes, the number of the subsystems is more than or equal to 2 and less than or equal to 4, and the subsystems can be freely combined and matched according to application requirements. In the subsystems, the second subsystem can be used for combining the bare chips according to application requirements, so that the application flexibility of the system is improved.

In the packaging form, the substrate size, the pin size, the spacing and the distribution of the subsystem are consistent, the packaging substrate can be selected according to the application requirements, the power consumption and the like, and the packaging material can also be selected according to the application requirements. The physically reconfigurable microsystem packaging substrate is a ceramic substrate to improve heat dissipation characteristics.

The subsystem of the invention can be used singly or combined into a physical reconfigurable subsystem, thereby improving the application flexibility. The subsystems adopt a substrate packaging form, the forms of metal cover plates, plastic package filling and the like can be selected according to different heat dissipation requirements, the first subsystem 1, the second subsystem 2 and the third subsystem 3 adopt packaging substrates with the same size, pin numbers and solder balls, a four-cavity reconfigurable subsystem substrate is designed based on the subsystem packaging form, 4 subsystems can be placed on the substrate, 2, 3 and 4 subsystems can be arranged in a physical reconfigurable subsystem, and the subsystems can be freely combined.

Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.

Claims

1. A heterogeneous reconfigurable signal processing SIP chip, characterized by comprising a substrate, a first sub-microsystem, a second sub-microsystem, and a third sub-microsystem;

The bottoms of the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem are independently packaged using substrates of the same size, the same number of pins, and solder balls of the same size and spacing;

The substrate is divided into four identical areas for encapsulating the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem, and provides supporting peripheral circuits and connection circuits for the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem, so as to form a SIP chip for signal processing;

The number and position of the first sub-microsystem, the second sub-microsystem, and the third sub-microsystem can be configured according to actual needs.

2. According to claim 1, a heterogeneous reconfigurable signal processing SIP chip is characterized in that the first sub-microsystem includes a CPU, a FLASH and a cache;

FLASH is used to store the CPU configuration program, the cache is used to store the intermediate data during the CPU operation process, and the CPU completes the corresponding signal control function according to the configured program.

3. A heterogeneous reconfigurable signal processing SIP chip according to claim 1, characterized in that the cache is SRAM or DDR.

4. According to claim 1, a heterogeneous reconfigurable signal processing SIP chip is characterized in that the second sub-microsystem includes a cache DDR, a data interface chip, an AD, and a DA;

DDR is used to implement high-speed data caching, high-speed interface chips are used to implement data exchange with the outside, AD is used to perform analog-to-digital conversion on signals, DA is used to perform digital-to-analog conversion on signals, and FPGA completes the corresponding signal processing functions according to the configured program.

5. According to claim 1, a heterogeneous reconfigurable signal processing SIP chip is characterized in that the second sub-microsystem includes a cache DDR, a data interface chip, and a radio frequency chip;

DDR is used to implement high-speed data caching, the interface chip is used to implement data exchange with the outside, the RF chip is used to receive RF signals and perform RF signal processing; FPGA completes the corresponding signal processing function according to the configured program.

6. According to claim 1, a heterogeneous reconfigurable signal processing SIP chip is characterized in that the third sub-microsystem includes a DSP, a cache DDR, a data interface chip

DDR is used to implement high-speed data caching, the data interface chip is used to implement data exchange between the third sub-microsystem and the outside; DSP is used to complete corresponding calculation and processing functions according to the configured program.

7. A heterogeneous reconfigurable signal processing SIP chip according to claim 1, characterized in that the packaging form adopted by the first sub-microsystem, the second sub-microsystem and the third sub-microsystem is plastic packaging or metal cap packaging.

8. According to claim 1, a heterogeneous reconfigurable signal processing SIP chip is characterized in that from the perspective of packaging cost, plastic packaging gives priority to packaging fully wire-bonded bare cores, followed by full flip-chip packaging, and finally mixed packaging of wire bonding and flip-chip can be used; from the perspective of process implementation, metal caps can only use fully flip-chip bare cores.

9. The heterogeneous reconfigurable signal processing SIP chip according to claim 1, characterized in that the substrate is packaged in a ceramic BGA packaging form.