CN1299554A - Picture-in-guide generator - Google Patents

Abstract

A picture-in-guide generator (21) has an output adapted to drive a display monitor (62) and an input adapted to receive a television signal. A display generator (34) feeds drive signals to the output in synchronism with the display monitor (62). EPG information is extracted from the television signal and stored in memory (26). The pixel size of the television signal is reduced. The reduced pixel size television signal is stored in memory (26). The EPG data and the television signal are retrieved from memory (26) and stored in the display generator (34). The EPG data and the television signal are fed from the display generator (34) to the output in a continuous data stream ordered to produce a picture-in-guide display (10) on the monitor (62). Preferably, the picture-in-guide generator (21) is implemented on a single integrated circuit chip.

Description

report-in-picture generator

This application claims priority to US Application No. 60/072,428, filed January 26, 1998, the disclosures of which are incorporated herein by reference in their entirety.

The contents disclosed in the following patent applications are also fully incorporated herein by reference: application No.08/475,395 filed on June 7, 1995; international application W096/07270; application No.60/ 053,330; Application No. 60/061,119, filed October 6, 1997; and Application No. 60/055,237, filed August 12, 1997. The publication "The CTC 140 Picture in Picture System (CPIP) Technical Training Manual", Thomson Consumer Electronics, Inc. Indianapolis, IN, is also incorporated by reference.

The electronic program guide (EPG) provides TV viewers with updatable TV program schedule information in the form of screen graphics. The EPG can provide information on the schedule of current and future broadcast programs, as well as a summary of the television program content of certain programs.

A particularly convenient EPG format is the picture-in-guide (PIG) display. The PIG displays a program guide consisting of a large graphic and a real-time video image of the TV program being watched displayed in a small window within it. Such PIG displays offer the viewer many options. The viewer can browse the TV schedule information in the guide while continuing to watch the TV programs he watched when he entered the guide. Or, when the viewer's cursor passes over the program in the guide, the program displayed in the PIG window can be converted to the corresponding selected channel in the guide. The viewer can also scroll through the PIG display to find more information about the program he is currently viewing, such as start/stop times or a program summary, while continuing to watch the program within the embedded PIG window.

Usually, the PIG EPG display is generated with an EPG generator, which includes: a microprocessor, a vertical blanking interval (VBI) decoder/limiter, an on-screen display generator, a digital-to-analog converter (DAC), a synchronization (synch) circuit, and a memory configured on one chip, and a picture-in-picture (PIP) generator, a DAC, synchronization signal circuit and microprocessor interface circuit configured on another chip.

The PIP generator makes two video signals generate a large background picture and a small embedded picture respectively. This small picture is produced by decimating a sub-video signal, for example, writing one pixel out of every three pixels out of one out of every three lines into the video memory. By scanning the large frame normally, and switching to scanning the small frame image with a quick switch when the scanner is in the PIP window area of the display monitor screen, a composite display with the large frame background and the small frame embedded is produced. Therefore this fast switch must work at the line scan frequency of the display monitor.

However, for the PIG display, it is not necessary to provide two real-time video images, because the main part of the display includes text and graphic information, such as program guides, rather than real-time moving video images. PIP snap switches are more expensive. Also, separate chips for the EPG generator and the PIP generator require more devices, making it difficult to integrate into home appliances, such as television receivers, VCRs, satellite receivers, and so on.

Therefore, it is desirable to integrate on a single chip the components necessary to provide a PIG display.

The picture-in-picture generator proposed by the present invention has an output suitable for driving a display monitor and an input suitable for receiving television signals. The display generator feeds the drive signal to this output synchronously with the display monitor. EPG information is stored in the memory after being extracted from the TV signal. The pixel size of the TV signal is reduced and stored in the memory. EPG data and TV signals are retrieved from memory and stored in the display generator. The EPG data and the television signal are fed from the display generator to the output in a continuous stream to produce a picture-in-picture display on the monitor. Preferably, the report-in-picture generator is implemented on a single integrated circuit chip.

Specific embodiments of the best modes for carrying out the invention are illustrated in the accompanying drawings, in which:

Figure 1 illustrates a program guide display in a picture-in-picture (PIG) format;

Fig. 2 is the schematic diagram of the PIG generator designed according to an embodiment of the present invention;

Fig. 3 is the schematic diagram of the data structure in RAM designed according to an embodiment of the present invention;

Fig. 4 is the schematic diagram of the YUV component of standard color bar video signal; And

FIG. 5 is a schematic diagram of an analog-to-digital conversion and clamping circuit designed according to an embodiment of the present invention.

In accordance with the present invention, a picture-in-picture (PIG) generator is configured to generate a PIG display on a television screen or computer monitor. There are generally two display types available in television systems using the PIG generator. The first type is a full-screen display of a live image of a broadcast TV program. The second type, the PIG display, consists of a background graphic and a live video image within a small embedded window.

FIG. 1 illustrates a PIG display 10 of an Electronic Program Guide (EPG), including a graphics portion 12 and a picture window 14. As shown in FIG. Picture window 14 is referred to as PIG window below, contains the TV program TV (image) image that a full-screen video shows, but size has dwindled, and usually all dwindles to 1/3rd on width and height, that is to say, is full-screen video. 1/9 of the screen size. Another possible screen displayed by the PIG system is a full screen graphics display.

Graphics portion 12 of PIG display 10 occupies most of the screen. The graphics section usually includes text, icons, and background graphics in several different colors. Graphics can include text or highlight areas of the screen. In an EPG system, the viewer can generally browse through different guides without changing the television program displayed in the PIG window 14. In some EPG systems, when the viewer places the cursor 16 on a different channel logo 18 or program title 20 in the graphic part, the system automatically tunes the associated tuning circuit 50 to the selected channel, and the PIG window 14 shows the programs broadcast on this channel.

In accordance with a preferred embodiment of the present invention, the components necessary to form the PIG display 10 are configured on a single chip for incorporation into a television receiver, VCR, stand-alone unit, or satellite receiver, or the like. By having all components on a single chip, the size of the overall assembly can be reduced, and the chip's gate count and bus interface size can be reduced.

FIG. 2 is a schematic diagram of some components of a preferred embodiment of the present invention configured on a single chip 21. These components include: microprocessor 22, memory controller or direct memory access (DMA) device 24, random access memory (RAM) 26, sync regeneration (sync signal) circuit 28, analog-to-digital conversion (ADC) and clamp Bit circuit circuit 30 , PIG window generator 32 , display generator 34 , and digital to analog conversion (DAC) circuit 36 .

Microprocessor 22 receives original text data from a data source, such as EPG data, and writes it into RAM 26. For example, EPG data may be embedded in the vertical blanking interval of the television signal received by television tuner 50 and extracted by VBI decoder/limiter 37 . Preferably, the RAM 26 has a storage capacity of 4M bits or more, and includes a data RAM 31 storing text data and a video RAM (VRAM) 31 storing video data, and a working memory between the data RAM 31 and the VRAM 33. The free zone of the zone is shown in Figure 3. Microprocessor 22 organizes the data storage in RAM 26, can specify address for text data and video data. However, microprocessor 22 is relatively slow compared to video processing hardware, such as PIG window generator 32 and display generator 34 . Therefore, microprocessor 22 typically only processes access data and text data, not video data. The microprocessor communicates bidirectionally with the DMA 24. The microprocessor 22 communicates with the DMA 24 and accesses the RAM 26 via a data bus and an address bus.

Even better, there is only one RAM. This RAM 26 is accessed by three different components: the microprocessor 22, the PIG window generator 32 and the display generator 34. This makes RAM highly accessed since all three components may compete for access to RAM at the same time. However, only one sample of as many bits (e.g., 8 bits for a 516KX8bit RAM) can be accessed per access cycle. To resolve arbitration between components, a multiplexer is required. Thus, microprocessor 22, PIG window generator 32 and display generator 34 each access RAM via DMA 24. The DMA 24 is a multiplexing and arbitration circuit that enables these three components to access the shared RAM 26 sequentially. The DMA 24 includes buffer memories to temporarily store data coming in from out-of-sequence components between access cycles. The DMA 24 stores the text data and video data in the correct address in the RAM 26, and then retrieves the correct data from the RAM according to the selected address if necessary.

As mentioned above, the RAM 26 preferably has a storage capacity of 4M bits or more, subject to a high access load. A method for adapting to this high access load and speeding up data transmission is to select 256KX1 6bit RAM instead of 51 2KX8bit RAM, so that each access cycle of DMA 24 can access more information, that is to say, it is 16 bits instead of Not 8 bits. The system receives a video signal from tuner circuit 50 . The horizontal and vertical (h- and v-) sync signals separated from the video signal are supplied to a sync signal circuit 28 . The synchronization signal circuit includes a pixel clock 28 . The pixel clock determines the x and y coordinates of each pixel displayed on the screen. The y-coordinate corresponds to the screen scan line number, and the x-coordinate corresponds to the pixel number in each scan line.

The video portion input from the tuner circuit 50 is converted into a YUV analog video signal by a chrominance processor 52 in the television receiver. This is an intermediate signal conversion between the input video and the RGB signals displayed on a cathode ray tube (CRT) 62, commonly used in television systems.

Figures 4A, 4B and 4C illustrate the YUV components 54, 56, 58, respectively, of a standard color stripe video signal. Component 54 is a luminance (Y) signal with horizontal sync pulse 55 . Component 56 is the color signal (V). Component 58 is the trailing region of the chrominance signal (U) used for video clamping. Each component of the signal is converted to digital form by an ADC/clamp circuit 30 (see Figure 5 for details). The clamping portion of the ADC/clamping circuit 30 reduces distortion in the signal due to, for example, low frequency noise and DC bounce when converting the signal.

The PIG window generator 32 receives a digital YUV video signal corresponding to a full screen video image. The PIG window generator reduces the size of the entire picture by extracting video data and sends it to DMA24 for storage in VRAM. In order to extract video data, the PIG window generator 32, in cooperation with the synchronous signal circuit 28, selects one scan line from every three scan lines, and then selects one pixel from every three pixels of this scan line (that is to say, 1/3) to send For DMA 24, stored in VRAM 33. Other decimation ratios are also possible, such as 1/4, to form PIG windows of different sizes.

The correct address for storing the video data from the PIG window generator 32 into the VRAM 33 is determined by the address translation circuit 40, which is preferably incorporated within the DMA 24. Using synchronization signals from synchronization signal circuit 28 and pixel clock 38, address mapping circuit 40 stores video data corresponding to each pixel on the CRT at the correct address in VRAM for later display access. This processing is often referred to as "bitmapping".

The display generator 34 includes a graphics generator for formatting the display text fonts, icons, colors and highlighting and background graphics of the PIG display 10 . The graphics data is sent to the address mapping circuit 40, and it stores the video data in the VRAM33 at the address corresponding to the coordinates of the pixels on the screen under the cooperation of the DMA 24.

The production of PIG display 10 (FIG. 1) according to the present preferred embodiment will now be described. Microprocessor 22 responds to a viewer's command device 70, such as an infrared remote control, for a given PIG EPG display, accessing data RAM 31 to read the appropriate text data for that display from the original text data. Microprocessor 22 configures the text data for display, together with the appropriate address for displaying this text, sent to DMA 24, stored in VRAM 33.

All video data used to form PIG display 10, including text and graphics data for graphics portion 12 and video image data for PIG window 14, is stored in VRAM 33, as described above. The display generator 34 reads the pre-organized VRAM content under the cooperation of the address mapping circuit 40 and the synchronous signal circuit 28, and generates an image for displaying on the screen of the CRT 62. The data of each pixel to be displayed on the screen is stored in the VRAM 33 at an address corresponding to the pixel's x and y coordinates on the screen. The display generator 34 uses the synchronization signal from the synchronization signal circuit 28 to read corresponding data from the VRAM 33 for each pixel in sequence determined by the pixel clock 38. The sync signal is generated by sync signal circuit 28 based on the h and v sync signals in the input video.

Although it is preferable to store information groups or frames of the entire screen into the VRAM 33 in bit-mapped form at one time, it is also possible to store less than the entire screen at one time, that is to say, only a part of the screen, and the display processing is actually performed in a manner smaller than the entire screen. Performed in units of pixel groups.

The display generator 34 converts the digital YUV signal of each pixel and sequentially outputs it to the DAC circuit 36 in the form of a continuous data stream, so that a report-in-picture display similar to that shown in FIG. 1 can be generated on the screen of the CRT 62. The DAC circuit converts the data into an analog YUV video signal. The analog YUV video signal is then transformed into an analog RGB signal by the RGB conversion circuit 60 in the television receiver, and then displayed on the screen of the CRT 62.

In another embodiment of the present invention, RAM 30 is arranged outside chip, is connected to DMA 24 by data bus.

Tuner circuit 50, chrominance processor 52, RGB converter 60, CRT 62 and viewer command device 70 are all part of a television receiver. In other words these parts have a dual role and can be used to display a TV signal, usually in full screen format, or in newspaper-in-picture format. Other parts are only available in the picture-in-picture format.

This design of the PIG circuit on a single chip 21 in accordance with the present invention provides a more economical assembly, small in size and low in gate count. Since the present invention only needs a single gate array for the microprocessor 22, the synchronous signal circuit 28, the DAC circuit 36 and the DMA 24 each, rather than for the television system that is used for the known PIG display, it is configured in an independent PIP respectively. Each of these components on the EPG and EPG chips requires two gate arrays, thus reducing the total gate count. It should also be noted that display generator 34 feeds both image information and EPG information to CRT 62 in a continuous data stream under the control of pixel clock 38 and sync signal circuit 28. Therefore, video (ie, moving picture) images can be generated in the EPG display without high-speed switching.

The described embodiments of the invention are only preferred and illustrative examples of this inventive solution, and the scope of the invention is not limited to such embodiments. Those skilled in the art can devise various other configurations within the scope of the present invention as long as they follow the spirit of the present invention. For example, separate RAMs can be used to store EPG data and downscaled TV signals. In addition, the present invention can also be used in a digital TV transmission system, in this case, the ADC, DAC and VBI limiter can be omitted.

Claims (4)

1. Picture-in-guide maker comprises:

An output that is fit to drive a display monitor;

One with synchronously the feed display generator of described output of drive signal and display monitor;

The input of a suitable received television signal;

Be connected to described input, be used for from described TV signal extracting the device of EPG information;

Be used for the device of described EPG information stores in memory;

Be used for dwindling the device of the pixel scale of described TV signal;

Be used for the TV signal that pixel scale has been dwindled is stored in device in the memory;

Be used for going out the device of described EPG data and TV signal from memory search;

Being used for the EPG data that will be retrieved and TV signal is stored in device in the described display generator; And

Be used for EPG data and TV signal are fed to described output so that produce the Picture-in-guide device shown at described monitor so that continuous data is streamed from described display generator.

2. the Picture-in-guide maker of claim 1, described Picture-in-guide maker is realized with the form of single integrated circuit sheet.

3. the Picture-in-guide maker of claim 2, wherein said extraction element is a VBI decoder.

4. the Picture-in-guide maker of claim 3, wherein said memory comprises one or more RAM.

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