CN1299363C - Complementary Metal-Oxide-Semiconductors and Composite Components - Google Patents

Abstract

The invention provides a complementary metal oxide semiconductor, which is composed of a first type thin film transistor and a second type thin film transistor, wherein the first type thin film transistor comprises a grid electrode, a channel region, a first type doped region and a source electrode doped region, and the channel region, the first type doped region and the source electrode doped region are arranged along a first direction. The second type thin film transistor includes a gate, a channel region, a second type doped region and a drain doped region, wherein the channel region, the second type doped region and the drain doped region are arranged along a first direction, and the second type doped region and the first type doped region are arranged along a second direction perpendicular to the first direction. The doped regions in each thin film transistor are electrically connected through a wire, wherein the extending direction of the wire is a second direction.

Description

Complementary Metal-Oxide-Semiconductors and Composite Components

technical field

The present invention relates to a low temperature polysilicon (low temperature poly-Si, LTPS for short) thin film transistor (thin film transistor, TFT for short), in particular to a low temperature polysilicon thin film transistor composed of two different types (type). Complementary metal oxide semiconductor (CMOS) and its combination components.

Background technique

With the development of high technology, video products, especially digital video or image devices have become common products in daily life. In these digital video or image devices, the display is an important component to display relevant information. Users can read information from the display, or further control the operation of the device.

Recently, in thin-film transistor liquid crystal displays, there is a kind of thin-film transistor made by polysilicon technology, whose electron mobility (mobility) is higher than that obtained by conventional amorphous silicon (a-Si) thin-film transistor technology. The ratio is much larger, so the thin film transistor element can be made smaller, the aperture ratio is increased (aperture ratio) and the brightness of the display is increased, and the power consumption is reduced. In addition, due to the increase in electron mobility, part of the driving circuit can be manufactured on the glass substrate at the same time as the thin film transistor process, which greatly improves the characteristics and reliability of the liquid crystal display panel, and greatly reduces the panel manufacturing cost. Therefore, the manufacturing cost is lower than that of amorphous silicon. TFT-LCDs are much lower. In addition, polysilicon has the characteristics of thin thickness, light weight, and good resolution, and is especially suitable for mobile terminal products that require light weight and power saving.

The early process of polycrystalline silicon thin film transistors used solid phase crystallization (solid phase crystallization, referred to as SPC) process, but under the high temperature process of up to 1000 degrees Celsius, it is necessary to use a quartz substrate with a higher melting point, because the cost of the quartz substrate is much more expensive than the glass substrate, and Under the limitation of the substrate size, the panel is only about 2 to 3 inches, so in the past only small panels can be developed. Later, due to the development of laser, laser crystallization (lasercrystallization) or excimer laser annealing (excimer laser annealing, referred to as ELA) process is used to make the amorphous silicon film into a polysilicon film, and the entire process is completed at a temperature below 600 degrees Celsius, so generally Only when the glass substrate used in the amorphous silicon thin film transistor liquid crystal display can be used can a larger size panel be produced, so the polysilicon formed according to this technology is also called low temperature polysilicon (LTPS).

In addition, due to the high electron mobility of polysilicon itself, usually during the liquid crystal display process, the driving circuit can be fabricated on the periphery of the display area, such as the complementary metal oxide semiconductor shown in FIG. 1A and FIG. 1B .

FIG. 1A is a schematic top view of a known CMOS including N-type low-temperature polysilicon thin film transistors and P-type low-temperature polysilicon thin film transistors, and FIG. 1B is a schematic cross-sectional view according to the I-I' section of FIG. 1A .

Referring to FIG. 1A and FIG. 1B , a known CMOS 10 includes an N-type LTPS thin film transistor 110 and a P-type LTPS thin film transistor 120 on a substrate 100 . N-type low-temperature polysilicon thin film transistor 110 includes a gate 102 and an island-shaped polysilicon (poly-island) layer 104, located between the gate 102 and the substrate 100, wherein the island-shaped polysilicon layer 104 has a channel region (channel region) 105 and the doped region 106 a and the doped drain region 106 b on both sides of the channel region 105 . The P-type low-temperature polysilicon film 120 has a gate 112 and an island-shaped polysilicon layer 114, located between the gate 112 and the substrate 100, wherein the island-shaped polysilicon layer 114 has a channel region 115 and two sides of the channel region 115. source doped region 116a, doped region 116b. In addition, an inter-layer dielectric (inter-layer dielectrics, ILD for short) 130 is covered on the N-type low-temperature polysilicon thin film transistor 110 and the P-type low-temperature polysilicon thin film transistor 120 . Moreover, the doped region 106a of the N-type low-temperature polysilicon thin film transistor 110 and the doped region 116b of the P-type low-temperature polysilicon thin film transistor 120 are electrically connected through a contact hole (contact hole) 132 in the interlayer dielectric layer 130 and a wire 122. sexually connected.

Please continue to refer to FIG. 1A and FIG. 1B, there is also a gate insulating layer (gate insulating film) 124 between the island polysilicon layers 104, 114 and the gates 102, 112, and a gate insulating film 124 between the substrate 100 and the island polysilicon layers 104, 114. There is also a buffer layer 126 in between. There is also a lightly doped drain region (LDD for short) 107 between the channel region 105 and the doped region 106 a/drain doped region 106 b of the N-type low temperature polysilicon thin film transistor 110 . Furthermore, there is usually a source/drain contact metal (source/drain contact metal) 128 connected to the source 116a and the drain 106b on both sides of the gate 102, 112 to form the source or drain.

However, it is known that the complementary metal oxide semiconductors fabricated on the periphery of the display area all present the layout shown in FIG. 116b cannot share the contact hole, so there must be a minimum separation distance (separate distance), as shown in Figure 1A, taking the width/length (width/length) equal to 6μ/6μ as an example, the overall width 142 is about 56μm. Therefore, in the traditional layout, the minimum width of the thin film transistor has been determined by the design rule, so that when the width of the pixel (pixel) is reduced and the resolution is improved, the driving circuit previously fabricated on the substrate may be due to the layout width exceeding problem and cannot be used.

Contents of the invention

Therefore, the object of the present invention is to provide a complementary metal oxide semiconductor and its combined components, so as to reduce its layout width, thereby improving resolution and solving the problem of insufficient space.

According to the above and other objectives, the present invention proposes a complementary metal oxide semiconductor, which is composed of a first type thin film transistor, a second type thin film transistor, an interlayer dielectric layer and a wire, wherein the first type thin film The transistor includes a first gate and a first island-shaped polysilicon layer, located under the first gate. The first island-shaped polysilicon layer includes a first channel region, a first source/drain and a first doped region, and the first channel region is located directly below the first gate, the first source/drain The drain is located on one side of the first gate, and the first doped region is located on the other side of the first gate, wherein the first source/drain and the first doped region are arranged in a first direction. Moreover, the second-type TFT is arranged side by side with the first-type TFT, and it includes a second gate and a second island-shaped polysilicon layer, located under the second gate. The second island-shaped polysilicon layer includes a second channel region, a second source/drain and a second doped region, and the second channel region is located directly below the second gate, the second doped The region is located on one side of the second gate, and the second source/drain is located on the other side of the second gate, wherein the second doped region and the second source/drain are aligned in the first direction. In addition, the interlayer dielectric layer covers the first type thin film transistor and the second type thin film transistor, and has a plurality of contact holes therein to expose the first doped region and the second doped region. The wire is located on the interlayer dielectric layer and connects the first doped region and the second doped region through the contact hole, wherein the extending direction of the wire is a second direction, and the second direction is perpendicular to the first direction.

The present invention further proposes a composite component of CMOS, including at least one first-type low-temperature polysilicon thin-film transistor, several second-type low-temperature polysilicon thin-film transistors, an interlayer dielectric layer, and several wires. And each first-type low-temperature polysilicon thin film transistor includes a first gate line and a first island-shaped polysilicon layer located under the first gate line, wherein the first island-shaped polysilicon layer has The lower first channel region, the first doped region on one side of the first gate line, and the second doped region on the other side of the first gate line. Each second-type low-temperature polysilicon thin film transistor includes a second gate line and a second island-shaped polysilicon layer located under the second gate line, wherein the second island-shaped polysilicon layer has a structure located directly under the second gate line. The second channel region, the third doped region on one side of the second gate line, and the source/drain doped region on the other side of the second gate line. Wherein, the interlayer dielectric layer covers the first type and the second type low temperature polysilicon thin film transistor, and the interlayer dielectric layer has several contact holes. The second-type low-temperature polysilicon thin film transistor and the first-type low-temperature polysilicon thin film transistor are arranged alternately, and are respectively connected to the first and third doped regions and the second drain through several wires and contact holes on the interlayer dielectric layer. pole and the third doped region, wherein the wire is parallel to the extension direction of the first gate line and the second gate line.

Since the present invention configures the layout of the first-type low-temperature polysilicon thin film transistor and the second-type low-temperature polysilicon thin film transistor to be parallel and staggered, the width of the complementary metal oxide semiconductor can be greatly reduced, thereby improving the resolution and solving the problem of insufficient space .

Description of drawings

1A is a schematic top view of a known complementary metal oxide semiconductor including an N-type low-temperature polysilicon thin film transistor and a P-type low-temperature polysilicon thin film transistor;

Fig. 1 B is a schematic cross-sectional view according to the I-I 'section of Fig. 1A;

2A is a schematic top view of a complementary metal oxide semiconductor (CMOS) according to a first embodiment of the present invention;

Fig. 2B is a schematic cross-sectional view according to the II-II' section of Fig. 2A;

3 is a schematic top view of a composite element of a complementary metal oxide semiconductor according to a second embodiment of the present invention;

Fig. 4A is a schematic sectional view according to the A-A' section of Fig. 3;

Fig. 4B is a schematic cross-sectional view according to the B-B' section of Fig. 3; and

Fig. 4C is a schematic cross-sectional view according to the C-C' cross-section of Fig. 3 .

10, 20: Complementary Metal Oxide Semiconductors

30: Combination components of complementary metal oxide semiconductors

100, 200: Substrate

102, 112, 202, 212: grid

104, 114, 204, 214, 304, 314: Island polysilicon layer

105, 115, 205, 215, 305, 315: channel area

106a, 116b, 306a, 306b, 316a: doped regions

106b, 206b: Drain doped regions

107, 207, 307: shallowly doped drain regions

110, 210, 310: N-type low temperature polysilicon thin film transistor

116a, 216a: source doped regions

120, 220, 320: P-type low temperature polysilicon thin film transistor

122, 222, 322a, 322b: wires

124, 224, 324: gate insulating layer

126, 226, 326: buffer layer

128, 228, 318, 319: Source/drain contact metal

130, 230, 330: interlayer dielectric layer

132, 232, 332: contact window hole

142, 242: overall width

206a: N-type doped region

216b: P-type doped region

302, 312: gate lines

316b: source/drain doped region

Detailed ways

first embodiment

The present invention can be applied to a low temperature polysilicon (low temperature poly-Si, LTPS for short) thin film transistor (TFT for short), please refer to FIG. 2A and FIG. 2B .

2A is a schematic top view of a complementary metal-oxide-semiconductor (CMOS) according to a first embodiment of the present invention, and FIG. 2B is a schematic cross-sectional view according to the II-II' section of FIG. 2A .

Please refer to FIG. 2A and FIG. 2B , the complementary metal oxide semiconductor 20 of the present invention includes an N-type low-temperature polysilicon thin film transistor 210 and a P-type low-temperature polysilicon thin-film transistor 220 located on a substrate 200, and covers the low-temperature polysilicon thin-film transistors 210 and 220. There is an inter-layer dielectric layer (inter-layer dielectrics, ILD for short) 230 . In this embodiment, the N-type low-temperature polysilicon thin film transistor 210 includes a gate 202 and an island-shaped polysilicon (poly-island) layer 204 between the gate 202 and the substrate 200, wherein the island-shaped polysilicon layer 204 has a The channel region directly below the gate 202, the N-type doped region 206a and the drain doped region 206b on both sides of the channel region below the gate 202. Moreover, the doped drain region 206 b is also connected to a source/drain contact metal 228 disposed on the interlayer dielectric layer 203 and in the interlayer dielectric layer 230 . Wherein, the direction in which the channel region, the drain doped region 206b and the N-type doped region 206a are arranged is the first direction.

Please refer to FIG. 2A and FIG. 2B again, the P-type low-temperature polysilicon film 220 of this embodiment includes a gate 212 and an island-shaped polysilicon layer 214 between the gate 212 and the substrate 200, wherein the island-shaped polysilicon layer 214 has The channel region directly below the gate 212 and the source doped region 216 a and the P-type doped region 216 b on both sides of the channel region below the gate 212 . Moreover, the source doped region 216 a is also connected to another source contact metal 228 . Wherein, the direction in which the channel region, the source doped region 216a and the P-type doped region 216b are arranged is also the first direction, and the P-type doped region 216b and the N-type doped region 206a are arranged along a second direction configuration, the second direction is perpendicular to the first direction.

Please refer to FIG. 2A and FIG. 2B again. The N-type doped region 206a of the N-type low-temperature polysilicon thin film transistor 210 and the P-type doped region 216b of the P-type low-temperature polysilicon thin film transistor 220 are exposed through the interlayer dielectric layer 230. The contact hole 232 of the N-type doped region 206a and the P-type doped region 216b is electrically connected to a wire 222, wherein the extending direction of the wire 222 is the second direction. Since the layout of the complementary metal oxide semiconductors 20 of the present invention is arranged side by side and staggered in pairs, its width can be greatly reduced. For example, in FIG. 2A , the overall width 242 is about 45 μm, which is significantly smaller than the known width 142 (see FIG. 1A ), saving about 20 percent of the width.

Please continue to refer to FIG. 2A and FIG. 2B. In this embodiment, there is a gate insulating film (gate insulating film) 224 between the island polysilicon layers 204, 214 and the gates 202, 212, and a gate insulating film 224 between the substrate 200 and the island polysilicon layers. There is also a buffer layer 226 between the layers 204, 214. There is also a lightly doped drain region between the channel region (directly below the gate 212) and the drain doped region 206b of the N-type low-temperature polysilicon thin film transistor 210, and between the channel region and the N-type doped region 206a. (lightly doped drain, LDD for short) 207.

Please note that this embodiment is only used for illustration, and is not intended to limit the scope of application of the present invention. All components composed of P-type thin film transistors and N-type thin film transistors can be designed using the features of the present invention, that is, the first The layout configurations of the type (N or P type) thin film transistors and the second type (N or P type) thin film transistors are parallel to each other and interlaced.

second embodiment

Any circuit structure composed of at least one P-type thin film transistor and at least one N-type thin film transistor can be laid out by using the present invention, please refer to FIG. 3 .

FIG. 3 is a schematic top view of a CMOS composite device according to a second embodiment of the present invention. Referring to FIG. 3 , the composite device 30 of the present invention includes an N-type low temperature polysilicon thin film transistor 310 and two P-type low temperature polysilicon thin film transistors 320 . Although there are only three thin film transistors in this embodiment, it is not limited to the application of the present invention, but only used as an example, so as long as the design is according to the characteristics of the present invention, no matter how many thin film transistors are available.

Please continue to refer to FIG. 3 , the N-type low-temperature polysilicon thin film transistor 310 of this embodiment includes a gate line 302 and an island-shaped polysilicon layer 304 located under the gate line 302 , which has a channel directly below the gate line 302 region and the doped regions 306 a , 306 b on both sides of the channel region below the gate line 302 . The P-type low-temperature polysilicon film 320 includes a gate line 312 and an island-shaped polysilicon layer 314 located under the gate line 312. Side doped region 316a, source/drain doped region 316b. Moreover, the source/drain doped region 316b is also connected to the source/drain contact metals 318 and 319 respectively disposed on the interlayer dielectric layer (see FIG. 4A ) and in the interlayer dielectric layer. Wherein, the N-type low-temperature polysilicon thin film transistors 310 and the P-type low-temperature polysilicon thin film transistors 320 are arranged alternately. Moreover, the doped regions 306a and 306b of the N-type low-temperature polysilicon thin film transistor 310 are electrically connected to the doped region 316a of the P-type low-temperature polysilicon thin film transistor 320 through the contact hole 332 and the wires 322a and 322b respectively, wherein the wires 322a and 322b are connected to the doped region 316a of the P-type low-temperature polysilicon thin film transistor 320. The extending directions of the gate lines 302 and 312 are parallel.

For more detailed description of this embodiment, please refer to the following sectional views, wherein FIG. 4A is a schematic sectional view according to the AA' section of FIG. 3, FIG. 4B is a schematic sectional view according to the BB' section of FIG. According to the schematic cross-sectional view of the CC' section in FIG. 3 .

Please refer to FIG. 4A first, a substrate 300 is covered with an interlayer dielectric layer 330, and the gate line 312 and the island polysilicon layer 314 are covered, and the contact hole 332 in the interlayer dielectric layer 330 The doped region 316 a is exposed, and the channel region 315 is directly below the gate line 312 . In addition, it can also be seen from the cross-sectional view that there is a gate insulating layer 324 between the island polysilicon layer 314 and the gate lines 302 and 312 , and a buffer layer 326 between the substrate 300 and the island polysilicon layer 314 .

Then, please refer to FIG. 4B , the contact hole 232 in the interlayer dielectric layer 230 exposes the doped regions 306 a , 306 b , wherein the channel region 305 is directly below the gate line 302 . In addition, there is a lightly doped drain region 307 between the channel region 305 and the doped regions 306a, 306b.

Finally, please refer to FIG. 4C , which is a schematic cross-sectional view of the CC' section in FIG. 3 , in which the wire 322a connects the doped regions 306a and 316b of different low-temperature polysilicon thin film transistors, and its extending direction is parallel to the CC' section. .

In a word, the feature of the present invention is that the layout of the first-type low-temperature polysilicon thin-film transistor and the second-type low-temperature polysilicon thin-film transistor are arranged side by side and staggered, so the width of the complementary metal-oxide-semiconductor or its combination elements can be greatly reduced, thereby improving resolution and solve the problem of insufficient space.

Claims (13)

1. a complementary metal oxide semiconductors (CMOS) is characterized in that, comprising:

One first type thin-film transistor comprises:

One first grid;

One first island polysilicon layer is positioned under this first grid, and wherein this first island polysilicon layer comprises:

One first channel region is positioned under this first grid;

The one source pole doped region is positioned at a side of this first grid; And

One first type doped region is positioned at the opposite side of this first grid, and wherein this source doping region, this first channel region and this first doped region are along a first direction alignment arrangements;

One second type thin-film transistor comprises:

One second grid;

One second island polysilicon layer is positioned under this second grid, and wherein this second island polysilicon layer comprises:

One second channel region is positioned under this second grid;

One second type doped region is positioned at a side of this second grid; And

One drain doping region, be positioned at the opposite side of this second grid, wherein this second type doped region, this second channel region and this drain doping region are along this first direction alignment arrangements, and this second type doped region and this first type doped region are along a second direction alignment arrangements, and this second direction is vertical with this first direction;

One interlayer dielectric layer is covered on this first type thin-film transistor and this second type thin-film transistor, and this interlayer dielectric layer has a plurality of contact window opening, to expose this first doped region and this second doped region;

One lead is positioned on this interlayer dielectric layer, and connects this first doped region and this second doped region by above-mentioned these contact window opening, and the bearing of trend of this lead is this second direction;

The one source pole contacting metal is configured on this interlayer dielectric layer and in this interlayer dielectric layer, and this source electrode contacting metal and this source doping region electrically connect; And

One drain electrode contacting metal is configured on this interlayer dielectric layer and in this interlayer dielectric layer, and should drain electrode contacting metal and the electric connection of this drain doping region.

2. complementary metal oxide semiconductors (CMOS) as claimed in claim 1 is characterized in that, this first type thin-film transistor comprises low-temperature polysilicon film transistor.

3. complementary metal oxide semiconductors (CMOS) as claimed in claim 1 is characterized in that, this second type thin-film transistor comprises low-temperature polysilicon film transistor.

4. complementary metal oxide semiconductors (CMOS) as claimed in claim 1 is characterized in that, this first type thin-film transistor comprises N type thin-film transistor.

5. complementary metal oxide semiconductors (CMOS) as claimed in claim 4, it is characterized in that, this first island polysilicon layer more comprises a shallow doped-drain zone, between this first channel region and this source doping region and between this first channel region and this first type doped region.

6. complementary metal oxide semiconductors (CMOS) as claimed in claim 4 is characterized in that, this second type thin-film transistor comprises P type thin-film transistor.

7. complementary metal oxide semiconductors (CMOS) as claimed in claim 1 is characterized in that, this first type thin-film transistor comprises P type thin-film transistor.

8. complementary metal oxide semiconductors (CMOS) as claimed in claim 7 is characterized in that, this second type thin-film transistor comprises N type thin-film transistor.

9. complementary metal oxide semiconductors (CMOS) as claimed in claim 8, it is characterized in that, this second island polysilicon layer more comprises a shallow doped-drain zone, between this second channel region and this drain doping region and between this second channel region and this second type doped region.

10. the composition element of a complementary metal oxide semiconductors (CMOS) is characterized in that, this element comprises:

At least one first type low-temperature polysilicon film transistor comprises:

One first grid polar curve;

One first island polysilicon layer is positioned under this first grid polar curve, and wherein this first island polysilicon layer comprises:

One first channel region is positioned under this first grid polar curve;

One first doped region is positioned at a side of this first grid polar curve; And

One second doped region is positioned at the opposite side of this first grid polar curve;

A plurality of second type low-temperature polysilicon film transistors, with the configuration that intermeshes of this at least one first type low-temperature polysilicon film transistor, wherein respectively this second type low-temperature polysilicon film transistor comprises:

One second grid line;

One second island polysilicon layer is positioned under this second grid line, and wherein this second island polysilicon layer comprises:

One second channel region is positioned under this second grid line;

One the 3rd doped region is positioned at a side of this second grid line; And

The source doped region is positioned at the opposite side of this second grid line;

One interlayer dielectric layer is covered on this at least one first type thin-film transistor and above-mentioned these second type thin-film transistors, and this interlayer dielectric layer has a plurality of contact window opening, to expose this first doped region, this second doped region and the 3rd doped region;

Many leads, be positioned on this interlayer dielectric layer, and connecting this first doped region respectively with the 3rd doped region and be connected this second doped region and the 3rd doped region by above-mentioned these contact window opening, wherein above-mentioned these leads are parallel with the bearing of trend of this first grid polar curve and this second grid line; And

At least one source/drain contacting metal is configured on this interlayer dielectric layer and in this interlayer dielectric layer, and this source/drain contacting metal and this source electrode electrically connect.

11. the composition element of complementary metal oxide semiconductors (CMOS) as claimed in claim 10 is characterized in that, above-mentioned these second type thin-film transistors comprise P type thin-film transistor.

12. the composition element of complementary metal oxide semiconductors (CMOS) as claimed in claim 10 is characterized in that, this at least one first type thin-film transistor comprises N type thin-film transistor.

13. the composition element of complementary metal oxide semiconductors (CMOS) as claimed in claim 12, it is characterized in that, this first island polysilicon layer more comprises a shallow doped-drain zone, between this first channel region and this first doped region and between this first channel region and this second doped region.

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