CN1299355C - Mfg. tech. of packaged interface substrate wafer having wholly metallized through hole - Google Patents

Abstract

The present invention is a technology that provides packaging intermediates that serve as interface substrates placed between different types of circuits with dimensions approaching the sub-100 micron range. The invention includes a dielectric wafer structure with first and second region surfaces of the wafer separated by a distance on the order of the electrical via design length, and an array of spaced vias through the wafer where each via is filled with metal.

Description

Manufacturing Technology of Package Interface Substrate Wafer with Fully Metallized Vias

technical field

The present invention relates to the fabrication of insulating wafer structural components, each of which has an array of sub-100 micron sized electrical pathways as an interface substrate between different types of wiring in electronic devices.

Background technique

The fabrication of insulating wafers that can serve as carriers or substrates for electronic circuits with thousands of metal-filled micron-sized vias or vias with acceptable electrical impedance and electromagnetic properties is a subject of considerable importance in the electronics industry. In the case of current electronic packaging, the density of interconnections or wiring in most carriers and substrates is generally lower than that achievable with integrated semiconductor chip technology. The performance and design advantages of combining different types of circuits and components on a dense carrier or substrate have been carefully studied and some progress has been made with respect to interface issues such as space mismatch and difficult access of signal and power lines from peripheral support components. results. This technology is sometimes referred to in the art as system-on-package (SOP) technology.

An example of work in this field is presented in U.S. Patent Application Serial No. 09/838,725, filed 4/1/01, in which the contemplated structure is an interconnected wafer supported multi-chip device attached to one side , while the other side of the die connects to other modules or boards made with different interconnect technologies.

A discussion of the current state of research in this area appears in a technical article titled "Packaging Provides Viable Alternatives to SOC" by J. Baliga in the July 2000 issue of "Semiconductor International", page 7.

Although much of the reported work has been done on silicon known as an insulating wafer material, the parameters involved in the present invention can be easily extended to other insulating materials; pp. 98-102 of IEEE Transactions on 2001 The paper titled "High Density Electrical Feedthroughs Fabricated by Deep Reactive Ion Etching of PYREX Glass" by Li et al. serves as an example of work performed on glass materials.

However, in the current state of the art, due to size shrinkage into the sub-100 micron range, many problems are encountered, for example, obtaining precise dimensions of via openings and uniform filling of metal while maintaining sufficient structural precision, enabling use including grinding And the ability to chemically correct chemical mechanical polishing (CMP) type of processing.

Contents of the invention

The present invention is a technology that provides packaging intermediates that serve as interface substrates placed between different types of circuits with dimensions approaching the sub-100 micron range. The present invention includes a dielectric wafer structure in which the first and second region surfaces of the wafer are separated by a distance approximately the design length of the electrical vias, and an array of spaced vias are arranged through the wafer, each The metal-filled vias surround the adhesion layer to facilitate electroless metal deposition on the exposed insulating material in the vias, with the termination of each via flush with the surface of the area.

The wafer structure is obtained by a technique wherein an array of blind via openings approximately 5-50 microns in diameter are formed through the first surface of the dielectric wafer to a depth of approximately 50-250 microns, close to the designed length of the vias. The sidewalls of the via openings are then conditioned to attach metal formed by a chemical reaction such as electroless plating. Blind via openings are completely filled with metal. CMP is used to remove all material on the surface of the first wafer, thereby planarizing the filled vias. Material is then removed from the surface of the second wafer, thereby thinning the wafer until the blind end of the metal-filled via for the designed via length is exposed.

According to one aspect of the present invention, there is provided a method of providing an interface support substrate with electrical pathways through the substrate, for use between entities of different circuits in an electrical device, comprising a combination of the steps of: providing a substrate made of a dielectric material A fabricated wafer structure having first and second region surfaces separated by a distance determined by the material of the wafer; An array of via openings in said material, the depth of the blind ends of said via openings being less than said distance, an electroless metal deposition enhanced adhesion coating is provided on at least the sidewalls of said blind via openings, with an electroless deposited metal filling the blind via opening, removing all material from the first region surface to planarize the via opening, and removing the material of the wafer through the second region surface until the The via holes are filled, and the surface of the second region is planarized.

According to another aspect of the present invention, there is provided an electrical device wherein first and second different types of circuits are interconnected into a functional electrical device unit, characterized in that it comprises: An interface of a flat surface dielectric material supports a substrate part, said first type of circuitry is placed on said first planar surface of said substrate part, and said second type of circuitry is placed on said substrate part of said substrate part. On the second planar surface, the substrate also has a plurality of electrical paths from the first planar surface through the dielectric material to the second planar surface, the plurality of electrical paths through the dielectric material connecting the Circuit locations in the circuits of the first and second types described above, and a plurality of electrical vias through the dielectric material are filled with electroless deposited metal.

According to another aspect of the present invention, there is provided a packaging method used in the manufacture of electrical equipment with different circuit entities, comprising the following steps: providing an interface support substrate made of the above-mentioned dielectric material on one surface The positioning of one circuit entity, and the positioning of the other circuit entity on the other surface of the support substrate component, provides for the support substrate component to pass through the dielectric material between locations on the surface with a plurality of electrical pathways arranged in an array, the plurality of electrical pathways through the dielectric material connecting together circuit locations in the circuit entity, and the electrical pathways through the dielectric material being used for Electroless deposition metal fill.

Description of drawings

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a perspective cutaway view of a portion of an intermediate manufactured product of the present invention.

Figure 2 is a sectional view of a part of the product in the manufacture of the structure of the present invention, illustrating the basic characteristics through steps 2A-2G; wherein:

Figure 2A shows the relative thickness of a blank wafer.

FIG. 2B shows a mask used for a via forming operation.

Figure 2C shows the formed blind via.

Figure 2D shows the blind via attachment enhancement operation.

Figure 2E shows the filling of blind vias.

Figure 2F shows the unmasking and filling via planarization operations.

FIG. 2G shows a removal operation that exposes the via.

Figure 2H shows the finished structure of the present invention.

Detailed ways

According to the present invention, the advantages encountered in electronic packages involving different types of circuits and technologies due to the shrinkage of package interconnect dimensions into the sub-100 micron range can be achieved by constructing an interface substrate for interconnecting different types of circuits and technologies. The main solution to many problems.

Figures 1 and 2 illustrate the technique of the present invention. Figure 1 is a partial perspective cutaway view of a structure involved in the present invention, and Figure 2 is a partial product cutaway view of the essential features in the manufacture of the structure, through step illustrations 2A-2G.

Referring to FIG. 1 , there is shown the structure of a wafer 1 of insulating material, an array 2 of electrical pathways or vias 3 (two shown in a row) approximately 150 microns apart in the diameter range of approximately 5 to approximately 50 microns, And extend from the first surface 4 to the second surface 5 . The surfaces 4 and 5 can be planarized using chemical mechanical processing (CMP) without damaging the vias 3 on the surfaces 4 and 5 during the process. The thickness of the wafer, denoted V, between the surfaces 4 and 5 is the designed length of the electrical path or via 3 . Via 3 is filled with metal that starts and ends flush with surfaces 4 and 5 . In a filled via, an attachment feature, shown as layer 7 , is applied to the exposed insulating material sidewalls of via 3 . The attachment member 7 can act as a catalyst in chemical deposition such as electroless plating. The dimension indicated by X is the diameter of the via hole 3 . The parameter VX is the aspect ratio of the via 3, which can be in the range of 1:1 to 10:1.

Referring to Figures 2A-2H in Figure 2, the structure of Figure 1 can be fabricated using a variety of materials and processes.

Features of the wafer 1 are shown in FIG. 2A . Like items are denoted by like reference numerals where appropriate. The blank wafer is indicated at 11 and is an insulating material such as a silicon semiconductor material having a relatively high resistivity. The blank wafer 11 has a total thickness W, beyond the dotted line defining the wafer thickness V to be achieved, material 12 available for subsequent thinning to precise dimensions for removal.

In FIG. 2B , the mask used for the etch operation is shown, wherein the array of blind holes 2 used to form the vias 3 is placed in the wafer 11 through the surface 4 . A masking layer 13 is applied to the surface 4 in a pattern such that the surface 4 is exposed at each opening 14 at the location of each via 3 . Etching operations can be accomplished by standard operations such as wet etching or reactive ion etching. The mask material 13 is selected as a resist in the etching process.

In FIG. 2C , the result of the etch operation is shown, blind holes 15 are formed in the insulating blank wafer 11 through the holes 14 in the mask 13 . The etching operation forms a blind hole of a depth defined by dimension V.

In FIG. 2D , the operational features of producing an attachment feature, indicated as layer 16 , on the exposed sidewalls and bottom surfaces of the blind hole 15 are shown. Adhesive layer 16 can act as a catalyst for blind holes 15 filled with metal.

In FIG. 2E , the filling of the hole 15 in the adhesion layer 16 is shown with a metal 17 , eg Ni, Co, Cu, Au or a combination thereof, by chemical deposition such as electroless plating. The deposited metal 17 may protrude slightly beyond the surface 14 into the opening 14 in the mask 13 . The adhesion layer 16 can be removed from the surface 4 of the substrate by a process such as CMP, so that the catalyzed deposition of the deposited metal 17 takes place only in the pores. This reduces the amount of metal 17 protruding beyond surface 4 .

In FIG. 2F, features of a planarization operation to unmask and fill vias are shown. The removed portion is the cross-hatched portion 18 shown, consisting of the masking material 13 reaching the surface 4 and including any metal 17 above the surface 4 in the opening 14 . Removal by chemical mechanical processing, including grinding during chemical operations, results in the metal 17 in the via 3 being planarized and flush with the surface 4 .

In FIG. 2G , the removal operation of material 12 from a blank wafer 11 shown as a shaded portion of element 19 is shown, thinning the insulating material and exposing the via 3 so as to locate the surface 5 at dimension V, via 3 is flush with the surface 5 .

Figure 2H shows the completed interface substrate structure. The principles of the present invention will be further illustrated in two examples of the filling process of metal 17, as shown in Figures 2D to 2H.

Example A

Referring to Figure 2D, layer 16 serves to function as an adhesion layer to assist in the electroless plating operation that occurs in Figure 2E.

The wafer is placed in the sputtering chamber. A 400 angstrom TaN/400 angstrom Ta/800 angstrom Cu layer is deposited over the entire wafer surface 4 , the mask 13 and the sidewalls and bottom surfaces of the blind holes 15 . TaN/Ta serves as the adhesion layer 16 . For metallization at locations in cavities such as blind vias 15 has the unique advantage of depositing a thin layer (not shown) of copper approximately 0.6 to 0.8 microns deep and subsequently removing the surface by simple mechanical polishing or CMP. copper on the but remain on the sidewalls and bottom of the blind via 15.

The wafer is then dipped into a dilute acid solution to remove any oxides on the thin copper layer. Then, the wafer is put into dilute palladium sulfate solution, and the reaction shown in formula 1 occurs on the surface and bottom of the blind hole 15 .

Formula 1: Pd(++)+Cu...Pd(o)+Cu(++)

As a result of this displacement reaction, the surfaces of the side walls and bottom of the blind hole 15 are covered with very small particles of the active catalyst Pd shown as layer 16 in FIGS. 2D-2H .

With the activation reaction of the catalyst, electroless plating occurs. The wafer is placed in a fast electroless Ni plating solution whereby nickel metal is uniformly deposited along the cavity sidewalls and bottom surfaces of the blind holes 15 . The plating solution is made of Ni salt, stabilizing or complexing agent, pH buffer, reducing agent and surfactant. Surfactants ensure low surface tension in the flow, which enables rapid removal of air bubbles and other reaction products. The resulting coating is uniform and free from porosity.

Example B

Referring to Figure 2D, layer 16 still serves the function of an adhesion layer, assisting the electroless plating operation that occurs in Figure 2E.

The wafer is silicon and immersed in a multifunctional cationic surfactant. As Si and Si/SiO2 surfaces are covered with negative silanol groups (Si-OH(-)), due to immersion in cationic surfactants, due to electrostatic attraction, on all exposed Si surfaces, both surface and Through the interior of the hole wall, a positive charge is generated. Here, it is considered that a large number of cationic groups (+) appear on Si.

The wafer was immersed in the suspension of Pd/Sn microcolloids for 5-8 minutes. The particles of this colloid are negatively (−) charged, resulting in a strong attractive force and good adhesion strength, making the Pd particles adhere tightly to all Si surfaces. By polishing the surface of the wafer, the Pd colloids can be selectively removed from unwanted areas, leaving properly mechanically polished surfaces only in the Pd contact reaction zones on the sidewalls and bottom of the cavity.

The wafer is then immersed in a low deposition rate electroless plating solution for approximately 5 minutes to initiate the plating reaction, and then immersed in a higher deposition rate electroless plating solution.

What has been described above is the procedural and structural principles of providing a chip via interface and supporting different types of circuits between different types of circuits in an electrical device.

Claims (16)

1. method that the interface supporting substrate that has the electric pathway that passes substrate is provided is used between the entity of different circuit in the electric equipment combination that may further comprise the steps:

The chip architecture of being made by dielectric material is provided, has first and second region surface, described first and second region surface are separated by one by the definite distance of the material of described wafer;

The via openings array in the described material that surface, described first area enters described wafer is passed in formation, and the degree of depth of the cecum of described via openings is less than described distance,

On the sidewall of described at least blind hole opening, provide chemical metal deposit to strengthen adhering coating,

With the metal filled described blind hole opening of chemical deposition,

Remove all material from surface, described first area, thus the described via openings of complanation, and

Remove the described material of described wafer by described second area surface, up to exposing described filled vias, and the described second area of planarization surface.

2. according to the process of claim 1 wherein the design length of described distance greater than described electric pathway.

3. according to the method for claim 2, the described material of wherein said wafer is a silicon.

4. according to the method for claim 3, wherein form described chemical deposition metal by electroless.

5. according to the method for claim 4, wherein said metal is selected from Ni, Co, Cu, Au or their combination.

6. according to the method for claim 5, the coating that wherein said chemical metal deposit provides is a catalyst.

7. electric equipment, wherein the first and second dissimilar circuit interconnections enter in the function electrical appliance, it is characterized in that comprising:

The interface supporting substrate parts of the dielectric material that provides according to claim 1 with first and second substantially parallel flat surfaces,

The circuit of the described first kind is placed on described first flat surfaces of described substrate element,

The circuit of described second type is placed on described second flat surfaces of described substrate element,

Described substrate also have from described first flat surfaces by described dielectric material to a plurality of electric pathways of described second flat surfaces,

A plurality of electric pathways by described dielectric material are connected the circuit position in the circuit of described first and second types, and

A plurality of electric pathways by described dielectric material are used the metal filled of chemical deposition.

8. according to the electric equipment of claim 7, wherein said dielectric material is a silicon.

9. electric equipment according to Claim 8, wherein said electric pathway with adhere to enhancement layer around.

10. according to the electric equipment of claim 9, wherein saidly adhere to the product that enhancement layer is Pd and Cu.

11. according to the electric equipment of claim 9, the wherein said enhancement layer that adheres to is selected from Ta, TaN, Pd haptoreaction layer or their combination.

12. according to the electric equipment of claim 7, the metal of wherein said chemical deposition is the electroless plating metal.

13. according to the electric equipment of claim 12, wherein said chemical deposition metal is selected from Ni, Co, Cu, Au or their combination.

14. the method for packing in the manufacturing that is used in the electric equipment with different circuit entity may further comprise the steps:

The location of a lip-deep circuit entity of the interface supporting substrate parts that the dielectric material that being provided at provides according to claim 1 is made and in the location of another lip-deep another circuit entity of described supporting substrate parts,

Pass described dielectric material and between the position on described surface, have a plurality of electric pathways for described supporting substrate parts provide with array format,

The described a plurality of electric pathways that pass described dielectric material link together the circuit position in the described circuit entity, and

The described electric pathway that passes described dielectric material is metal filled with chemical deposition.

15. according to the method for packing of claim 14, metal described here is Ni.

16. according to the method for packing of claim 14, the chemical deposition step of wherein said metal comprises the use catalyst.