CN1298026C - Method for modifying formation procedure for fabricating cumulate texture of controlling grid of flash memory - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit manufacturing technology, and in particular relates to an improved technology for manufacturing a flash memory (FLASH) control gate stacking structure. In the manufacturing process of partially overlapped double-gate flash memory, the formation step of the control gate stack structure is as follows: after the floating gate is formed, a second tunnel gate oxidation is performed, followed by depositing a layer of polysilicon and tungsten silicide respectively, and then depositing an oxide film. There are a number of disadvantages to this process. The present invention proposes an improved process for forming a new control gate stack structure, that is, no oxide film is deposited after the deposition of polysilicon and tungsten silicide films; only one dry etching process is required, which reduces process complexity and Production cost; in order to improve the oxidation quality of the second tunnel gate, NO gas is used for high-temperature annealing, which improves the yield and has higher reliability.

Description

An improved method for forming a flash memory control gate stacked structure

technical field

The invention belongs to the technical field of integrated circuit manufacturing technology, and in particular relates to an improved method for manufacturing a flash memory (FLASH) control gate stacking structure forming process.

Background technique

Memory is not only used in various types of electronic digital computers, becoming one of the main components of computers, but also widely used in other electronic technology fields. Digital computers have long used magnetic cores as memory cells. With the development of computing technology, magnetic cores can no longer meet various requirements in terms of performance and production efficiency. The successful development and mass production of semiconductor memory has greatly promoted the development of computers. Because MOS memory has significant advantages in high density, large capacity, low power consumption, and low cost, it has always occupied a dominant position in semiconductor memory. With the rapid development of new technology and new technology, the speed of MOS memory is also continuously improved, especially in the research and development of non-volatile memory, MOS memory has also made great progress. Therefore, MOS memory has formed a new technical field in electronics with its development and maturity, and has become an important aspect of large-scale and ultra-large-scale integrated circuits.

Memory can be divided into two categories according to its function: random access memory (RAM) and non-volatile memory (NVM). RAM random access memory can be divided into dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory can be divided into magnetic and optical media memory, ferroelectric memory (FRAM), magnetic memory (MRAM) and semiconductor NVM non-volatile memory.

Semiconductor NVM non-volatile memory can be divided into read-only memory (ROM), programmable read-only memory (PROM), erasable read-only memory (EPROM), electrically rewritable read-only memory (EEPROM) and Flash memory (Flash), etc. Compared with RAM random access memory, the biggest advantage of semiconductor NVM non-volatile memory is that it can keep data for a long time without consuming power, that is, it has the characteristics of energy saving.

Today, semiconductor NVM non-volatile memory has been widely used in many electronic products, especially the wide application of flash memory. For example, MP3 Players, Digital Cameras, DVD ROM Drives, CD-RW/DVD Drives, CDROM Drives, USB Drives, PC BIOS, Network Interface Cards/Products, Cable Modems, Smart Cards, PDAs, Hard Drives, Video Games , Video mobile phones, mobile phones, ADSL, digital TV, that is, set-top boxes, etc.

As we all know, EPROM memory is developed on the basis of ROM read-only memory.

The single-tube unit of EPROM structure is shown in Figure 1. It has two overlapping polysilicon gates, and the lower gate is insulated from the outside world and is called a floating gate, which plays the role of storing charges. The upper gate is connected to the X decoder, called the control gate, which plays a role in gating and controlling the device unit, so a control MOS transistor is omitted to form a single-transistor unit. When both the control gate and the drain are at zero potential, there is no charge on the floating gate. When the control gate and the drain are both at positive potential, the channel region is turned on, hot electrons are injected into the floating gate by means of the potential difference between the floating gate and the channel, and the floating gate forms negative charges to realize the task of programming or writing. It can be seen that the electron injection in the floating gate is accomplished by "channel hot electron injection". The so-called channel hot electron injection is to apply a sufficiently high electric field between the drain and the source, so that the electrons are accelerated by the electric field to become hot electrons. When the energy exceeds the barrier height of the silicon dioxide and silicon interface, with the help of additional Positive voltage is directly injected from the channel into the floating gate. This process is commonly referred to as channel hot electron injection programming or writing.

According to the presence or absence of charge in the floating gate, the threshold voltage of the control gate changes to represent different stored data, thereby realizing two states of reading and writing. We want the charge injected into the floating gate to remain there long before it is erased. However, the leakage and Fowler-Nordheim (F-N) tunneling effect in the actual process will gradually reduce the electrons.

To erase the charge in the floating gate must use UV ultraviolet light method. Ultraviolet erasing is to make the electrons in the floating gate obtain energy from the photon, so that they enter the silicon dioxide beyond the silicon dioxide and silicon interface barrier, and then are swept to the silicon substrate by the electric field in the silicon dioxide. This process is often called wiping.

The biggest disadvantage of EPROM memory is that it cannot be erased by electrical methods. It can only be erased by UV ultraviolet light all at once, but it cannot be erased word by word. Moreover, when erasing by UV ultraviolet light, EPROM cannot be powered on. In addition, two different voltages are required (Vdd and Vpp), and it takes a long time (about 10-20 minutes) to erase with UV light. Channel hot electron injection programming requires high current and high voltage, and therefore consumes a lot of power. Since UV light is required for erasing, a transparent quartz window must be used in the EPROM packaging process, which greatly increases the packaging cost.

In order to overcome the above shortcomings, people have developed EEPROM memory, which can use electrical methods to erase the stored content word by word, then rewrite it word by word, and then reprogram it to write. The EEPROM storage unit uses a double-gate MOS transistor for storage, and also requires an ordinary MOS transistor as a selector, as shown in Figure 2. EEPROM has the following characteristics: It can be programmed, written and erased through FN tunnel electronics; it can be rewritten and erased word by word; Tunnel, does not require a large programming current; fully compatible with other memories such as SRAM and DRAM. The biggest disadvantage of EEPROM is that two MOS transistors are used as storage units, and the area is large, so the integration level is low.

The purpose of designing Flash flash memory is to solve the problem of EEPROM scaling down by balancing memory cells and functions.

Flash flash memory is divided into the following types from the process technology: EPROM-based double-gate MOS single-transistor structure storage unit is EPROM-type flash memory, EEPROM-based double-gate and conventional MOS two-transistor structure storage unit is EEPROM-type flash memory, some Overlapped double-gate MOS single-transistor structure storage unit, that is, SPLIT-GATE flash memory, etc. Flash memory is functionally divided into two major products, NOR flash memory and NAND flash memory. NOR flash memory is mainly used to store instruction codes and NAND flash memory is mainly used to store data.

Flash flash memory has the following characteristics: it can realize all, block, slice and page number erasing functions; it has two working modes of single power supply voltage (Vdd) and dual voltage (Vdd and Vpp).

EPROM type flash memory storage unit as shown in Figure 3. It is characterized by the use of channel hot electron programming; single power supply voltage or dual voltage (Vdd and Vpp) about 12V working mode; can be used as a programmer and realize the internal programming function of the system; can realize source FN tunnel erasing or channel FN tunnel Erasing function; Compared with traditional EPROM, the erasing speed is fast, it can be packaged in plastic, and the cost is low. But it has the following disadvantages: over-erasing problem; large programming current (200-300 microamperes per unit); it is difficult to realize low-voltage and low-power applications; circuit design is complicated; strict process control is required; Hole traps or read disturb problems due to charge gain caused by FN tunnel-related traps during read.

The characteristics of EEPROM flash memory are: the same as EEPROM unit; the entire memory array is erased very quickly; there is no over-erasing problem; no byte selection is required; page number-, slice-, or block-selection functions can be performed; the design is simple However, it has a very large unit area and chip size; in addition, compared with traditional EEPROM, only the entire memory array can be erased and cannot be erased word by word.

The SPLIT-GATE flash memory storage unit is shown in Figure 4. FIG. 5 is a schematic diagram of two adjacent memory cells of a SPLIT-GATE flash memory formed by a non-self-aligned process technology. A new type of serial SUPERFLASH flash memory can be processed to integrate higher-density storage units in a smaller size and reduce the packaging volume.

It has the following characteristics: hot electrons are injected into the floating gate near the source side channel for programming; the hot electrons on the top corner of the floating gate are injected into the control gate through the FN tunnel to realize the erasing function, so the erasing speed is fast; because the control gate Partially overlaps with floating gate, so there is no over-erase problem; low programming current (0.1-5 microamps per cell); no negative charge pump required; suitable for low voltage and low power operation; suitable for very small "segments" and EEPROM application; but compared with serial EEPROM, this new type of serial flash memory has higher density, faster speed, and smaller size; it has higher reliability, as shown in Figure 6 for traditional flash memory and Figure 7 for SPLIT- GATE flash memory erase process is shown.

At present, in the integrated manufacturing process of the SPLIT-GATE flash memory front-end process, the second gate oxidation is performed after the floating gate is formed, and then a layer of 150-200 nanometer polysilicon film and a layer of tungsten silicide are deposited respectively, and then a layer of 200 nanometers is deposited. -300nm oxide film. Afterwards, the photolithography process is carried out: first apply a layer of organic ARC anti-reflection layer of about tens of nanometers, then apply photoresist, and then perform exposure and development. Then perform dry etching. The currently popular dry etching steps are as follows: dry-etch the organic ARC anti-reflective layer first, and then etch the 200-300nm oxide film. The process flow is shown in Figure 8. Then perform dry and wet stripping to remove the photoresist; use the 200-300nm oxide film as a mask to perform dry etching of tungsten silicide and polysilicon film, the process flow is shown in FIG. 9 . After that, sidewall oxide film dielectric deposition and etch back are performed. Then proceed to the normal process flow until all process steps are completed. This traditional process has many disadvantages, for example, a layer of 200-300nm oxide film is deposited after the deposition of polysilicon film and tungsten silicide film; two different dry etching processes are required, which increases process complexity and production Cost, low throughput, control gate build-up structure morphology is difficult to control, thus affecting yield and reliability. In addition, after the floating gate is formed, the tunnel gate oxide three-layer structure: thermally grown silicon dioxide/HTO/thermally grown silicon dioxide also has some shortcomings, which will adversely affect device reliability such as the number of erasing and writing cycles and data retention life .

Therefore, aiming at the above-mentioned shortcomings, the present invention proposes a new method for improving the process of manufacturing the flash memory control gate stacked structure. After the deposition of the polysilicon film and the tungsten silicide film, there is no need to deposit a layer of 200-300 nanometer oxide film; only one step of dry etching is required, and the process flow is shown in Figures 10 and 11. At the same time, after the floating gate is formed, the tunnel gate is oxidized. After the three-layer structure is completed, NO gas is used for high-temperature annealing to improve the quality of the tunnel gate oxide layer, thereby improving device reliability such as the number of erasing and writing cycles and data retention life.

Contents of the invention

The object of the present invention is to provide an improved process for manufacturing flash memory (Flash) control gate stacking structure which can reduce process complexity and production cost.

The improved process for preparing the control gate stack structure of the flash memory proposed by the present invention is to adopt the following process after the formation of the floating gate and before the formation of the control gate (polysilicon 2) in the integrated manufacturing process of the front-end process of the flash memory:

After the floating gate is formed, the second gate oxidation is performed to complete the deposition of the control gate stack structure. The steps are as follows:

(1) Perform necessary second tunnel gate oxidation pre-cleaning;

(2) Carry out the second tunnel gate oxidation to form a SiO ₂ /HTO/SiO ₂ three-layer structure;

(3) Deposit polysilicon and its doping, the thickness of which can be 150-200 nanometers;

(4) deposit tungsten silicide film, its thickness can be 100-200 nanometers;

(5) Carry out conventional photolithography process;

(6) Carry out dry etching, its step is as follows:

① One-step dry etching:

(A) etching the organic ARC anti-reflection layer;

(B) etching tungsten silicide and polysilicon film;

(C) Stripping the photoresist.

② Wet stripping to remove photoresist.

The above process does not need to deposit a layer of 200-300 nanometer oxide film on the tungsten silicide. The above-mentioned dry etching only needs to be carried out in one step of dry etching, the organic anti-reflection layer is firstly etched, and then the tungsten silicide and polysilicon film are etched.

The present invention proposes an improved method for fabricating a flash memory (Flash) control gate stack-up structure. It has the following advantages: the complexity of the process is reduced, the production cost is reduced, the process flow and production time are shortened, that is, the production volume is increased; the process stability is very good; the morphology of the stacked structure of the control gate is better, thereby improving the Yield and reliability.

Description of drawings

FIG. 1 is a schematic diagram of an EPROM floating gate memory cell.

Figure 2 is a schematic diagram of an EEPROM storage unit.

Fig. 3 is a schematic diagram of an EPROM flash memory storage unit.

Figure 4 is a schematic diagram of a SPLIT-GATE flash memory storage unit.

FIG. 5 is a schematic diagram of two adjacent memory cells of a SPLIT-GATE flash memory formed by a non-self-aligned process technology.

Fig. 6 is a schematic diagram of a conventional flash memory erasing process.

Figure 7 Schematic diagram of SPLIT-GATE flash memory erasing process.

FIG. 8 is a schematic diagram of the polysilicon 2 (control gate) photolithography process: dry etching the anti-reflection layer and the silicon oxide layer, and before stripping the photoresist in the conventional process flow.

FIG. 9 is a schematic diagram after dry etching of tungsten silicide and polysilicon film in a conventional process flow.

FIG. 10 is a schematic diagram of polysilicon 2 (control gate) photolithography and development after the process flow is improved.

Fig. 11 is a schematic diagram of the improved process flow, after dry etching of tungsten silicide and polysilicon film and before photoresist stripping.

Numbers in the figure: 1 is the control gate, 2 is the floating gate, 3 is the electron, 4 is the hole, 5 is the N+ source region, 6 is the P-type substrate, 7 is the selection gate, 8 is (for FN tunnel thin) oxidation layer, 9 is the channel erasing process, 10 is the source erasing process, 11 is the word line, 12 is the conventional Flash structure, 13 is the electric field distribution, 14 is tungsten silicide, 15 is the anti-radiation layer, and 16 is the photoresist.

Detailed ways

The specific implementation steps of the control gate stacked structure of the present invention are as follows.

After the floating gate is formed, the steps are as follows:

(1) The first step is to perform tunnel gate oxidation pre-cleaning.

(2) The second step is the formation of a three-layer structure of tunnel gate oxidation:

(A) thermally grown silica/N ₂ O-LPCVD HTO/thermally grown silica;

(B) above-mentioned temperature is respectively 800-950 ℃, 750-800 ℃ and 800-950 ℃;

(C) the thicknesses of the above three layers are respectively 7.5-3 nanometers/200-70 nanometers/7.5-3 nanometers;

(D) After the three-layer structure is formed, NO gas is used for annealing at a temperature of 850-950°C;

(E) The above-mentioned NO gas annealing time is 2-30 minutes.

(3) In the third step, doped polysilicon and tungsten silicide thin films are deposited by LPCVD, the thicknesses of which are 150-250nm and 100-200nm respectively.

(4) The fourth step is to carry out the photolithography process (as shown in Figure 10):

(A) coating one deck of 30-100 nanometer organic ARC anti-reflection layer;

(B) coating photoresist;

(C) Exposure and development.

(5) The fifth step of dry etching (as shown in Figure 11):

(A) etching the organic ARC anti-reflection layer;

(B) etching tungsten silicide and polysilicon film;

(C) Stripping the photoresist.

Adopt the improved method that the present invention is used to manufacture flash memory (Flash) control gate stacking structure, can satisfy large-scale and ultra-large-scale flash memory manufacturing technology performance requirement fully, in some electrical characteristics, such as number of erasing and writing cycles and Device reliability, such as data retention life, has exceeded the performance of flash memories manufactured by traditional processes.

In this application document, HTO refers to high-temperature thermal layer, MOS refers to metal oxide semiconductor, LPCVD refers to low-pressure chemical vapor deposition, and SPL1T-6ATE refers to double fission, all of which are conventional terms in this technical field.

Claims (6)

1, a kind ofly be used to make flash memory control gate packed structures and improve technology, it is characterized in that in the integrated manufacture process of the preceding road of flash memory technology after floating boom formed, control gate adopted following operation before forming:

(1) carries out the tunnel gate oxidation prerinse second time;

(2) carry out the tunnel gate oxidation second time, form SiO ₂/ HTO/SiO ₂Three-decker;

(3) deposit polysilicon and doping thereof;

(4) deposit tungsten silicide thin film;

(5) carry out conventional photo-mask process, its step is as follows; (a) coating organic antireflection layer; (b) coating photoresist; (c) exposure and development;

(6) dry etching, its step is as follows:

(a) carry out a step dry etching, its step is as follows: at first carry out the etching of organic antireflection layer, then carry out tungsten silicide and polysilicon film etching;

(b) wet method is peeled off the removal photoresist.

2, improvement technology according to claim 1 is characterized in that: the SiO that the described second time, the tunnel gate oxidation formed ₂/ HTO/SiO ₂Three-decker thickness is respectively 3-7.5 nanometer/70-200 nanometer/3-7.5 nanometer.

3, improvement technology according to claim 1 is characterized in that: the described SiO that the second time, gate oxidation formed ₂/ HTO/SiO ₂Three-decker, temperature are respectively 800-950 ℃, 750-800 ℃ and 800-950 ℃.

4, improvement technology according to claim 3, it is characterized in that: the described second time, gate oxidation three-decker in tunnel formed after silicon dioxide/HTO/ silicon dioxide is finished, adopt NO gas to carry out high annealing, temperature is 850-950 ℃, and the time is 2-30 minute.

5, improvement technology according to claim 1 is characterized in that: the thickness of described deposit polysilicon is the 150-200 nanometer.

6, improvement technology according to claim 1 is characterized in that: the thickness of described deposit tungsten silicide thin film is the 100-200 nanometer.

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