CN1296929C - Absolute time bit data generator and method for optical disc - Google Patents

Abstract

An Absolute Time (ATIP) bit data generator for an optical disc is not affected by a non-uniform duty cycle. The bit data generator includes: the analog processor receives a signal generated by an optical head and generates an ATIP FM signal after processing the signal; a high frequency phase-locked loop, which takes ATIP FM signal as reference to generate high frequency clock pulse; a first decoder for receiving ATIP FM signal and high frequency clock pulse to generate biphase coding data; a synchronous mark detector for receiving biphase coded data and high-frequency clock pulse and generating synchronous indication signal; and a second decoder, taking the synchronous indication signal as reference, taking half period of a plurality of ATIP FM signals as counting period, calculating the pulse number of high frequency clock pulse of each counting period, when the pulse number is smaller than the first threshold value or larger than the second threshold value, outputting ATIP bit data of the first level, and when the pulse number is between the first threshold value and the second threshold value, outputting ATIP bit data of the second level.

Description

Absolute time bit data generator and method for optical disc

technical field

The invention relates to an Absolute Time In Pregroove (absolute time in pregroove, hereinafter referred to as ATIP) bit data generator.

Background technique

Figure 1 is a structural diagram of a 42-bit ATIP information block. As shown in the figure, the 42-bit ATIP information block includes 4-bit synchronization mark, 8-bit minute information, 8-bit second information, 8-bit data segment information, and 14-bit cyclic redundancy check (Cyclic Redundancy) Check, CRC) information. The ATIP information provides the correct writing location for writable optical disc systems.

FIG. 2 is a structural diagram of frequency modulation to biphase data conversion for writable CDATIP data in US Patent No. 5,506,824. As shown in Figure 2, after its ATIP bit information generator 12 utilizes biphase converter (Biphase converter) 32 to convert ATIP frequency modulation (FM) data into biphase data, then utilizes digital PLL 38 to generate 2 multiplied clock pulses , and finally use the ATIP decoder 26 to use the double-frequency clock pulse as the reference clock pulse, and generate ATIP bit information according to the bi-phase data. The bi-phase converter 32 counts how many high-frequency clock pulses (generated by the high-frequency PLL 28) pass through in each half-cycle FM signal, and determines the bi-phase data to be H or L according to the pulse number. That is, when the number of pulses is lower than a threshold, the bi-phase data is H, and when the number of pulses is higher than the threshold, the bi-phase data is L. The ATIP decoder 26 decodes the ATIP information according to the bi-phase data.

Under normal circumstances, the above method can produce correct biphase data. But if the duty cycle (duty cycle) of ATIP FM data is uneven, then biphase converter 32 promptly can be affected when counting the pulse number of the high-frequency clock pulse corresponding to every half cycle, and can't produce correct biphase data . Secondly, when the reading speed of the optical disc is getting faster and faster, the output frequency of the high-frequency PLL 28 is relatively increased, which causes design difficulties, increases costs, or reduces resolution.

Figure 3 shows the relationship between ATIP FM data and bi-phase data, where (A) is ATIP FM data, (B) is bi-phase data, and (C) is bi-phase clock signal. When the ATIP FM data is high frequency, the biphasic data is H, and when the ATIP FM data is low frequency, the biphasic data is L.

Contents of the invention

In view of the above problems, the object of the present invention is to propose a generator of absolute time (ATIP) bit data that is not affected by the duty cycle of ATIP FM data.

In order to achieve the above object, the optical disc absolute time (ATIP) bit data generator provided by the present invention comprises: an analog processor, receives the signal that an optical head produces, and produces ATIP FM signal after being processed; The FM signal is used as a reference to generate high-frequency clock pulses; a first decoder receives ATIP FM signals and high-frequency clock pulses, and generates bi-phase encoded data; a sync mark detector receives bi-phase encoded data and high-frequency clock pulses , and generate a synchronous indication signal; and a second decoder, with the synchronous indication signal as a reference, the half cycle of a plurality of ATIP FM signals as a counting period, calculates the pulse number of the high-frequency clock pulse corresponding to each counting period, When the number of pulses is less than the first threshold or greater than the second threshold, the ATIP bit data of the first level is output, and when the number of pulses is between the first threshold and the second threshold, the second level is output ATIP bit data.

Because the absolute time (ATIP) bit data generator of the present invention uses the half cycle of a plurality of ATIP FM signals as the counting cycle, the count value will not be affected by the uneven duty cycle, so the correct ATIP signal can be generated. At the same time, because the counting period is longer, the frequency of the required high-frequency clock pulse can be reduced.

In addition, the absolute time (ATIP) bit data generator of the present invention integrates a bi-phase demodulator (Bi-phase demodulator) and a frequency demodulator (FM demodulator), which can simplify the complexity of circuit design and reduce the delay time of data generation (delay time).

Description of drawings

Fig. 1 is a 42-bit ATIP information block structure diagram;

Fig. 2 shows the structural diagram of conventional writable CD ATIP data frequency modulation to bi-phase data conversion;

Figure 3 shows the relationship between ATIP FM data and bi-phase data, where (A) is ATIP FM data, (B) is bi-phase data, and (C) is a bi-phase clock signal;

Fig. 4 shows the structural diagram of the bit data generator of the present invention;

Fig. 5 shows the structural diagram of the first decoder of the present invention;

Fig. 6 shows the structural diagram of the second decoder of the present invention;

Figure 7 shows four examples where the ATIP FM signal counts every 14 half cycles;

Figure 8 shows a timing diagram of some signals;

Fig. 9 shows the flowchart of the bit data generator of the present invention;

In the accompanying drawings, 40 represents a bit data generator, 41 represents an optical disc, 42 represents an optical head, 43 represents an analog processor, 44 represents a first decoder, 441 and 461 represent a first pulse counter and a second pulse counter, 442 , 463, 464 represent comparators, 45 represents a sync mark detector, 46 represents a second decoder, 465 represents an AND gate, 47 represents a microprocessor, and 48 represents a high-frequency phase-locked loop (PLL).

Detailed ways

The absolute time (ATIP) bit data generator of the present invention will be described in detail below with reference to the accompanying drawings.

In the optical disc system, each ATIP bit corresponds to two bits of biphase data, and each bit of biphase data corresponds to 7 half-cycles of ATIP FM data. Therefore, each ATIP bit corresponds to 14 half cycles of ATIP FM data. When the duty cycle of ATIP FM data is asymmetrical, if only the ATIP FM data of each half cycle is counted, the cycle count value may be wrong, resulting in wrong bi-phase data. In order to solve this problem, the present invention takes the ATIP FM data of 7 half-periods or the ATIP FM data of 14 half-periods as the counting cycle, counts the pulse number of the high-frequency clock pulse of each counting cycle, then can avoid duty cycle asymmetry Impact. In addition, since the counting period is extended by 7 times or 14 times, the resolution of the present invention is relatively improved, or the frequency of the high-frequency clock pulse can be reduced.

FIG. 4 shows a structural diagram of the bit data generator of the present invention. As shown in the figure, the bit data generator 40 of the present invention includes an optical head 42 receiving the information of the optical disc 41, an analog processor 43 receiving the signal of the optical head 42, a first decoder receiving the ATIP FM signal and generating bi-phase data 44. A synchronous mark detector 45 that receives biphase data and generates a synchronous indication signal, receives a synchronous indication signal and an ATIP FM signal and generates a second decoder 46 of ATIP data, and generates a high-frequency phase-locked loop (PLL) 48 of a high-frequency clock pulse , and a microprocessor 47 that receives ATIP data and generates control signals.

The analog processor 43 processes and amplifies the signal generated by the optical head 42, and generates an ATIP FM signal. For a 32x CD player, the ATIP FM signal has a high frequency of 705.6kHz and a low frequency of 641.6kHz. The analog processor 43 has a general conventional structure, and no repeated description is given. The high-frequency phase-locked loop (PLL) 48 generates a high-frequency clock pulse HFC (High frequency clock) with the ATIP FM signal as a reference. The frequency of the high-frequency clock pulse HFC can be adjusted according to the frequency and resolution of the ATIP FM signal. For a 32-fold speed CD player, this embodiment selects 67.7376 MHz as the frequency of the high-frequency clock pulse HFC. In addition, the function of the microprocessor 47 is a well-known technology, and description is not repeated.

The first decoder 44 receives the ATIP FM signal of the analog processor 43, and uses the high-frequency clock pulse HFC output by the high-frequency phase-locked loop 48 as the working clock pulse to generate bi-phase data. FIG. 5 shows a block diagram of the first decoder 44 . As shown in the figure, the first decoder 44 includes a first pulse counter 441 and a comparator 442 . The first pulse counter 441 receives the ATIP FM signal and the high-frequency clock pulse HFC, and counts the number of pulses of the high-frequency clock pulse HFC corresponding to each counting cycle with every 7 half cycles of the ATIP FM signal as the counting period, and generates the first pulse counter 441. A pulse number is associated with the first trigger signal. The comparator 442 compares the first pulse number with a first pulse threshold F_SH according to the first trigger signal, and generates bi-phase data. When the first pulse number is greater than or equal to the first pulse threshold F_SH, the bi-phase data is 0, otherwise the bi-phase data is 1. The calculation method of the first pulse threshold F_SH is:

F_SH＝(HF+LF)/4*7 (1)

Among them, HF is the pulse number of high-frequency clock pulse HFC corresponding to each cycle of ATIP FM signal at high frequency, and LF is the pulse number of high-frequency clock pulse HFC corresponding to each cycle of ATIP FM signal at low frequency. For a 32x speed CD player, when the frequency of the high-frequency clock pulse HFC is 67.7376MHz, since the high-frequency and low-frequency frequencies are 705.6kHz and 641.6kHz respectively, the HF is 96 (67.7376MHz/705.6kHz), And LF is 105.6 (67.7376MHz/641.6kHz). Therefore, according to formula (1), the first pulse threshold F_SH is about 353.

Because the first decoder 44 takes every 7 half periods of the ATIP FM signal as the counting cycle, it can offset counting errors caused by uneven duty cycles. And with the same resolution, the frequency of the high-frequency clock pulse HFC of the present invention is reduced by about 1/7 times.

After receiving the bi-phase data, the sync mark detector 45 detects whether there is a special pattern of the sync mark of the ATIP data, such as 000101111 or 11101000, in the bi-phase data. If it is detected that the bi-phase data has a special pattern, the synchronization indication signal Syn_S is enabled (enable). Since the technology of detecting whether there is a special pattern in a sequence of digital signals is a well-known technology in the art, the description will not be repeated.

When the synchronization indication signal Syn_S is enabled, it means that the ATIP FM signal at this time is detected to contain correct ATIP data. Therefore, the second decoder 46 starts to operate when the synchronization indication signal Syn_S is enabled. The second decoder 46 takes the half cycle of 14 ATIP FM signals as the counting cycle, counts the pulse number of the high-frequency clock pulse in each counting cycle, and generates ATIP data according to the range of the pulse number.

FIG. 6 shows an embodiment of the second decoder 46 of the present invention. As shown in the figure, the second decoder 46 includes a second pulse counter 461 , a first comparator 463 , a second comparator 464 , and an AND gate 465 . The second pulse counter 461 utilizes the synchronous indication signal as a trigger signal, takes the half cycle of 14 ATIP FM signals as the counting cycle, starts counting the pulse number of the high-frequency clock pulse in each counting cycle, and generates the second pulse number and the second trigger Signal. The first comparator 463 compares the second pulse number with the lower limit count value (first threshold) L_TH according to the second trigger signal, and generates a first comparison value. At the same time, the second comparator 464 also compares the second pulse number with the upper count value (second threshold) H_TH according to the second trigger signal, and generates a second comparison value. The AND gate 465 receives the first comparison value and the second comparison value, and generates ATIP data.

The calculation methods of the lower limit count value L_TH and the upper limit count value H_TH are shown in formula (2) and formula (3):

L_TH＝(3*HF+LF)/8*14 (2)

H_TH＝(HF+3*LF)/8*14 (3)

Among them, HF is the pulse number of high-frequency clock pulse HFC corresponding to each cycle of ATIP FM signal at high frequency, and LF is the pulse number of high-frequency clock pulse HFC corresponding to each cycle of ATIP FM signal at low frequency. For a 32x speed CD player, if the frequency of the high-frequency clock pulse HFC is set to 67.7376MHz, the average value of HF is 91.835, and the average value of LF is 100.56. Therefore, according to formula (2) and formula (3), the lower limit count value L_TH and the upper limit count value H_TH are about 656 and 687 respectively.

Figure 7 shows four examples of counting cycles with half cycles of 14 ATIP FM signals. T in the figure is the low-frequency period of the ATIP FM signal, and t is the high-frequency period of the ATIP FM signal. As shown in the figure, the four examples are displayed as (A) 10, (B) 11, (C) 00, and (D) 01 with bi-phase data, and the ATIP data represented are 1, 0, 0 respectively ,1. If the second decoder 46 of the present invention counts the pulse numbers of the high-frequency clock pulses of these four examples respectively, then under the structure of 32 times of speed, if the frequency of the high-frequency clock pulse HFC is set to 67.7376MHz, the pulse The numbers are 672, 642, 704, and 672, respectively. Therefore, according to the above data, as long as the number of pulses is between the lower limit count value L_TH and the upper limit count value H_TH, the ATIP data is H, otherwise the ATIP data is L.

Figure 8 shows a timing diagram of some of the signals. Figure 8(A) is a high-frequency clock pulse. Figure 8(B) is the ATIP FM signal. Figure 8(C) shows the number of high-frequency clock pulses counted with each half cycle of the ATIP FM signal as the counting cycle. FIG. 8(D) shows the bi-phase signal generated by the conventional technology with the count value of FIG. 8(C). Figure 8(E) shows the number of high-frequency clock pulses counted by counting every 7 half cycles of the ATIP FM signal. FIG. 8(F) shows the bi-phase signal generated by the count value of FIG. 8(E) according to the present invention. Figure 8(G) shows the number of high-frequency clock pulses counted every 14 half cycles (7 cycles) of the ATIP FM signal as the counting cycle. FIG. 8(H) shows the ATIP bit data generated by the count value of FIG. 8(G) according to the present invention. The environment in this figure is a 32x speed CD player, and the frequency of the high-frequency clock used is set to 67.7376MHz. Therefore, it can be understood from the figure that when the prior art is used, errors in bi-phase data will be caused. However, the method and device of the present invention are not affected. In addition, it can also be understood from this figure that the resolution of the present invention is higher than that of the prior art at the same frequency of the high-frequency clock pulse.

The implementation steps of the absolute time (ATIP) bit data generating method of the present invention will be described below with reference to FIG. 9 . The implementation steps include:

Step S900: Generate an ATIP FM signal, receive a signal generated by an optical head, and process it to generate an ATIP FM signal.

Step S902: Generate a high-frequency clock pulse, and use the ATIP FM signal as a reference to generate a high-frequency clock pulse. It can be generated by a high-frequency phase-locked loop PLL.

Step S904: Generate a synchronization indication signal, and generate a synchronization indication signal according to the ATIP FM signal and the high-frequency clock pulse. When the synchronization indication signal is enabled, it indicates that the ATIP signal is detected.

Step S906: Generate an ATIP signal, and when the synchronization indication signal is enabled, use multiple half cycles of the ATIP FM signal as the counting cycle, and calculate the number of high-frequency clock pulses corresponding to each counting cycle. When the number of pulses is less than the first threshold or greater than the second threshold, the ATIP bit data of the first level is output; and when the number of pulses is between the first threshold and the second threshold, the ATIP of the second level is output bit data. Reference values of the first threshold and the second threshold are shown in equations (2) and (3).

Although the present invention has been described above with examples, the scope of the present invention is not limited thereto. As long as those skilled in the art do not depart from the gist of the present invention, various modifications and changes can be made.

Claims (14)

1. An absolute time (ATIP) bit data generator, comprising: An analog processor that receives a signal generated by an optical head and processes it to generate an absolute time frequency modulation (ATIP FM) signal; A high-frequency phase-locked loop, using the aforementioned ATIP FM signal as a reference, generates a high-frequency clock pulse; A first decoder, receiving the aforementioned ATIP FM signal and the aforementioned high-frequency clock pulse, and generating bi-phase encoded data; A sync mark detector, receiving the aforementioned bi-phase encoded data and the aforementioned high-frequency clock pulse, and generating a sync indication signal; and A second decoder, with the aforementioned synchronous indication signal as a reference, with a plurality of half cycles of the aforementioned ATIP FM signal as the first counting cycle, calculate the pulse number of the corresponding aforementioned high-frequency clock pulses of each first counting cycle, when When the number of pulses is less than the first threshold or greater than the second threshold, the ATIP bit data of the first level is output, and when the number of pulses is between the first threshold and the second threshold, the ATIP bit data of the second level is output ATIP bit data. 2. The absolute time (ATIP) bit data generator as claimed in claim 1, wherein said first decoder comprises: A first pulse counter, receiving the aforementioned ATIP FM signal and the aforementioned high-frequency clock pulse, and taking the half cycle of every 7 ATIP FM signals as the second counting cycle, counting the number of high-frequency clock pulses corresponding to each second counting cycle pulse number, generating a first pulse number and a first trigger signal; and A comparator, when the first trigger signal is enabled, compares the first pulse number with a pulse threshold, and generates the bi-phase encoded data. 3. The absolute time (ATIP) bit data generator as claimed in claim 1, wherein the ATIP bit data of the first level is L. 4. The absolute time (ATIP) bit data generator as claimed in claim 1, wherein the ATIP bit data of the second level is H. 5. The absolute time (ATIP) bit data generator as claimed in claim 1, wherein said second decoder comprises: A second pulse counter, counting the number of pulses of the aforementioned high-frequency clock pulses corresponding to each of the aforementioned first counting cycles, and generating a pulse count value; A first comparator, comparing the aforementioned pulse count value with the aforementioned first threshold, and generating a first comparison signal; A second comparator, comparing the aforementioned pulse count value with the aforementioned second threshold, and generating a second comparison signal; and An AND gate receives the aforementioned first comparison signal and the second comparison signal, and generates the aforementioned bit data. 6. The absolute time (ATIP) bit data generator as claimed in claim 5, wherein the aforementioned first counting period is a period of 7 ATIP FM signals. 7. The absolute time (ATIP) bit data generator as claimed in claim 5, wherein the aforementioned first threshold is: (3*HF+LF)/8*14, Wherein, HF is the pulse number of the above-mentioned high-frequency clock pulse corresponding to each cycle of the aforementioned ATIP FM signal at the high-frequency frequency, and LF is the pulse number of the aforementioned high-frequency clock pulse corresponding to each cycle of the aforementioned ATIP FM signal at the low-frequency frequency number. 8. The absolute time (ATIP) bit data generator as claimed in claim 5, wherein the aforementioned second threshold is: (HF+3*LF)/8*14, Wherein, HF is the pulse number of the above-mentioned high-frequency clock pulse corresponding to each cycle of the aforementioned ATIP FM signal at the high-frequency frequency, and LF is the pulse number of the aforementioned high-frequency clock pulse corresponding to each cycle of the aforementioned ATIP FM signal at the low-frequency frequency number. 9. A method for generating absolute time (ATIP) bit data, comprising: Generate ATIP FM signal, receive the signal generated by an optical head, and generate ATIP FM signal after processing; Generate high-frequency clock pulses, using the aforementioned ATIP FM signal as a reference to generate high-frequency clock pulses; Generate a synchronous indication signal, and generate a synchronous indication signal according to the ATIP FM signal and the aforementioned high-frequency clock pulse; and Generate the ATIP signal, take the aforementioned synchronous indication signal as a reference, and use the multiple half cycles of the aforementioned ATIP FM signal as the counting cycle to calculate the number of pulses of the aforementioned high-frequency clock pulses corresponding to each counting cycle. When the number of pulses is less than the first When the threshold is equal to or greater than the second threshold, the ATIP bit data of the first level is output, and when the pulse number is between the first threshold and the second threshold, the ATIP bit data of the second level is output. 10. absolute time (ATIP) bit data generation method as claimed in claim 9, wherein aforementioned counting period is the cycle of 7 ATIP FM signals. 11. The method for generating absolute time (ATIP) bit data as claimed in claim 9, wherein the ATIP bit data of the first level is L. 12. The method for generating absolute time (ATIP) bit data as claimed in claim 9, wherein the ATIP bit data of the second level is H. 13. The absolute time (ATIP) bit data generation method as claimed in claim 9, wherein the aforementioned first threshold is: (3*HF+LF)/8*14, Among them, HF is the pulse number of the aforementioned high-frequency clock pulse corresponding to each cycle of the ATIP FM signal at a high frequency, and LF is the pulse number of the aforementioned high-frequency clock pulse corresponding to each cycle of the ATIP FM signal at a low frequency. 14. The absolute time (ATIP) bit data generation method as claimed in claim 9, wherein the aforementioned second threshold is: (HF+3*LF)/8*14, Among them, HF is the pulse number of the aforementioned high-frequency clock pulse corresponding to each cycle of the ATIP FM signal at a high frequency, and LF is the pulse number of the aforementioned high-frequency clock pulse corresponding to each cycle of the ATIP FM signal at a low frequency.

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