CN1295599C - Instruction prefetch method of association of dynamic and inactive of overlength instruction word structure microprocessor - Google Patents

Abstract

The invention discloses a dynamic and static instruction prefetching method for a microprocessor with an ultra-long instruction word structure. The technical problem to be solved is to improve the efficiency of instruction prefetch and hide storage delay. The technical solution is to design a prefetch controller to be responsible for instruction prefetch, establish a simulation debugging environment to control instruction prefetch, design the prefetch instruction nop-pref to be compatible with NOP, replace NOP with nop-pref during compilation, and use prefetch during debugging. The fetch controller dynamically adjusts the prefetching timing, and feeds back the change information of the prefetching timing to the compiler to optimize the static prefetching strategy, and downloads the new program generated after the compiler adjusts the prefetching strategy to the RAM memory. Finally, a personalized prefetch prediction mechanism for this application system is formed. Under the premise of simple implementation of embedded microprocessor hardware and low power consumption, it hides storage delays and improves program execution efficiency. It not only overcomes the shortcomings of static prefetch to increase code length , and overcome the shortcoming of low precision of dynamic prefetching.

Description

Instruction Prefetching Method Based on Dynamic and Static Combination of VLW Structured Microprocessor

Technical field: the present invention relates to the method for instruction prefetch in very long instruction word (VLIW) structure microprocessor design, especially the method for instruction prefetch in embedded VLIW microprocessor design.

Background technology: Many current high-performance microprocessors adopt the VLIW structure, which is characterized by multiple functional units working in parallel, and instruction parallelism and data transmission are completely determined by the compiler at compile time. This mechanism of VLIW instructions is simple to implement, has low hardware complexity, and can develop more instruction-level parallelism, so it is widely used.

Due to the widening performance gap between processors and memory, storage latency becomes a system bottleneck. In order to hide storage delays, many processors use prefetch technology. Through special prefetch instructions or special hardware mechanisms, the compiler performs software scheduling or a combination of software and hardware to transfer the data of the external memory to the on-chip cache in advance. among. Among them, the precision of hardware prefetching is often not high, and if there is support from the compiler, prefetching is only performed when appropriate, which can improve efficiency and reduce unnecessary prefetching. Both IBM 370/168 and Amdahl 470V processors use prefetch technology.

Steven Paul VanderWiel studied the compiler-assisted data prefetch controller in his doctoral dissertation, which is a dynamic and static data prefetch method, which can improve the execution efficiency by about 50%. But it is researched for general-purpose CPU, the characteristics of embedded VLIW microprocessor are not fully utilized, and the code length is increased by inserting prefetching instructions.

A general embedded VLIW microprocessor system includes four parts: CPU core, Cache system, storage controller and memory, which are connected by instruction bus, data bus and address bus. The CPU core is responsible for executing instructions and writing the execution results back to the memory; the Cache system is a cache for storing instructions and data, consisting of two parts: the instruction Cache and the data Cache; the storage controller provides the interface between the memory and the Cache system, and when the CPU core When the required instruction or data is not in the Cache, the storage controller is responsible for reading the instruction or data from the memory into the Cache; the memory stores the instruction and data.

The execution program of the embedded VLIW microprocessor can be divided into several basic blocks. The basic block is the basic unit of the program. It has only one entry (ie, the first statement of the basic block) and one exit (ie, the last statement of the basic block). statement), the exit of the basic block is a branch instruction. The program code of the embedded microprocessor is generally solidified in the non-volatile memory, but in order to reduce the delay of the memory, the program code is moved to the RAM to run.

Embedded VLIW microprocessors are mainly used in computing-intensive or data-intensive embedded application systems, running embedded real-time operating systems or no operating systems, and the executed application codes are relatively fixed, and the codes are generally fixed in non-volatile In memory, rarely changed.

In the debugging stage of the embedded application system, the application system works in an environment as real as possible, and the application program code runs in the embedded VLIW microprocessor through the emulator. This kind of program running state is called emulation debugging, and the debugging host accesses the registers and memory of the VLIW microprocessor through the emulator.

Summary of the invention: The technical problem to be solved by the present invention is to make full use of the characteristics of the embedded VLIW microprocessor, and use the dynamic and static combination method to further improve the efficiency of instruction prefetch and achieve the purpose of hiding storage delay. The technical scheme of the present invention is to design a prefetch controller in the VLIW microprocessor to be responsible for instruction prefetch specially, set up a simulation debugging environment for instruction prefetch control, design prefetch instruction nop_pref and NOP instruction compatible, when compiling will The empty operation instruction NOP in the VLIW microprocessor is replaced by a prefetch instruction. During the debugging process, the prefetch controller dynamically adjusts the prefetch timing, and feeds back the change information of the prefetch timing to the compiler to optimize the static prefetch strategy. Download the new program code generated by the compiler to adjust the static prefetch strategy to the RAM memory, and form a personalized prefetch prediction mechanism for this application system after multiple feedbacks. Under the premise of low cost, the storage delay is hidden, and the program execution efficiency is improved. It not only overcomes the shortcomings of static prefetching to increase the code length, but also overcomes the shortcomings of dynamic prefetching with low precision. At present, there is no report of using this method to prefetch instructions at home and abroad.

Concrete scheme of the present invention is:

Establish a simulation debugging environment for instruction prefetch control. This environment consists of a compiler on the debugging host, an embedded application system running in a real environment, and a hardware emulator connecting the debugging host and the VLIW microprocessor in the embedded application system. The compiler reads back the prefetch adjustment information saved in the RAM memory from the embedded application system through the hardware emulator, and the compiler downloads the program code after adjusting the prefetch instructions to the embedded application system through the emulator for VLIW microprocessor implement.

A no-operation instruction (NOP) is designed in the instruction set of the embedded VLIW microprocessor, which is used to fill the delay slots of multi-cycle instructions and to align the boundaries of parallel instruction packets. NOP instructions account for about 5%-20% of the total number of instructions in general applications.

The invention designs the nop_pref instruction to be compatible with the NOP instruction, and the nop_pref instruction is the NOP instruction in the view of the CPU core.

The nop_pref instruction includes instruction effective fields V and E fields, prefetched address intrc and cst fields, and no-operation compatible part spec field. The V field indicates whether this NOP can be replaced by a nop_pref instruction. V is valid, indicating that the NOP can be replaced by a nop_pref instruction, and its address can be stored in the NOP buffer; V is invalid, indicating that the NOP cannot be replaced by a nop_pref instruction. The E field indicates whether the nop_pref directive is valid. If E is valid, it means that the nop_pref instruction can be executed, and if E is invalid, it means that the nop_pref instruction cannot be executed. The intrc field and the cst field together represent the address of the prefetched instruction. The spec field indicates the meaning of the empty operation of the NOP instruction compatible with the original instruction set, including the instruction code of the NOP, the number of cycles of the empty operation, and whether it is parallel or not.

The invention designs a prefetch controller in the embedded VLIW microprocessor to execute prefetch instructions, analyze prefetch effect and adjust prefetch timing. It consists of three parts: bus monitoring module, NOP buffer and prefetching module. The bus monitoring module is connected to the cache system and CPU core through the instruction bus and address bus. The NOP buffer is connected to the bus monitoring module and the prefetching module through the data bus and address bus. .

The bus monitoring module is composed of monitoring sub-module, decoding sub-module and time sub-module. The monitoring sub-module is a comparator, which monitors the instruction bus and address bus between the CPU core and the instruction cache. The decoding sub-module is connected to the monitoring sub-module and the NOP buffer through the data bus and the address bus. It has two functions: storing all valid nop_pref instructions in the V field into the NOP buffer; sending valid nop_pref instructions in the E field to the prefetch module for execution Prefetching. The time sub-module records the time t ₀ when the execution sub-module issues the prefetch, the time t _p when the prefetch instruction block enters the program cache, and the time t _r when the CPU core requests the instruction block, and sends these three times to the prefetch through the data bus The module analyzes the effect of prefetching.

NOP buffer is a buffer, implemented by RAM, with a first-in-first-out structure, responsible for caching the content and address of the recently executed nop_pref instruction, with a depth of N items, a write port and a read port, the write port will be the most recently executed The V field is the content and address of the effective nop_pref instruction written into the buffer item specified by the write pointer, and the write pointer is incremented in a 1, 2, 3...N, 1, 2... cycle. The read port is controlled by the prefetch module, which retrieves the NOP buffer through the read port.

The prefetch module consists of an execution sub-module and an analysis sub-module. The execution sub-module is connected with the decoding sub-module and the instruction cache through the data bus, and is responsible for issuing prefetch commands to the instruction cache. The analysis sub-module is connected to the NOP buffer and the storage controller through the data bus and the address bus, and analyzes the prefetching effect according to t ₀ , t _p and t _r to judge whether the timing of prefetching is appropriate: if t _p -t _r <0, prefetch Lag, the nop_pref position needs to be advanced; if t _p -t _r > Tm (Tm is an empirical value), the prefetch is too early, and the prefetched content occupies cache space and will not be used immediately, resulting in a waste of cache space. The position of nop_pref is moved backward; if Tm>t _p -t _r >0, the prefetching position is appropriate and no adjustment is required. The value of Tm is determined by (t _p -t ₀ ) cache capacity and cache line capacity.

The method of adjusting the nop_pref position is as follows: If nop_pref needs to be advanced, the analysis submodule retrieves the address of the nop_pref (E field is invalid) available before the nop_pref instruction in the NOP buffer, and writes the nop_pref instruction to the address of the memory through the storage controller. This address; and write back the original address of this instruction after setting the E field of this nop_pref instruction as invalid. If the nop_pref needs to be moved, the prefetch module retrieves the available nop_pref address in the NOP buffer after the nop_pref instruction, and writes the nop_pref instruction to this address; writes the invalid nop_pref instruction to the original address.

When a program was running in the embedded VLIW microprocessor, the concrete execution steps of the instruction prefetching method of the present invention are:

1. The compiler estimates the transmission time of an instruction block requested by the CPU core according to the CPU clock, memory bandwidth, and cache structure, and replaces a certain NOP (null operation) instruction in the compiled assembly code with a prefetch instruction nop_pref, so that The program executes the prefetch instruction first, and takes the instruction block out of the memory in advance and stores it in the instruction cache. When the instruction block is executed, the instruction is ready in the cache, and the CPU core can execute it immediately without waiting. The compiler performs prefetch prediction for all instruction blocks and replaces the corresponding NOP with nop_pref.

2. In order to improve the performance of prefetch, the prefetch controller dynamically adjusts the position of nop_pref according to the actual program running results during program execution. The specific process is as follows:

1) The monitoring sub-module of the prefetch controller monitors the instruction bus and address bus between the CPU core and the instruction cache, and the decoding sub-module continuously transfers the CPU core to the instruction bus of the instruction cache (hereinafter referred to as the instruction bus). The nop_pref instruction and its address are stored in the NOP buffer.

2) Once the monitoring sub-module detects the valid nop_pref command in the V field on the command bus, it sends a prefetch request to the command cache, and records this time as time t ₀ . When the program block specified by nop_pref is read into the instruction cache, record this time as time t _p . When the CPU core requests the prefetched program block, record this time as t _r time, if t _r is infinite, then this prefetch is invalid, record t _r =T _MAX . The analysis sub-module judges whether the timing of prefetching is appropriate according to the three moments of t ₀ , t _p and t _r . If t _p -t _r < 0, the prefetch lags behind, and the nop_pref position needs to be advanced; if t _p -t _r > Tm, the prefetch is advanced, and if it is too early, it will occupy the cache line too early and cause waste, and the nop_pref position needs to be moved After that; if Tm>t _p -t _r >0, the prefetching position is appropriate and no adjustment is required.

3) According to the records in the NOP buffer, the analysis sub-module adjusts this nop_pref instruction to a nop_pref position where the V field is invalid if Tm>t _p -t _r >0, and writes this nop_pref instruction to the invalid V field The address of the nop_pref to achieve the purpose of dynamically adjusting the prefetch.

3. After the program runs in the simulation environment for a period of time, the debugging host stops the running of the program through the emulator, reads the program code in the RAM memory back to the debugging host, and extracts the dynamic position adjustment information of the prefetch controller to nop_pref, that is, all The nop_pref instruction address and content are fed back to the compiler. The compiler adjusts its static prefetching strategy according to this information to adjust the position of nop_pref in the program, and the debugging host downloads the new program code after adjusting the position of nop_pref in the program to the RAM memory, and the VLIW microprocessor re-executes the program code. program. Repeating the above process, the compiler continuously revises the static prefetch strategy according to the prefetch position dynamically adjusted by the hardware, and stops the revision after a certain number of repetitions to obtain a personalized prefetch prediction mechanism for this application system. Finally, the debugging process is over, and the compiler provides fully optimized and prefetched program code, which is solidified in the embedded application system as the final program.

Adopting the present invention can produce following beneficial technical effect:

1. According to the program execution process, the instruction package required by the VLIW microprocessor is moved from the off-chip memory to the instruction cache for reading in advance, which hides the delay of the processor accessing the external memory.

2. Place the VLIW microprocessor in a real environment for simulation and debugging, and dynamically adjust the position of nop_pref through the prefetch controller according to the actual program running results, which greatly improves the accuracy of prefetch and achieves a good prefetch effect.

3. Feedback the prefetching timing information dynamically adjusted by the hardware to the compiler through the emulator, and the compiler adjusts the static prefetching strategy to regenerate the program code to perform prefetching, using the original NOP instruction in the program without increasing any code length Instruction prefetching is implemented in the case.

Description of drawings:

Fig. 1 is background technology VLIW microprocessor overall logic structural diagram;

Fig. 2 is the hardware emulation debugging environment schematic diagram that the present invention sets up;

Fig. 3 is the instruction format of prefetching instruction nop_pref of the present invention;

Fig. 4 has adopted the VLIW microprocessor logic structure diagram of the present invention;

Fig. 5 is the structural representation of NOP buffer in the prefetching controller of the present invention;

FIG. 6 is a comparison diagram of effects between the present invention and the traditional prefetching method.

Detailed ways:

FIG. 1 is an overall logical structure diagram of the background technology. The entire embedded VLIW microprocessor system includes four parts: CPU core, Cache system, storage controller and memory: the CPU core is responsible for executing instructions and writing the execution results back to the memory. It communicates with the Cache system through the instruction/data bus and address bus. Connection; the Cache system is a cache for storing instructions and data, consisting of two parts: the instruction Cache and the data Cache; the storage controller provides the interface between the memory and the Cache system, and when the instructions or data required by the CPU core are not in the Cache, the storage The controller is responsible for reading instructions or data from the memory into the Cache; the memory stores instructions and data. The four modules of CPU core, Cache system, storage controller and memory are connected through instruction bus, data bus and address bus.

FIG. 2 is a schematic diagram of a hardware emulation debugging environment established by the present invention. The hardware emulation debugging environment includes three parts: debugging host computer, hardware emulator and embedded application system. The debugging host debugs the program code running in the embedded VLIW microprocessor, and the compiler runs on the debugging host; the embedded application system is the working environment of the embedded VLIW microprocessor; the hardware emulator is the debugging host and the embedded VLIW microprocessor Provides a debug communication channel for the compiler and a prefetch communication channel for the compiler and prefetch controller.

In the debugging stage of the embedded application system, the application system works in an environment as real as possible, and the application program code runs in the VLIW microprocessor of the application system through a hardware emulator. This kind of program running state is called emulation debugging, and the debugging host can access the registers and memory of the VLIW microprocessor through the emulator.

According to the VLIW microprocessor clock, memory bandwidth and cache structure, the compiler estimates the transmission time of an instruction block requested by the CPU core, replaces a certain NOP instruction with the prefetch instruction nop_pref, and downloads the program code to the embedded Execute in the RAM memory of the application system. During program execution, the prefetch controller dynamically adjusts the position of the prefetch instruction according to the actual program running process, and writes the adjusted result back to the RAM memory. After the program code runs for a period of time in the real application system, the debugging host controls the VLIW microprocessor to stop running, reads the memory content back to the debugging host, and the static prefetching strategy is corrected by the compiler according to the prefetching information dynamically adjusted by the hardware , and then download the corrected prefetched program code to the application system for execution. Repeatedly, after multiple feedbacks, the compiler forms a personalized prefetch prediction mechanism for this application system, achieving high-efficiency prefetch at a lower cost.

Fig. 3 is the instruction format of the prefetching instruction nop_pref of the present invention. The nop_pref instruction includes instruction valid fields (V and E fields), prefetched addresses (intrc and cst fields) and a no-op compatible part (spec field). The V field indicates whether this NOP can be replaced by a nop_pref instruction. Where V is valid, indicating that the NOP can be replaced by a nop_pref instruction, and its address can be stored in the NOP buffer; V is invalid, indicating that the NOP cannot be replaced by a nop_pref instruction. The E field indicates whether the nop_pref directive is valid. If E is valid, it means that the nop_pref instruction can be executed, and if E is invalid, it means that the nop_pref instruction cannot be executed. The intrc field and the cst field together represent the address of the prefetched instruction. The spec field indicates the meaning of the empty operation of the NOP instruction compatible with the original instruction set, including the instruction code of the NOP, the number of cycles of the empty operation, and whether it is parallel or not.

Fig. 4 is a logical structure diagram of the prefetching controller of the present invention. The prefetch controller is connected to the CPU core, the instruction cache, and the storage controller through a bus. The prefetch controller consists of three parts: bus monitoring module, NOP buffer and prefetch module.

The bus monitoring module is composed of monitoring sub-module, decoding sub-module and time sub-module. The monitoring sub-module is a comparator for monitoring the instruction bus and address bus between the CPU core and the instruction cache. The decoding sub-module has two functions: storing all nop_pref instructions valid in the V field into the NOP buffer; sending the nop_pref instructions valid in the E field to the prefetch module for prefetching. The time sub-module records the time t ₀ when the prefetch is issued, the time t _p when the prefetch instruction block enters the program cache, and the time t _r when the CPU core requests the instruction block, and sends these three times to the prefetch module to analyze the prefetch effect.

The NOP buffer is responsible for caching the contents and addresses of the most recently executed nop_pref instructions. Its depth is N, and it adopts a circular writing method when writing. Its contents are retrieved by the prefetch module.

The prefetch module consists of an execution sub-module and an analysis sub-module. The execution sub-module decodes the valid nop_pref instruction, and issues a prefetch command to the instruction cache. The analysis sub-module analyzes the effect of prefetching according to t ₀ , t _p and t _r , and judges whether the timing of prefetching is appropriate; writes the adjusted prefetching instruction back into the memory through the memory controller.

Fig. 5 is the structural representation of NOP buffer among the present invention. NOP buffer is RAM, which is responsible for caching the content and address of the recently executed nop_pref instruction. It has a width of M bits and a depth of N items. It has a write port and a read port. The write port writes the content and address of the most recently executed nop_pref instruction whose V field is 1 to the buffer item specified by the write pointer, and the write pointer increments in a cyclic manner of 1, 2, 3...N, 1, 2.... The read port is controlled by the prefetch block.

FIG. 6 is a comparison diagram of effects between the present invention and the traditional prefetching method. Wherein, figure (a) is the effect without prefetching, figure (b) is the prefetching effect of the traditional method, and figure (c) is the prefetching effect of the present invention. In the figure, r1, r2 and r3 represent the three instruction fetch requests executed by the program in the CPU core. The horizontal axis represents time, and each cell on the horizontal axis represents a clock cycle. The dark gray cells indicate that the CPU core is computing. A light gray cell indicates that a memory access is in progress. The white cells indicate that the CPU core fetches and accesses the cache hit, and the required instruction is obtained immediately. The small black box indicates that the CPU core fetches and accesses the cache miss, and the required instruction cannot be obtained immediately. The colored cell indicates that the CPU core executes the prefetch instruction, and the memory starts to prefetch the instruction.

In figure (a), the CPU core sends instruction fetch requests at time r1, r2, and r3 respectively. Since there is no prefetch mechanism, the access cache does not hit, the CPU core cannot get instructions, and the pipeline pauses to wait for the memory access to end. The pipeline continues to work after receiving the instruction.

In Figure (b), the CPU core sends a prefetch request one cycle before r1, but the prefetch request is too late, so when the CPU core sends an instruction fetch request at r1, the prefetched content has not been sent to the cache. The pipeline is paused. The situation is similar when the CPU core issues an instruction fetch request at time r2, and the pipeline is still suspended. However, the CPU checks the execution time of the third prefetch instruction too early. When the instruction fetch request is issued at time r3, the instruction has been stored in the cache for three cycles, resulting in a certain degree of waste.

In Figure (c), the time when the CPU core executes the prefetch instruction is repeatedly adjusted by the prefetch controller and the compiler in the simulation environment, so that the instruction is immediately executed after being fetched into the cache, which neither causes the pipeline to pause nor wastes cache space, the overall performance of the processor has been greatly improved.

The present invention has been applied in the YHFT series DSP independently developed by the University of National Defense Science and Technology. The width of the NOPbuffer in the prefetching controller is 64 bits, the depth is 64 items, and the Tm is 3×(t _p -t ₀ ).

Claims (5)

1. the instruction prefetch method of very long instruction word structure microprocessor sound attitude combination, it is characterized in that prefetch controller of design is responsible for instruction prefetch specially in vliw microprocessor, set up an artificial debugging environment and be used for instruction prefetch control, design prefetched instruction nop-pref and NOP instruction are compatible, when compiling, the non-operation instruction NOP in the vliw microprocessor is replaced with prefetched instruction, in debug process, look ahead opportunity by dynamic adjustment of prefetch controller, and the change information that will look ahead opportunity feeds back to compiler to optimize static prefetch policy, the new procedures code that will generate after the static prefetch policy of compiler adjustment downloads to the RAM storer, forms at the personalization of this application system forecasting mechanism of looking ahead through feedback back repeatedly.

2. the instruction prefetch method of very long instruction word structure microprocessor sound attitude as claimed in claim 1 combination, it is characterized in that the described method of setting up the artificial debugging environment is: by the compiler on the debug host, the built-in applied system that under true environment, moves, the hardware emulator that connects vliw microprocessor in debug host and the built-in applied system is formed the artificial debugging environment, compiler reads back the adjustment information of looking ahead of preserving in the RAM storer by hardware emulator from built-in applied system, the program code that compiler will be adjusted behind the prefetched instruction downloads in the built-in applied system for the vliw microprocessor execution by emulator.

3. the instruction prefetch method of very long instruction word structure microprocessor sound attitude as claimed in claim 1 combination, it is characterized in that described nop-pref instruction method for designing is: it comprises effective field V of instruction and E field, the compatible part spec of address intrc that looks ahead and cst field and blank operation field: the V field shows whether this NOP can be replaced by the nop-pref instruction, V can be replaced by the nop-pref instruction for effectively showing this NOP, and its address can be deposited in NOP buffer; V is that invalid this NOP that shows cannot be replaced by the nop-pref instruction; The E field shows whether this nop-pref instruction is effective, and E can be performed for effectively representing this nop-pref instruction, and E is that this nop-pref instruction of invalid representation cannot be performed; The instruction address that the common expression of intrc field and cst field is looked ahead, spec field are represented the implication of NOP instruction blank operation in the compatible former instruction set, comprise the order code of NOP, and whether the periodicity of blank operation is parallel.

4. the instruction prefetch method of very long instruction word structure microprocessor sound attitude as claimed in claim 1 combination, it is characterized in that described prefetch controller is that prefetched instruction is carried out in design in vliw microprocessor, look ahead effect and dynamically adjust the parts of looking ahead opportunity of analysis, its method for designing is: it is by the bus monitor module, NOP buffer and prefetch module three parts are formed, the bus monitor module passes through instruction bus, address bus and cache system and CPU nuclear phase connect, and NOP buffer passes through data bus, address bus links to each other with prefetch module with the bus monitor module:

The bus monitor module is formed by monitoring submodule, decoding submodule and chronon module, monitoring submodule is comparer, monitor instruction bus and address bus between the CPU nuclear and instruction cache, constantly CPU is examined on the instruction bus of command cache effective nop-pref instruction of V field and address thereof and deposit NOP buffer in; The decoding submodule links to each other with NOP buffer with the monitoring submodule with address bus by data bus, and function has two: deposit effective nop-pref instruction of all V fields and address thereof in NOP buffer; The prefetch module execution is sent in the effective nop-pref instruction of E field looks ahead; Chronon module records implementation sub-module sends the moment t that looks ahead ₀, the prefetched instruction piece enters the moment t of program cache _p, this instruction block of CPU nuclear request moment t _r, this three times are sent into the prefetch module analysis effect of looking ahead by data bus;

NOP buffer is a buffer, adopt the first-in first-out structure, realize with RAM, be responsible for the content and the address of the nop-pref instruction of buffer memory execution recently, its degree of depth is the N item, a write port and a read port are arranged, the V field that write port will be carried out recently is the content of effective nop-pref instruction and the buffer item that the address writes the write pointer appointment, write pointer is with 1,2,3 ... N, 1,2 ... recycle design increases progressively writing mode, read port is controlled by prefetch module, and prefetch module is by read port retrieval NOP buffer;

Prefetch module is made up of implementation sub-module and analysis submodule, and implementation sub-module links to each other with command cache with the decoding submodule by data bus, is responsible for sending prefetched command to command cache; Analyze submodule and link to each other with memory controller with NOP buffer with address bus, according to t by data bus ₀, t _pAnd t _rThe analysis effect of looking ahead judges whether the opportunity of looking ahead is suitable: if t _p-t _r＜0 hysteresis of looking ahead needs with the nop-pref position in advance; If t _p-t _r＞Tm then looks ahead too early, and the content of looking ahead occupies the cache space and can not used immediately, causes the waste in cache space, after the nop-pref position need being moved; If Tm＞t _p-t _r＞0 location-appropriate of looking ahead need not to adjust; The value of Tm is t _p-t ₀, the capable capacity decision of cache capacity and cache; The method of adjusting the nop-pref position is as follows: shift to an earlier date nop-pref if desired, analyze submodule retrieves the invalid nop-pref of last available E field of this nop-pref instruction in NOPbuffer address, with this nop-pref instruction this address by the memory controller write store; And the E field of this nop-pref instruction is made as writes back the original address of this instruction after invalid; Move back nop-pref if desired, prefetch module retrieves this nop-pref and instructs a back available nop-pref address in NOP buffer, and this nop-pref instruction is write this address; This nop-pref instruction that is made as after invalid is write raw address.

5. the instruction prefetch method of very long instruction word structure microprocessor sound attitude as claimed in claim 1 combination is characterized in that when a program is moved in embedded vliw microprocessor, and concrete execution in step is:

Compiler is according to cpu clock, memory bandwidth and cache structure, estimate the transmission time of an instruction block of CPU nuclear request, change certain NOP instruction in the assembly code after the compiling into prefetched instruction nop-pref, make calling program carry out prefetched instruction earlier, in advance instruction block is taken out from storer and deposit command cache in, instruct to be ready in cache when this instruction block is performed, CPU endorses to carry out immediately and need not to wait for; Compiler is to the prediction of all looking ahead of all instruction blocks, and to replace corresponding NOP be nop-pref;

In program process, dynamically adjust the position of nop-pref according to the practical programs operation result by prefetch controller;

Program is moved a period of time under simulated environment after, debug host is by the operation of emulator shut down procedure, and with the debug host of reading back of the program code in the RAM storer, dynamically promptly all nop-pref instruction addresses and content feed are given compiler to the position adjustment information of nop-pref to extract prefetch controller, compiler is adjusted its static prefetch policy promptly to adjust the position of nop-pref in program according to this information, the new procedures code that debug host will have been adjusted behind the position of nop-pref in program downloads in the RAM storer, vliw microprocessor re-executes this program, repeat said process, compiler is constantly revised static prefetch policy according to the adjusted position of looking ahead of hardware dynamic, revise through stopping after the repetition of certain number of times, obtain at the personalization of this application system forecasting mechanism of looking ahead, last debug process finishes, compiler provides the program code that abundant optimization is looked ahead, as final program Solidification in built-in applied system.

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