CN1294547C - Driving device and method for plasma display panel - Google Patents

Abstract

In the PDP driving circuit, first and second inductors are connected to a panel capacitor. The driving circuit stores a first energy in the first inductor by a current in a first direction while the voltage of the panel capacitor is maintained at the first voltage, and reduces the voltage of the panel capacitor to a second voltage using the first energy and a resonance between the panel capacitor and the first inductor. Then, the driving circuit maintains the voltage of the panel capacitor at a second voltage, recovers energy remaining in the first inductor, stores the second energy in the second inductor by a current in a second direction, and increases the voltage of the panel capacitor to the first voltage using the energy stored in the second inductor. Therefore, the rising and falling times of the voltage of the panel capacitor are shortened, and when the drive circuit has a parasitic component, zero-voltage switching can be realized.

Description

Driving device and method for plasma display panel

Cross References to Related Applications

This application claims the benefit of priority and rights, the contents of these patent applications are incorporated herein by reference.

technical field

The present invention relates to an apparatus and method for driving a plasma display panel (PDP). More particularly, the present invention relates to a PDP sustain discharge circuit or an address drive circuit.

Background technique

In general, a PDP is a flat panel display for displaying characters or images using plasma generated by gas discharge. According to the size of the PDP, pixels ranging from hundreds of thousands to several million or more are arranged in a matrix. PDPs are classified into direct current (DC) PDPs and alternating current (AC) PDPs according to patterns of waveforms of applied driving voltages and structures of discharge cells.

When a voltage is applied to the DC PDP, current flows directly in the discharge space because the electrodes of the DC PDP are exposed to the discharge space. Therefore, a resistor for limiting the current must be provided to the DC PDP. On the other hand, in the case of AC PDP, the current is limited due to the naturally formed capacitive element because the dielectric layer covers the electrodes. Because the electrodes of the AC PDP are protected from impacts caused by ions during discharge, it has a longer lifespan than the AC PDP.

FIG. 11 shows a circuit diagram of a conventional PDP drive circuit; FIG. 12 shows a drive timing chart of a conventional PDP drive circuit.

In general, methods for driving an AC PDP include a reset cycle, an address cycle, a sustain cycle, and an erase cycle.

During the reset period, the state of each cell is reset in order to address the cell smoothly. In the address period, turned-on cells and non-turned-on cells within the panel are selected, and wall charges are accumulated for turned-on cells (ie, addressed cells). During the sustain period, a discharge is performed to actually display an image on the addressed cells. During the erase period, the wall charges of the cell are reduced, thereby ending the sustain discharge.

In AC PDP, because the plate between address electrodes, sustain electrodes, and scan electrodes works as a capacitive load, it is generally called a plate capacitor. In order to provide a waveform for addressing or for sustain discharge, reactive power is required because of the capacitance of the plate capacitor. One type of circuit used to recover and reuse reactive power is known as a power recovery circuit. L.F. Weber discloses a power recovery circuit in US patents 4,866,349 and 5,081,400.

However, the conventional power recovery circuit only uses the resonance between the panel capacitor and the inductor coupled to the panel capacitor, and works normally only when the power recovery capacitor is charged by a voltage corresponding to 1/2 of the external power. Because the conventional power recovery circuit has losses generated by itself, such as conduction loss and switching loss of switches, so that it cannot recover all the energy during the recovery process. Thus, since the panel voltage may not increase or decrease to a desired voltage value, the switch switches with difficulty, thereby generating power loss and making the time for rising or falling of the panel voltage longer.

Summary of the invention

According to the present invention, there is provided a PDP drive circuit for power recovery. The rise and fall times of the plate voltage are reduced and zero voltage switching is achieved. The invention stores energy in the inductor and uses the stored energy to change the plate voltage.

In one aspect of the present invention, an apparatus for driving a PDP having a plurality of address electrodes, scan electrodes, sustain electrodes, and plate capacitors formed between the address, scan, and sustain electrodes, comprising : first and second capacitors, which are connected in series between the first and second power supplies, respectively for providing the first and second voltages; and the first and second capacitors connected in parallel to the first and second capacitors a second switch; third and fourth switches connected in series between said first and second power sources, a connection point of the third and fourth switches being connected to said plate capacitor; and first and second inductors, connected between the first switch and the connection points of the third and fourth switches and between the second switch and the connection points of the third and fourth switches, respectively.

The apparatus also includes: a fifth switch connected between the first inductor and the second power source; and a sixth switch connected between the first power source and the first inductor.

In another aspect of the present invention, an apparatus for driving a PDP having a plurality of address electrodes, scan electrodes, sustain electrodes, and a plate capacitor formed between the address, scan, and sustain electrodes, Including: a first switch, which has a first end connected to the first power supply for providing a first voltage; a first diode, connected to a second power supply for providing a second voltage and the second end of the first switch between the second switch, connected between the plate capacitor and the connection point between the first switch and the first diode; an inductor and a third switch, which are connected in series between the second power supply and Between the connection point of the first switch and the first diode; the second diode is connected between the connection point of the inductor and the third switch and the second switch and the plate between connection points of the capacitor; and a third diode connected between the first power supply and the connection point of the second switch and the plate capacitor.

In another aspect of the present invention, an apparatus for driving a PDP having a plurality of address electrodes, scan electrodes, sustain electrodes, and a plate capacitor formed between the address, scan, and sustain electrodes, It includes: a discharge unit, which has a first inductor connected to the flat capacitor, and is used to maintain the voltage on the flat capacitor at a first voltage while using a current along a first direction to flow through the first inductor. storing a first energy in the first energy, using the first energy and the resonance between the panel capacitor and the first inductor, reducing the voltage of the panel capacitor to a second voltage, and maintaining the voltage of the panel capacitor at the first Recovering the energy remaining in the first inductor while charging two voltages; and a charging unit including a second inductor connected to the panel capacitor, for maintaining the voltage on the panel capacitor at the first voltage while maintaining the first voltage , using a current in a second direction to store a second energy in the second inductor, using the second energy and the resonance between the plate capacitor and the second inductor to reduce the voltage of the plate capacitor to ramping up to a first voltage, and recovering energy remaining in the second inductor while maintaining the voltage of the plate capacitor at the first voltage.

In another aspect of the present invention, an apparatus for driving a PDP having a plurality of address electrodes, scan electrodes, sustain electrodes, and a plate capacitor formed between the address, scan, and sustain electrodes, including: an inductor connected to the plate capacitor; and a freewheeling unit for temporarily inertially continuing the current flowing to the inductor, wherein the voltage of the plate capacitor is maintained at a first voltage while maintaining the voltage of the plate capacitor at the first voltage. storing energy in the inductor, using the energy and resonance between the panel capacitor and the inductor, changing the voltage of the panel capacitor to a second voltage, and utilizing Energy that freewheels and is continuously stored in the inductor changes the voltage of the plate capacitor to a first voltage.

In another aspect of the present invention, an apparatus for driving a PDP having a plurality of address electrodes, scan electrodes, sustain electrodes, and a plate capacitor formed between the address, scan, and sustain electrodes, Including: first and second inductors, connected to the plate capacitor; first and second signal lines, respectively used to transmit the first and second voltages; capacitors, used to be charged to the third voltage; the first current A path is formed between the first signal line and the capacitor so that a current in a first direction is supplied to the first inductor while the voltage of the plate capacitor is maintained at a first voltage, so as to store a second an energy; a second current path for generating resonance between the first inductor and the plate capacitor while storing the first energy in the first inductor, and utilizing the first energy and the resonance reduces the voltage of the panel capacitor to a second voltage; a third current path for recovering energy remaining in the first inductor while changing the voltage of the panel capacitor to the second voltage; a fourth current path, formed between the capacitor and the second signal line so that a current in a second direction opposite to the first direction can be supplied to the second signal line while maintaining the voltage of the panel capacitor at a second voltage. an inductor for storing a second energy; a fifth current path for generating resonance between the second inductor and the plate capacitor and utilizing the second energy while the second energy is stored in the second inductor said second energy and said resonance cause the voltage of the panel capacitor to increase to a first voltage; and a sixth current path for recovering the current in said second inductance while the voltage of said panel capacitor changes to said first voltage remaining energy in the device.

In another aspect of the present invention, an apparatus for driving a PDP having a plurality of address electrodes, scan electrodes, sustain electrodes, and a plate capacitor formed between the address, scan, and sustain electrodes, Comprising: an inductor connected to the plate capacitor; first and second signal lines for transmitting first and second voltages; a first current path formed between the first signal line and the second signal line , so that along this current can be supplied to the inductor, so as to store the first energy while the voltage of the plate capacitor is maintained at the first voltage; the second current path is used to store the first energy in the inductor when the first energy is stored simultaneously generate resonance between the inductor and the panel capacitor, and use the first energy and the resonance to reduce the voltage of the panel capacitor to a second voltage; at least one third current path for changing While the voltage of the plate capacitor is the second voltage, the current flowing to the inductor is freewheeled so as to maintain the remaining second energy in the inductor; the fourth current path is used to flow to the inductor generating resonance between the inductor and the panel capacitor while the current is freewheeling, and increasing the voltage of the panel capacitor to a first voltage using the second energy and the resonance; and a fifth current path, using Energy remaining in the inductor is recovered while the voltage of the plate capacitor is changed to the first voltage.

Description of drawings

FIG. 1 shows a schematic diagram of a PDP according to an embodiment of the present invention;

Fig. 2 shows the circuit diagram according to the PDP drive circuit of the first embodiment of the present invention;

3A-3E represent the current paths of various modes in the drive circuit according to the first embodiment of the present invention;

FIG. 4 shows a driving timing diagram of the driving circuit according to the first embodiment of the present invention;

FIG. 5 shows a circuit diagram of a PDP driving circuit according to a second embodiment of the present invention;

6A-6E represent the current paths of various modes in the drive circuit according to the second embodiment of the present invention;

FIG. 7 shows a driving timing diagram of a driving circuit according to a second embodiment of the present invention;

FIG. 8 shows a circuit diagram of a PDP driving circuit according to a third embodiment of the present invention;

9A-9E represent the current paths of various modes in the drive circuit according to the third embodiment of the present invention; and

Fig. 10 shows a driving timing chart of the driving circuit according to the third embodiment of the present invention.

Fig. 11 represents the circuit diagram of the PDP drive circuit of prior art;

FIG. 12 shows a driving timing chart of a conventional PDP driving circuit.

Detailed description

Fig. 1 shows a PDP according to an embodiment of the present invention.

As shown, the PDP includes a plasma panel 100 , an address driver 200 , a scan/sustain driver 300 , and a controller 400 .

The plasma display panel 100 includes: a plurality of address electrodes A1-Am along the column direction; a plurality of scan electrodes Y1-Yn arranged along the row direction; and a plurality of sustain electrodes alternately arranged along the row direction and the scan electrodes Y1-Yn X1-Xn. The address driver 200 receives an address driving control signal from the controller 400, and provides each address electrode with a display data signal for selecting a desired discharge cell. The scan/sustain driver 300 receives a sustain discharge control signal from the controller 400, and alternately inputs sustain discharge voltages to the scan electrodes and the sustain electrodes, thereby performing sustain discharge on selected discharge cells. The address driver 200 and the scan/sustain driver 300 respectively include a driving circuit (ie, a power recovery circuit) for recovering and using reactive power. The controller 400 receives an external image signal, generates an address driving control signal and a sustain discharge control signal, and supplies the signals to the address driver 200 and the scan/sustain driver 300, respectively.

Referring to FIGS. 2 to 4, the driving circuit 210 of the address driver 200 according to the first embodiment of the present invention will now be described in detail.

FIG. 2 shows a circuit diagram of a driving circuit 210 according to a first embodiment of the present invention. 3A-3E show current paths in various modes in the driving circuit 210 according to the first embodiment of the present invention, and FIG. 4 shows a driving timing chart of the driving circuit 210 according to the first embodiment of the present invention.

As shown in FIG. 2 , the driving circuit 210 includes an address unit 212 and a charging/discharging unit 214 . The address unit 212 is connected to ground and a power source Va for supplying a voltage Va, and includes address switches AH and AL, each address switch having a body diode. The voltage Va represents an address voltage and is used for addressing. A plate capacitor Cp is provided at the connection point of the address switches AH and AL. The switching operation by the address switches AH and AL is used to supply the address voltage Va or the ground voltage to the panel capacitor Cp. A plurality of address voltages 212 are respectively connected to a plurality of address electrodes A1-Am, and an address voltage Va is supplied to the address electrodes connected to the address cells 212 having the switches AH turned on.

The discharge/charge unit 214 includes switches M1-M4, boosting inductors L1 and L2, power recovery switches Ma, Mb, and capacitors Cr1, Cr2. The switches M1, M2 are connected in series between the power supply Va and the ground, and the switches M3, M4 are connected in series between the power supply Va and the ground, and the paths of the switches M1, M2 are different. Diodes D1 and D2 may be provided between the switches M1, M2 and between the switches M3, M4 for establishing a path for current supplied to and recovered from the panel capacitor Cp, respectively.

The boost inductor L1 is provided between the power recovery switch Ma and the connection point of the switches M1, M2, and the boost inductor L2 is provided between the power recovery switch Mb and the connection point of the switches M3, M4. The capacitors Cr1, Cr2 are connected in series between the power source Va and the ground, and the power recovery switches Ma, Mb are connected to a connection point provided between the capacitors Cr1, Cr2.

In FIG. 2, the switches AH, AL, M1, M2, M3, M4, Ma and Mb are represented as MOSFETs, but not limited thereto, any switches that can perform the same or similar functions can be used.

Referring to FIGS. 3A-3E and FIG. 4, the driving method of the PDP according to the first embodiment of the present invention will be described below.

In the first embodiment, it is assumed that the switches AH and M1 are turned on before the start of "mode 1", the capacitors Cr1, Cr2 are charged with respective voltages V1 and V2 (V2=Va=V1), and the inductor L1 The inductances of , L2 are set as L1 and L2 respectively.

(1) Mode 1 (t0-t1)

Referring to FIG. 3A and the time interval (t0-t1) in FIG. 4, the operation of Mode 1 will be described.

During the time interval of mode 1 (t0-t1), switches M3 and Mb are turned on, and switches AH and M1 are turned on at the same time. As shown in FIG. 3A, when the switches AH and M1 are turned on, a current path 30 is formed in the order of the switch M1, the switch AH, and the panel capacitor Cp, and thus, the address voltage Va charges the panel capacitor Cp. Wherein, when the switches M3 and Mb are turned on, a current path 31 is formed in the order of the switch M3, the inductor L2, the switch Mb and the capacitor Cr1. As shown in FIG. 4, according to the current path 31, the current IL2 flowing through the inductor L2 has a gradient of (Va-V1)/L2 and increases linearly, thereby storing energy in the inductor L2.

(2) Mode 2 (t1-t2)

Referring to FIG. 3B and the time interval (t1-t2) in FIG. 4, the operation of Mode 2 will be described.

During the time interval (t1-t2) of mode 2, the switches AH, M1, M3 are turned off, while the switch Mb is turned on. As shown in FIG. 3B, a current path 32 is formed in this order of the plate capacitor Cp, the body diode of the switch AH, the inductor L2, the switch Mb, and the capacitor Cr1. In this case, since the inductor L2 and the panel capacitor Cp flow a resonant current, the voltage Vp on the panel capacitor Cp drops from the address voltage Va to the ground voltage.

Because of the energy stored in the inductor L2, the process of discharging the voltage charged on the plate capacitor Cp can be performed rapidly. That is, the fall time (t2-t1) of the voltage Vp across the panel capacitor CP is reduced. Furthermore, in practical cases involving parasitic components of the circuit, the voltage Vp on the plate capacitor CP can be completely reduced to ground voltage due to the energy stored in the inductor L2.

(3) Mode 3 (t2-t3)

Referring to FIG. 3C and the time interval (t2-t3) in FIG. 4, the operation of Mode 3 will be described.

During the time interval (t2-t3) of mode 3, while the switch Mb is turned on, the switches M4 and AL are turned on in sequence.

When the voltage Vp on the plate capacitor CP is equal to the ground voltage at t=t2, the body diode of the switch M4 is turned on. In this case, when the switch M4 is turned on, the voltage between the drain and the source of the switch M4 builds up from a zero voltage state. That is, since the switch M4 performs zero-voltage switching, the switch M4 does not generate a turn-on switching loss. In addition, when switch M4 has parasitic components of the circuit, switch M4 is also capable of zero voltage switching because of the energy stored in inductor L2.

As shown in FIG. 3C, when the switch M4 is turned on, a current path 33 is formed in the order of the panel capacitor CP, the body diode of the switch AH, and the switch M4, and thus, the voltage Vp on the panel capacitor CP is maintained at the ground voltage. In addition, when the switch AL is turned on, the current path 34 is formed in the order of the panel capacitor CP and the switch AL, and thus, the voltage Vp on the panel capacitor CP is maintained at the ground voltage.

Further, a current path 35 is formed in the order of the body diode of the switch M4, the inductor L2, the switch Mb, and the capacitor Cr1. The current flowing to the inductor L2 has a gradient of -V1/L2 and decreases linearly to zero because of the current path 35 . That is, the energy stored in the inductor L2 is recovered into the capacitor Cr1 through the switch Mb.

Next, when switches Mb, AL, and M4 are turned on while switches Ma and M2 are turned on, a current path 36 is formed in the order of capacitor Cr1, switch Ma, inductor L1, and switch M2, and the current flowing to inductor L1 has V1 /L1 and increases linearly due to current path 36, whereby energy is stored in inductor L1.

Before mode 3 ends, switches Mb and AL are sequentially turned off, and switch AH is turned on.

(4) Mode 4 (t3-t4)

Referring to FIG. 3D and the time interval (t3-t4) in FIG. 4, the operation of Mode 4 will be described.

During the time interval (t3-t4) of mode 4, the switches M2 and M4 are turned off while the switches AH and Ma are turned on. As shown in FIG. 3D, a current path 37 is formed in the order of the capacitor Cr1, the switch Ma, the inductor L1, the switch AH, and the plate capacitor CP. In this case, since the resonance current flows through the inductor L1 and the panel capacitor CP, the voltage Vp on the panel capacitor CP increases from the ground voltage to the address voltage Va.

Due to the energy stored in the inductor L1, the process of charging the plate capacitor is performed rapidly. That is, the rising time (t4-t3) of the voltage Vp across the plate capacitor CP is shortened. Furthermore, the voltage Vp on the plate capacitor CP can be fully increased to the address voltage Va due to the energy stored in the inductor L1 with the parasitic components of the circuit.

(5) Mode 5 (t4-45)

In mode 5 (t4-t5), the switch M1 is turned on, and the switches AH and Ma are turned on at the same time.

When the voltage Vp on the plate capacitor CP reaches the address voltage Va at t=t4, the body diode of the switch M1 is turned on. In this case, when the switch M1 is turned on, the voltage between the drain and the source of the switch M1 builds up from a zero voltage state. That is, the switch M1 performs zero-voltage switching, and thus no turn-on switching loss caused by the switch M1 occurs.

As shown in FIG. 3E, when the switch M1 is turned on, a current path 38 is formed in the order of the switch M1, the switch AH, and the panel capacitor CP, thereby maintaining the voltage Vp on the panel capacitor CP equal to the address voltage Va. Further, a current path 39 is formed in this order of the switch Ma, the inductor L1, the body diode of the switch M1, and the capacitor Cr2. The current IL1 flowing to the inductor L1 has a gradient of −V1/L1 and decreases linearly to zero due to the current path 39 . That is, the energy stored in the inductor L1 is recovered into the capacitor Crr2 through the body diode of the switch M1.

According to the first embodiment of the present invention described above, in modes 1 and 3 before charging the voltage of the plate capacitor CP (mode 4), the current is stored in the inductor and the voltage of the plate capacitor CP is discharged (mode 2), And the stored energy is utilized so that the voltage Vp of the plate capacitor CP can quickly rise to the address voltage Va or drop to the ground voltage, and when there is a parasitic component of the circuit, the voltage Vp can be completely raised to the address voltage or completely dropped to the ground voltage . Furthermore, the energy stored in the inductor in mode 3 and mode 5 can be recovered and reused.

Referring to FIGS. 5, 6A-6E, and FIG. 7, a driving circuit and a driving method of a PDP according to a second embodiment of the present invention will be described.

Fig. 5 represents according to the circuit diagram of the PDP drive circuit of the second embodiment of the present invention, Fig. 6A-6E represents the current path according to each mode in the drive circuit of the second embodiment of the present invention, Fig. 7 represents according to the first embodiment of the present invention The driving timing chart of the driving circuit of the second embodiment.

As shown in FIG. 5, the driving circuit 210 has the same circuit as that of the first embodiment except for the switches M2, M3 shown in FIG.

In detail, the switches M1, M4 of the charging/discharging unit 214 according to the second embodiment are connected in series between the power supply Va and the ground, and the address unit 212 and the connection point of the switches M1, M4 are connected. The inductance L1 is provided between the power recovery switch Ma and the connection point between the switches M1, M4, and the inductance L2 is provided between the power recovery switch Mb and the connection point of the switches M1, M4. Diodes D1 and D2 are also provided between the inductor L1 and the switch Ma and between the inductor L2 and the switch Mb for forming current paths, respectively.

Referring to FIGS. 6A-6E and FIG. 7, the PDP driving method of the second embodiment of the present invention will be described.

In the second embodiment, it is assumed that switches AH and M1 are turned on before mode 1 starts and capacitors Cr1, Cr2 are charged to voltages V1 and V2 (=Va-V1) in the same manner as in the first embodiment.

(1) Mode 1 (t0-t1)

During the mode 1 time interval (t0-t1), the switch Mb is turned on, and the switches AH and M1 are turned on at the same time. As shown in FIG. 6A, when the switches AH and M1 are turned on, a current path 60 is formed and the plate capacitor CP is charged to the address voltage Va. Wherein, when the switch Mb is turned on, the current path 61 is formed, and the current IL2 flowing to the inductor L2 has a gradient of (Va-V1)/L2 and increases linearly, thereby storing energy in the inductor L2.

(2) Mode 2 (t1-t2)

During the mode 2 time interval (t1-t2), switches AH and M1 are turned off, while switch Mb is turned on. As shown in FIG. 6B, a current path 62 is formed at this time, and a resonance current is generated due to the inductor L2 and the panel capacitor CP, and thus, the voltage Vp of the panel capacitor CP drops from the address voltage Va to the ground voltage.

(3) Mode 3 (t2-t3)

During the time interval (t2-t3) of mode 3, while the switch Mb is turned on, the switches M4 and AL are turned on sequentially. As shown in FIG. 6C , current paths 63 and 64 are formed, and the voltage Vp of the panel capacitor CP is held at the ground voltage. Furthermore, a current path 65 is formed, the current IL2 flowing to the inductor L2 has a gradient of -V1/L2, and decreases linearly to 0, and thus, the energy stored in the inductor L2 is recovered to the capacitor Cr1 through the switch Mb.

In this case, since the voltage Vp of the panel capacitor CP is equal to the ground voltage, and the switch M4 is turned on while the body diode of the switch M4 is turned on, the switch M4 does not generate a turn-on switching loss.

Next, when the switches Mb, M4, and AL are turned on while the switch Ma is turned on, the current path 66 is formed, and the current flowing to the inductor L1 has a gradient of V1/L1 and increases linearly, thereby storing energy.

Before mode 3 ends, switches Mb and AL are sequentially turned off, and switch AH is turned on.

(4) Mode 4 (t3-t4)

During the time interval (t3-t4) of mode 4, the switch M4 is turned off while the switches AH and Ma are turned on. As shown in FIG. 6D, a current path 67 is formed, and since a resonance current flows due to the inductor L1 and the panel capacitor CP, the voltage Vp on the panel capacitor CP rises from the ground voltage to the address voltage.

(5) Mode 5 (t4-t5)

During the time interval (t4-t5) of mode 5, the switch M1 is turned on while the switches AH and Ma are turned on. As shown in FIG. 6E, a current path 68 is formed at this time, thereby maintaining the voltage Vp of the plate capacitor CP at the address voltage Va.

In this case, since the voltage Vp of the panel capacitor CP is equal to the address voltage Va, and the switch M1 is turned on while the body diode of the switch M1 is turned on, the switch M2 does not generate a turn-on switching loss.

In addition, another current path 69 is formed, and the current flowing to the inductor L1 has a gradient of -V2/L1 and thus decreases linearly to zero. That is, the energy stored in the inductor L1 is recovered to the capacitor Cr2 through the body diode of the switch M1.

According to the second embodiment of the present invention described above, in modes 1 and 3 before charging the voltage of the plate capacitor CP (mode 4), the current is stored in the inductor and the voltage of the plate capacitor CP is discharged (mode 2), And the stored energy is utilized so that the voltage Vp of the plate capacitor CP can quickly rise to the address voltage Va or fall to the ground voltage, thereby reducing the rise and fall time. Furthermore, in mode 3 and mode 5, the energy stored in the inductor can be recovered and reused.

The drive circuits according to the first and second embodiments of the present invention are examples of PDP address drive circuits, and drive circuits having elements of capacitive loads may also be used. For example, it can be used for a sustain electrode drive circuit and a scan electrode drive circuit of scan/sustain driver 300 .

In the first and second embodiments, different inductors are used to charge and discharge the panel capacitor CP, and one inductor may be used to charge and discharge the panel capacitor CP. Next, a third embodiment will be described with reference to Figs. 8, 9A-9E, and Fig. 10 .

Fig. 8 shows the circuit diagram according to the PDP driving circuit of the third embodiment of the present invention, Fig. 9A-9E shows according to the current path of each mode in the driving circuit of the third embodiment of the present invention, Fig. 10 shows according to the first of the present invention The driving timing chart of the driving circuit of the third embodiment.

Referring to FIG. 8, a driving circuit 210 of an address driver 200 according to a third embodiment of the present invention is illustrated.

As shown, the driving circuit 210 includes an address voltage 212 and a charging/discharging unit 214 . Since the address unit 212 is the same as that of the first embodiment, no further description is given.

The charging/discharging unit 214 includes switches M1, M2 and M3, an inductor L, freewheeling diodes D1 and D2, and a recovery diode D3. The switch M1, the inductor L, and the switch M3 are connected in series between the power supply Va and the ground, and the diode D1 is connected between the ground and the connection point of the switch M1 and the inductor L.

The switch M2 is connected between the switch AH of the address unit 212 and the connection point of the switch M1 and the inductor L. Diode D2 is connected between switch AH and the junction of inductor L and switch M3. The diode D3 is connected between the power supply Va and the connection point of the switch M2 and AH, and it recovers the current flowing to the inductor L to the power supply Va.

In this case, a diode D4 for establishing a path for the current recovered from the panel capacitor CP may also be provided between the inductor L and the switch M3.

A PDP driving method according to the third embodiment will be described with reference to FIGS. 9A-9E and FIG. 10 .

In the third embodiment, it is assumed that the plate capacitor CP is charged to the address voltage Va before mode 1 starts, the switch M1 and the switch AH of the address cell are turned on, and the inductance of the inductor L is L.

(1) Mode 1 (t0-t1)

Mode 1 will be described with reference to FIG. 9A and the time interval (t0-t1) in FIG. 10 .

In the mode 1 time interval (t0-t1), the switches M2 and M3 are turned on, and at the same time the switches M1 and AH are turned on.

As shown in FIG. 9A, when the switch M2 is turned on while the switches M1 and AH are turned on, a current path 91 is formed in the order of the switch M1, the switch M2, the switch AH, and the panel capacitor CP, and thus, the voltage of the panel capacitor CP Vp holds the address voltage Va. Furthermore, when the switch M3 is turned on while the switch M1 is turned on, a current path 92 is formed in the order of the switch M1, the inductor L, the diode D4, and the switch M3. The current IL flowing to the inductor L according to the current path 91 has a gradient of Va/L and increases linearly, whereby energy is stored in the inductor L.

(2) Mode 2 (t1-t2)

Referring to FIG. 9B and the time interval (t1-t2) of FIG. 10, the operation of Mode 2 will be described.

During the mode 2 time interval (t1-t2), while the switches AH, M2, and M3 are turned on, the switch M1 is turned off. As shown in FIG. 9B , at this time, a current path 93 is formed in the order of the plate capacitor CP, the switch AH, the switch M2 , the inductor L, the diode D4 , and the switch M3 . In this case, a resonance current flows due to the inductor L and the panel capacitor CP, and thus, the voltage Vp of the panel capacitor CP drops from the address voltage to the ground voltage, and the current IL flowing to the inductor L continues to increase.

Because of the energy stored in the inductor L in mode 1, the process of recovering the charging voltage of the panel capacitor CP is performed quickly. That is, since the fall time (t2-t1) of the voltage Vp of the plate capacitor CP is reduced, quick address recovery can be achieved. Furthermore, the voltage Vp of the plate capacitor CP can drop completely to the ground voltage due to the energy stored in the inductor L in a practical situation including parasitic components of the circuit.

(3) Mode 3 (t2-t3)

Referring to FIG. 9C and the time interval (t2-t3) of FIG. 10, the operation of Mode 3 will be described.

During the time interval of mode 3 (t2-t3), the switch AH is turned off while the switches M2 and M3 are turned on, and the switch AL is turned on.

When the switch AH is turned off while the switches M2 and M3 are turned on, the current flowing through the inductor L is directed to the current formed in the order of the inductor L, the diode D4, the switch M3, and the diode D1 according to the freewheeling diodes D1 and D2. The path 94, and the current path 95 formed by the inductor L, the diode D2 and the switch M2 in this order continue to flow. Because of the freewheeling described above, the current IL flowing to the inductor L can continue to maintain a predetermined value, as shown in FIG. 10 .

When the switch AL is turned on, a current path 96 is formed in the order of the panel capacitor CP and the switch AL, and thus, the voltage Vp of the panel capacitor CP is maintained at the ground voltage.

Switch AL is turned off before mode 3 ends.

(4) Mode 4 (t3-t4)

Referring to FIG. 9D and the time interval (t3-t4) in FIG. 10, the operation of Mode 4 will be described.

During the time interval (t3-t4) of mode 4, the switches M2 and M3 are turned off, and the switch AH is turned on. As shown in FIG. Current path 97 .

Due to the resonant current on the current path 97 due to the inductor L and the panel capacitor CP, the voltage Vp of the panel capacitor CP rises from the ground voltage to the address voltage. Due to the energy stored in the inductor L, the process of charging the voltage of the plate capacitor CP proceeds rapidly. That is, the rise time (t4-t3) of the voltage Vp of the panel capacitor CP is reduced. Furthermore, when there is a parasitic component of the circuit, the voltage Vp of the panel capacitor CP can be fully increased to the address voltage Va because of the energy stored in the inductor L.

When the voltage Vp of the panel capacitor CP is charged to the address voltage Va, a current path 98 is formed in the order of the diode D1, the inductor L, the diode D2, and the diode D3. Because of the current path 98, the current IL flowing to the inductor L is recycled to the power supply and reduced to zero.

(5) Mode 5 (t4-t5)

In mode 5 (t4-t5), while the switch AH is turned on, the switch M1 is turned on. As shown in FIG. 9E , at this time, a current path 99 is formed by the switch M1 , the body diode of the switch M2 , the switch AH, and the panel capacitor CP, so as to maintain the voltage Vp of the panel capacitor CP as the address voltage Va.

Thereafter, Mode 1 to Mode 5 are repeated, and thus, the voltage Vp of the panel capacitor CP is repeatedly switched between the address voltage Va and the ground voltage.

According to the third embodiment of the present invention described above, by storing energy in the inductor and using the stored energy, the voltage Vp of the plate capacitor CP can be quickly raised to the address voltage or dropped to the ground voltage, and when With the parasitic component of the circuit, the voltage Vp of the plate capacitor CP can be fully raised to the address voltage or fully dropped to the ground voltage.

Although the invention has been described in connection with what is presently considered to be the best embodiment, it is to be understood that the invention is not limited to the disclosed embodiment, but on the contrary is intended to cover various modifications within the concept of the appended claims. type and its equivalents.

Claims (15)

1. device that is used to drive plasma display panel, described plasma display panel have a plurality of address electrodes, scan electrode, keep electrode and in described address, scan and keep the plate condenser that forms between the electrode, comprising:

First and second capacitors, they are connected in series between first and second power supplys, and being respectively applied for provides first and second voltages;

First and second switches that are connected in parallel with the tie point of described first and second capacitors;

Be connected in series in third and fourth switch between described first and second power supplys, the tie point of described third and fourth switch links to each other with described plate condenser; And

First and second inductors are connected between the tie point of described first switch and described third and fourth switch, and between the tie point of described second switch and described third and fourth switch.

2. device as claimed in claim 1 also comprises:

The 5th switch is connected between described first inductor and the described second source; And

The 6th switch is connected between described first power supply and described first inductor.

3. device as claimed in claim 1, wherein said third and fourth switch comprises body diode.

4. device as claimed in claim 1, wherein said first voltage is the address voltage that is used for the described plate condenser of addressing, described second voltage is ground voltage.

5. device that is used to drive plasma display panel, described plasma display panel have a plurality of address electrodes, scan electrode, keep electrode and in described address, scan and keep the plate condenser that forms between the electrode, comprising:

Discharge cell, it has first inductor that links to each other with described plate condenser, the voltage that is used on making described plate condenser is kept in first voltage, utilization is stored first energy along the electric current of first direction in described first inductor, utilize described first energy and the resonance between described plate condenser and described first inductor, the voltage of plate condenser is reduced to second voltage, and when the voltage of keeping plate condenser is second voltage, reclaim the energy that remains in described first inductor; And

Charhing unit, comprise second inductor that links to each other with described plate condenser, when being used to make voltage on the described plate condenser to keep first voltage, utilization is stored second energy along the electric current of second direction in described second inductor, utilize described second energy and the resonance between described plate condenser and described second inductor, the voltage of plate condenser is risen to first voltage, and when the voltage of keeping plate condenser is first voltage, reclaim the energy that remains in described second inductor.

6. device as claimed in claim 5, wherein said charhing unit also comprises first switch, be connected between described second inductor and first power supply, be used to provide first voltage, and when the voltage of plate condenser reaches described first voltage, make described first switch conduction, and described discharge cell also comprises second switch, be connected between described first inductor and the second source, be used to provide second voltage, and when the voltage of plate condenser reaches described second voltage, make described second switch conducting.

7. device as claimed in claim 6, wherein first and second switches comprise body diode respectively, and energy remaining reclaims by the body diode of first switch in second inductor, and energy remaining reclaims by the body diode of second switch in first inductor.

8. device that is used to drive plasma display panel, described plasma display panel have a plurality of address electrodes, scan electrode, keep electrode and in described address, scan and keep the plate condenser that forms between the electrode, comprising:

First and second inductors link to each other with described plate condenser;

First and second signal wires are respectively applied for transmission first and second voltages;

Capacitor is used to be charged to tertiary voltage;

First current path is formed between described first signal wire and the described capacitor, makes when the voltage of plate condenser is maintained first voltage, offers described first inductor along the electric current of first direction, so that store first energy;

Second current path is used for producing resonance between first inductor and plate condenser in described first energy of described first inductor storage, and utilizes described first energy and described resonance that the voltage of plate condenser is reduced to second voltage;

The 3rd current path is used for being recovered in energy remaining in described first inductor when the voltage that changes plate condenser is second voltage;

The 4th current path, be formed between described capacitor and the described secondary signal line, make that when the voltage of keeping plate condenser is second voltage the electric current of the second direction that the edge is opposite with described first direction can offer described second inductor, so that store second energy;

The 5th current path is used for producing resonance between second inductor and plate condenser, and when described second energy is stored in described second inductor, utilizes described second energy and described resonance to make the voltage of plate condenser be increased to first voltage; And

The 6th current path is used for being recovered in the described second inductor energy remaining when the voltage of described plate condenser is changed into described first voltage.

9. device as claimed in claim 8, wherein said first signal wire links to each other with plate condenser, so that keeping the voltage of plate condenser is first voltage, and described secondary signal line links to each other with plate condenser, is second voltage so that keep the voltage of plate condenser.

10. device as claimed in claim 8 also comprises:

First switch, it is connected between the tie point of secondary signal line and the plate condenser and first inductor, and has body diode; And

Second switch, it is connected between the tie point of first signal wire and the plate condenser and second inductor, and has body diode,

Wherein first switch conducting when the voltage of plate condenser equals second voltage, and second switch conducting when the voltage of plate condenser equals first voltage.

11. device as claimed in claim 10, wherein the body diode by first and second switches forms the 3rd and the 6th current path.

12. a method that is used to drive plasma display panel, described plasma display panel have a plurality of address electrodes, scan electrode, keep electrode and in described address, scan and keep the plate condenser that forms between the electrode, comprising:

(a) when being maintained at first voltage, the voltage of capacitor provides electric current to first inductor that links to each other with plate condenser, so that store first energy along first direction;

(b) utilize first energy and the resonance between the plate condenser and first inductor that the voltage of plate condenser is changed into second voltage;

(c) flow to the electric current of first inductor by the resonance afterflow, so that storage second energy in first inductor, perhaps be recovered in the energy of storing in first inductor, the edge second direction opposite with first direction provides electric current to second inductor that links to each other with plate condenser, so that store second energy.And the voltage of keeping plate condenser equals second voltage;

(d) utilize the resonance between second energy and in the plate condenser and first and second inductors one that the voltage of plate condenser is changed into first voltage; And

(e) voltage of keeping plate condenser equals first voltage, and is recovered in the energy remaining in one of first and second inductors.

13. method as claimed in claim 12, wherein plasma display panel also comprises at least two diodes, and it has the two ends that link to each other with the two ends of first inductor, and at (c), the electric current that flows to first inductor is by described diode continuousing flow.

14. method as claimed in claim 12, wherein said plasma display panel also comprises: first switch, and it is connected between the plate condenser and first power supply, is used to provide first voltage; And second switch, it is connected between plate condenser and the second source, be used to provide second voltage, and at (c), the second switch conducting equals second voltage so that keep the voltage of plate condenser, and at (e), first switch conduction equals first voltage so that keep the voltage of plate condenser.

15. method as claimed in claim 12, wherein said plasma display panel also comprises: the 3rd switch, and it is connected between first inductor and second voltage; And the 4th switch, it is connected between first voltage and second inductor, and (c) also comprise when the voltage of plate condenser is changed into second voltage and make the 3rd switch conduction, and (e) also comprise, when the voltage of plate condenser is changed into first voltage, make the 4th switch conduction.

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