CN1293739C - High speed link control protocol transmission processing/module and data processing/method - Google Patents

Abstract

The invention belongs to the technical field of network interconnection equipment, and relates to an HDLC protocol sending processing module and a data processing method thereof. The module includes: a port arbitration module, a sending HDLC protocol processor and a state memory module; its data processing method is: the port arbitration module receives the data request signals of N ports, and sends the request signals of the ports according to the priority level Pass it to the sending HDLC protocol processor in turn, and provide arbitration for the shared data processing pipeline of N ports; the sending HDLC protocol processor reads the unprocessed data from the FIFO, reads the state data of the HDLC channel to which the data belongs from the state memory module, and Its data is processed by the pipeline, and the processed data is sent to the corresponding port; and the new state data of the HDLC channel is written back to the state memory. The invention has the advantages of high processing speed, no linear increase of chip area with the increase of ports and strong versatility.

Description

High-speed data link control protocol sending processing module and data processing method thereof

technical field

The invention belongs to the technical field of network interconnection equipment, and in particular relates to the structural design of a high-speed data link control (HDLC) protocol transmission processing module and a data processing method thereof.

Background technique

Serial communication control chips are usually used in communication devices such as routers and switches, and often need to control multi-port and multi-channel data streams at the same time, which means performing high-speed data links on multiple channels of multiple ports at the same time. Send/receive processing of the HDLC protocol.

The HDLC protocol is at the second layer of the Open Systems Interconnection (OSI) seven-layer network reference model: the data link layer. The data frame structure of the HDLC protocol is shown in Figure 1. In the figure: the HDLC data frame uses the hexadecimal number 7E (0x7E) as the frame start and frame end signs, and there is a frame check field (FCS) before the frame end character. ) is used for frame check (CRC) of data, this field is an optional field, there may be no frame check. Frames are filled with 0x7E or 0xFF, and two consecutive frames can share a 0x7E as the frame start and frame end. In addition, if an error occurs when sending a frame, a frame stop flag (0xFF) can be sent to indicate that the frame data is wrong, and if more than 7 consecutive 1s are found during reception, it will be considered as a frame stop mark. When sending, since there may also be 0x7E in the data, in order to avoid mistaking 0x7E in the data as a frame identifier, it is necessary to use the zero insertion function: if there are 5 consecutive 1s found in the data and frame check fields, then add them to the 5 consecutive 1s. Insert a zero after 1, so that there will be no frame identifier in the data and frame check fields. At this time, the zero deletion function must be used at the receiving end: if there are 5 consecutive 1s found in the data and frame check fields, the following zero will be removed to restore the original data.

The structure of an existing serial communication controller chip is shown in Figure 2, including: physical layer interface module, protocol processing module, first-in-first-out buffer (FIFO), direct memory access (DMA) module and peripheral component expansion Interface (PCI) module; wherein, the physical layer interface module module is responsible for the interface with the first physical layer of the OSI reference model, and converts the serial data received by the physical layer into 8bit parallel data and sends it to the protocol processing module, or processes the protocol The 8bit parallel data sent by the module becomes serial data and sent to the physical layer for processing.

The protocol processing module includes an HDLC protocol processing module and an asynchronous serial port protocol processing module, which respectively perform protocol processing of the synchronous HDLC serial port and the asynchronous serial port. The protocol processing of the asynchronous serial port has nothing to do with the present invention and will not be introduced again.

The structure of the HDLC protocol processing module is shown in Figure 3, which consists of a receiving HDLC protocol processing module and a sending HDLC protocol processing module. These two modules are independent of each other and process the received data and sent data respectively, so that the system can work in full duplex.

Among them, the functions to be completed by the sending protocol processing module:

1. Support M HDLC channels;

2. Support N ports, each port can have multiple HDLC channels at the same time;

3. Support transparent transmission;

4. Automatic generation of frame start and frame end signs;

5. Support shared frame start and frame end flags;

6. The data between two transmission frames is automatically filled, and the filling characters are programmable;

7. Support zero insertion function;

8.16-bit/32-bit CRC frame check generation (CRC16 and CRC32);

9. Support the exchange of high and low bits in the byte;

10. Support port data inversion;

11. Support flow control function.

The structure of the existing sending HDLC protocol processing module is shown in Figure 4, which consists of N sending HDLC protocol processors, a state memory, a state arbitration module and a data fetching arbitration module.

In order to facilitate the description of the problems existing in the sending HDLC protocol processing module and its data processing method, the following takes the HDLC protocol sending processing for 256 channels of 16 ports as an example.

As can be seen from Figure 4, using the existing serial HDLC protocol processing module to process the serial data of 16 ports requires 16 (one for each port) to send HDLC protocol processors, but since each HDLC channel A large amount of intermediate data (about one hundred bits) needs to be saved, so 16 processors must share a state memory to access the intermediate data of 256 HDLC channels, so the operation of the state memory needs to be arbitrated. At the same time, because the 16 sending HDLC protocol processors receive data from the first-in-first-out buffer circuit (FIFO) used to store the data to be sent in each channel at the same time, arbitration is also required here. Arbitration in these places becomes the bottleneck of the system speed, so even if the speed of each processor is increased, the port rate cannot be effectively improved. Using this scheme when the main clock is 33MHz, the maximum port rate of each port can only reach about 8Mbps at most, and since 16 sending HDLC protocol processors are used, the occupied chip area is also large.

Contents of the invention

The purpose of the present invention is to propose a high-speed data link control protocol transmission processing module and its data processing method in order to overcome the deficiencies of the prior art, so that it has fast processing speed and the area of the chip will not decrease with the increase of ports. The advantages of linear increase and strong versatility.

The present invention proposes a high-speed data link control protocol sending processing module, which is characterized in that it is composed of a port arbitration module, a sending high-speed data link control protocol processor and a state memory module; wherein said port arbitration The input end of the module is connected with N ports, and the input end of the said sending high-speed data link control protocol processor is respectively connected with the output end of the port arbitration module and the first-in-first-out buffer circuit for storing the data to be sent in each channel The output end is connected, and at the same time, it is bidirectionally connected with the state memory module, and the output end of the sending high-speed data link control protocol processor is connected with N ports.

The present invention also proposes a data processing method for the above modules, characterized in that, comprising the following steps:

1) The port arbitration module receives the data request signals of N ports, transmits the request signals of the ports to the high-speed data link control protocol processor in sequence according to the priority level, and provides arbitration for the shared data processing pipeline of the N ports;

2) The sending high-speed data link control protocol processor reads the unprocessed data from the first-in-first-out buffer circuit used to store the data to be sent in each channel, and transfers the state data of the high-speed data link control channel to which the data belongs from the state memory The module reads out, performs pipeline processing on its data, and sends the processed data to the corresponding port;

3) Write the new state data of the high-speed data link control channel back to the state memory.

Features and good effects of the present invention:

1) Use the parallel sending high-speed protocol processor in the method of the present invention to process the data streams of all ports, and if the ports have data to be processed at the same time, then process them in priority order. The processing capability of the HDLC protocol processing module is greatly improved by parallel and pipeline processing of data, and the one-way throughput is 8 times the clock rate.

2) the pipeline structure is adopted inside the high-speed processor of the present invention, and each clock can process an 8-bit data. If the chip supporting 16 ports reaches 264Mbps in one-way data throughput when the clock is 33MHz, the maximum rate of the port can reach 52Mbps, with an average port speed of 16Mbps.

3) Since the present invention only uses one sending HDLC protocol processor to process N port data, the area of the control chip occupied by the protocol processing part will not increase linearly with the increase of ports. And it turns out that the chip area occupied by the sending HDLC protocol processor is not larger than that of a single serial HDLC protocol processor. That is to say, if the supported ports are 16, the chip area occupied by the protocol processing module using the HDLC protocol processor is only about 1/16 of that of the existing serial HDLC protocol processor solution. The number is more, such as 32, 64, and its advantages are incomparable.

Description of drawings

Fig. 1 is a schematic diagram of HDLC frame structure.

Fig. 2 is the structural block diagram of the existing serial communication controller chip.

Fig. 3 is a structural block diagram of an existing HDLC protocol control module.

FIG. 4 is a structural block diagram of an existing sending HDLC protocol processing module.

Fig. 5 is the structure of the sending HDLC protocol processing module of the present invention.

FIG. 6 is a schematic structural diagram of a three-stage pipeline of the present invention.

FIG. 7 is a schematic diagram of the HDLC protocol transmission processing state machine of the present invention.

Detailed ways

A kind of high-speed data link control protocol sending processing module and data processing method thereof for controlling the serial port communication controller chip of N (taking N=16 as embodiment) ports that the present invention proposes, in conjunction with accompanying drawing, describe in detail as follows:

The structure of the sending HDLC protocol processing module of this embodiment is shown in FIG. 5 , which consists of a port arbitration module, a sending HDLC protocol processor and a state memory module. Wherein, the input end of said port arbitration module is connected with 16 ports, and the input end of said sending high-speed data link control protocol processor is respectively connected with the output end of the port arbitration module and the data to be sent for storing each channel. The output end of the FIFO is connected, and is connected bidirectionally with the state memory module at the same time, and the output end of the sending high-speed data link control protocol processor is connected with 16 ports.

The data processing method of the sending HDLC protocol processing module of the present embodiment is: the port arbitration module receives the data request signals of 16 ports, and sends the request signals of the ports to the sending HDLC protocol processor in turn according to the priority level, and is 16 ports The shared data processing pipeline provides arbitration; the sending HDLC protocol processor reads data from the FIFO, reads the state data of the HDLC channel to which the data belongs from the state memory module, performs pipeline processing on the data read from the FIFO, and processes the processed The data is sent to the corresponding port, and the new state data of the HDLC channel is written back to the state memory.

In order to improve the sending efficiency, the HDLC protocol sending processor of the present embodiment is provided with a secondary cache structure composed of a data buffer register (level one buffer) and a data buffer register (secondary buffer) to cache the data read from the FIFO, That is: put the data read from the FIFO into the first-level buffer, the second-level buffer fetches data from the first-level buffer, and send the protocol processor to process the data in the second-level buffer, so that the protocol processor can process the data in the second-level buffer. While the data in the secondary buffer is being processed, the primary buffer can read the subsequent data from the FIFO.

The specific implementation steps of the data processing method in this embodiment are described in detail as follows:

The above-mentioned method of providing arbitration for the shared data processing pipeline of the 16 ports specifically includes the following steps: placing the data channel with the highest rate among the request data of the 16 ports on the port with the smaller port number, and the smaller the port number is, the priority is given to the arbitration. The higher the level, that is, when multiple ports request data at the same time, the port with the lower number is processed first. When in use, the port rate can be set not to exceed the maximum rate and the total data throughput not to exceed the maximum throughput. Since the data request of each port comes every (8×processing clock frequency/port rate) processing clocks, the situation that the previous data request has not been processed and the next data request has come will not occur.

The above-mentioned method for sending the HDLC protocol processor to carry out pipeline processing of data, the specific steps are: see whether the port arbitration module has channel application data, if there is an application, the protocol processing pipeline is started, if there is no application, the processing pipeline of this clock cycle is idle.

Since the data processing is complicated and difficult to complete in one clock cycle, the processing pipeline of this embodiment adopts a three-stage pipeline to realize data processing. As shown in FIG. 6 , each clock can process an 8-bit parallel data. Each level of pipeline completes the corresponding work, and the data is clocked and sent to the next level for further processing. The work of each level of pipeline is carried out in parallel, so it is possible to process the data of 3 channels at the same time. The data processing method specifically includes the following steps:

first level

1. If there is an application for the port, the channel number of the applied data, the port where it is located, the working mode, and the flow control indicator signal are latched;

2. Send a read enable signal to the state memory;

second level

1. Latch the state data read from the state memory;

2. For the read data to be sent, if it is currently in the state of sending data or frame verification, perform 5 consecutive 1 detections, perform zero insertion, and obtain zero-filled data;

3. Merge the data to be sent this time with the remaining data from the last time to obtain the total data to be sent;

4. Perform the state jump of the sending processing state machine according to the state bit information;

5. Obtain new data to be sent according to the state of the sending processing state machine;

6. If the data buffer register (level 1 buffer) has been sent to the data buffer register (level 2 buffer), then request new data from the sending FIFO;

third level

1. Complete the data flip operation (optional) for the data to be sent, and send the data to the corresponding port;

2. If the send processing state machine is in the state of sending data, perform frame check calculation on the currently prepared data;

3. If the data buffer register (secondary buffer) is emptied and the data in the buffer register (first-level buffer) is valid, then the data in the first-level buffer is sent to the second-level buffer, and the bit sequence selection function is completed at the same time;

4. If the first stage has sent the request data to the FIFO, then write the new data requested from the FIFO into the buffer register; if the data in the buffer register is sent out, the buffer register is cleared, otherwise the buffer register remains unchanged;

5. Send the write enable message, and write the new status bit into the status memory.

In the second-level pipeline processing method above, the HDLC protocol transmission processing state machine is used, and the state machine is used to control the processing process of HDLC protocol transmission. The state transition diagram of the state machine is shown in Figure 7. The state of the sending processing state machine includes: idle state, inter-frame filling, exception handling, inserting frame header, sending data, frame checking and frame tail insertion;

Each jump condition is explained as follows:

When no line error is found, the conditions for each state jump include:

The state machine is idle when reset (rst);

a- If there is data in the data buffer register and it is in non-transparent mode, if the inter-frame filling selection bit is 0000 or 0001, and the flow control register is high. Jump from idle state to frame header insertion state;

b- and when the flow control register is high, if the inter-frame filling selection bit is not 0000 or 0001, jump from the idle state to the inter-frame filling state;

c - unconditionally jump along the c path;

d- If the frame data is sent, when working in the non-transparent mode and the flow control is turned on, when the frame check is selected as CRC16 or CRC32, it will jump from the sending data state to the frame checking state;

e- If the frame data is sent, and the flow control is turned on, and the frame check selection is not CRC32 or CRC16, jump from the state of sending data to the state of inserting the end of the frame.

g-If the frame check is selected as CRC16, jump along the g path when the frame check send byte count is 2; if the CRC is selected as CRC32, jump from the CRC state when the frame check send byte count is 4 Go to end-of-frame insertion state;

h- If the buffer data valid register is high, and the inter-frame filling selection bit is 0000, then the frame identifiers of adjacent frames are multiplexed, and the flow control is turned on, jumping directly from the frame end insertion state to the sending data state, at this time continuous The data frame shared frame flag;

i- If the buffer data valid register is high, and the inter-frame filling selection bit is 0001, jump from the frame end insertion state to the frame head insertion state;

j- If the buffer data valid register is high, and the inter-frame filling selection bit is not 0000 or 0001, jump from the frame end insertion state to the inter-frame filling state;

k-If the buffer data valid register is low, or the flow control register is closed; then jump from the end-of-frame insertion state to the idle state;

r- If the inter-frame filling has been sent, jump from the inter-frame filling state to the frame header insertion state;

When a line error is found, if the flow control is closed or the frame stop flag is required to be sent when an error occurs, the state machine is always in the exception processing state, otherwise the transition conditions are as follows:

f- If the buffered data valid register is low (may be caused by an error), and the data frame is not over, jump from the sending data state to the exception handling state;

l- If the buffer data valid register is high, and the inter-frame filling selection bit is 0000 or 0001, then jump from the exception handling state to the frame header insertion state;

m-If the buffer data valid register is high, and the inter-frame filling selection bit is not 0000 or 0001, then jump along the m path, jump from the exception handling state to the inter-frame filling state;

n - jump from exception handling state to idle state if the buffer data valid register is low;

o- If an error is found, jump from the idle state to the exception handling state;

p- If it is transparent transmission mode, and the buffer data valid register is high, jump directly from the exception handling state to the sending data state;

If the above jump conditions are not met, the state machine defaults to keep the state unchanged.

Due to the 8-bit parallel processing, the design of the zero-insertion function is quite different from serial processing:

The zero insertion method is:

For the current 8bit data to be sent (new_data), calculate the number of 1s from the lowest bit up (cur_count1_low) and the number of 1s from the highest bit down (cur_count1_high), and save the cur_count1_high as Count the number of consecutive 1s from the highest bit down (last_count1_high);

Make continuous 1 counter count1=last_count1_high, judge whether it is 1 from the lowest bit of data (new_data[0]) to the highest bit of data (new_data[7]), if it is 1, add 1 to the continuous 1 counter, and judge whether the continuous 1 counter is It is equal to 5, if it is equal to 5, insert a 0 after the bit, and reset the continuous 1 counter to 0.

The implementation method of zero insertion in the above state machine can be realized by using a for loop statement or a case statement in a hardware description language (such as verilogHDL, VHDL language), which only needs to occupy one clock cycle. The circuit area designed with the for loop statement is smaller, and the circuit designed with the case statement is faster.

Since the realization of other functions is relatively simple and can be realized by conventional technical means, it will not be elaborated here.

The new high-speed HDLC protocol module can be realized by using the high-speed data link control protocol sending processing module and the data processing method of the invention. And it can be assembled into a serial communication controller chip structure as shown in Figure 2, so that the performance of the entire chip is improved, and the chip area is also reduced at the same time, making the cost lower. Since the HDLC protocol processing module occupies a small chip area, it can also be easily implemented with a programmable logic device (such as FPGA) and applied to any product that requires HDLC protocol processing, which greatly improves the product development speed and effectively shortens the Development cycle.

Claims (10)

1. A high-speed data link control protocol transmission processing circuit module is characterized in that it is composed of a port arbitration circuit module, a high-speed data link control protocol processor circuit module and a state memory circuit module for sending; wherein, the The input end of said port arbitration circuit module is connected with N ports, the input end of said sending high-speed data link control protocol processor is respectively connected with the output end of this port arbitration module and the advanced The output end of the first-out buffer circuit is connected, and at the same time, it is bidirectionally connected with the state memory module, and the output end of the sending high-speed data link control protocol processor is connected with N ports. 2. the high-speed data link control protocol sending processing module as claimed in claim 1, is characterized in that, said sending high-speed data link control protocol processor comprises a two-level data buffer register and a secondary data buffer register. Level register cache circuit structure. 3. A data processing method for a high-speed data link control protocol sending processing module, characterized in that, comprising the following steps: 3-1) The port arbitration module receives the data request signals of N ports, transmits the request signals of the ports to the high-speed data link control protocol processor in sequence according to the priority level, and provides arbitration for the shared data processing pipeline of the N ports; 3-2) The sending high-speed data link control protocol processor reads unprocessed data from the first-in-first-out buffer circuit used to store the data to be sent in each channel, and reads the state data of the high-speed data link control channel to which the data belongs from The state memory module reads out, performs pipeline processing on its data, and sends the processed data to the corresponding port; 3-3) Write the new state data of the high-speed data link control channel back to the state memory circuit module. 4. The data processing method according to claim 3, wherein said method of providing arbitration to the N ports shared data processing pipeline specifically comprises the following steps: 4-1) The port number of the port with the highest data rate among the N ports is set to 0, the port number of the port with the second highest data rate is set to 1, and so on, the smaller the port number, the higher the priority during arbitration; 4-2) When multiple ports request data at the same time, the data of the port with the lowest port number is transmitted first. 5. The data processing method according to claim 3, wherein said sending high-speed data link control protocol processor processes data, specifically comprising the following steps: 5-1) The said sending high-speed data link control protocol processor puts the data read from the first-in-first-out buffer circuit used to store the data to be sent in each channel into the first-level data buffer register, and the second-level data The buffer register fetches data from the primary data buffer register; 5-2) While performing pipeline processing on the data in the second-level data buffer register, the first-level data buffer register can read subsequent data from the first-in first-out buffer. 6. The data processing method according to claim 5, characterized in that, said sending high-speed data link control protocol processor performs pipeline processing on data, specifically comprising the following steps: 6-1) First check whether the port arbitration module has channel application data, and if there is an application, start the processing pipeline; 6-2) If there is no application, the processing pipeline is idle. 7. The data processing method as claimed in claim 6, characterized in that said pipeline processing of data adopts three-stage pipeline processing, and each stage of pipeline completes corresponding work, and sends the data to the next stage with clock latch. The first level continues to process, so that each clock can process an 8-bit parallel data, and the work of the pipeline at all levels is performed in parallel to process the data of 3 channels at the same time. 8. The data processing method according to claim 7, wherein the method for processing data by said three-stage pipeline specifically comprises the following steps: first level 8-1-1) If there is an application for the port, the channel number of the applied data, the port where it is located, the working mode, and the flow control indication signal are latched, 8-1-2) Send a read enable signal to the state memory circuit module; second level 8-2-1) latching the state data read from the state memory circuit module, 8-2-2) For the read data to be sent, if it is currently in the data processing state or the frame verification state, then detect that 5 bits in the data are consecutively 1, perform zero insertion, and obtain the zero-filled data , 8-2-3) Merge the data to be sent this time with the remaining data last time to obtain the total data to be sent, 8-2-4) Carry out the jump of sending processing state machine according to status bit information, 8-2-5) Obtain new data to be sent according to the state of the sending processing state machine, 8-2-6) If the data buffer register has been sent to the data buffer register, then request new data from the first-in first-out buffer; third level 8-3-1) Send the data to be sent to the corresponding port, 8-3-2) If the sending processing state machine is in the sending data state, perform frame check calculation on the currently prepared data, 8-3-3) If the data buffer register is taken empty and the data in the buffer register is valid, then the data in the buffer register is sent to the data buffer register, and the bit sequence selection function is completed simultaneously, 8-3-4) If the first stage has sent the requested data to the FIFO buffer, write the new data requested from the FIFO buffer into the buffer register; if the data in the buffer register is sent out, then clear it buffer register, otherwise the buffer register is unchanged, 8-3-5) Send the write enable information, and write the new state bit into the state memory circuit module. 9. The data processing method as claimed in claim 8, characterized in that, the process of using said transmission processing state machine to control the transmission of the high-speed data link control protocol, the state of the transmission processing state machine includes: idle state, inter-frame Filling, exception handling, inserting frame header, sending data, frame checking and frame tail insertion; When no line error is found, the conditions for each state jump include: The send processing state machine is in an idle state when reset; a- If the buffer data valid register is high and it is in non-transparent mode, if the interframe fill selection bit is 0000 or 0001, and the flow control register is high, jump from the idle state to the frame header insertion state; b- If the buffer data valid register is high, and it is non-transparent mode, and when the flow control register is high, if the inter-frame filling selection bit is not 0000 or 0001, jump from the idle state to the inter-frame filling state; c-Unconditionally jump from the frame header insertion state to the sending data state; d- If the frame data is sent, when working in the non-transparent mode and the flow control is turned on, when the frame check is selected as CRC16 or CRC32, it will jump from the sending data state to the frame checking state; e- If the frame data is sent and the flow control is turned on, and the frame check selection is not CRC32 or CRC16, jump from the state of sending data to the state of inserting the end of the frame; g-If the frame check is selected as CRC16, then jump along the g path when the frame check send byte count is 2; if the frame check is selected as CRC32, then when the frame check send byte count is 4, jump from The frame check state jumps to the frame end insertion state; h- If the buffer data valid register is high, and the inter-frame filling selection bit is 0000, at this time, the frame identifiers of adjacent frames are multiplexed, and the flow control is turned on, then jump directly from the end-of-frame insertion state to the sending data state, at this time Continuous data frames share frame flags; i- If the buffer data valid register is high, and the inter-frame filling selection bit is 0001, jump from the frame end insertion state to the frame head insertion state; j- If the buffer data valid register is high, and the inter-frame fill selection bit is not 0000 or 0001, then jump from the end-of-frame insertion state to the inter-frame fill state; k - If the buffer data valid register is low, or the flow control register is off, jump from the end-of-frame insertion state to the idle state; r- If the inter-frame filling has been sent, jump from the inter-frame filling state to the frame header insertion state; When a line error is found, if the flow control is closed or the frame stop flag is required to be sent all the time when an error occurs, the sending processing state machine is always in the abnormal processing state, otherwise the transition conditions are as follows: f- If the buffer data valid register is low and the data frame is not over, jump from the sending data state to the exception handling state; l- If the buffer data valid register is high, and the inter-frame filling selection bit is 0000 or 0001, then jump from the exception handling state to the frame header insertion state; m-If the buffer data valid register is high, and the inter-frame filling selection bit is not 0000 or 0001, jump from the exception handling state to the inter-frame filling state; n - jump from exception handling state to idle state if the buffer data valid register is low; o- If an error is found, jump from the idle state to the exception handling state; p- If it is transparent transmission mode, and the buffer data valid register is high, jump directly from the exception handling state to the sending data state; If the jump condition is not satisfied, the sending processing state machine will keep the state unchanged by default. 10. The data processing method according to claim 9, characterized in that said zero insertion specifically comprises the following steps: 10-1) For the current data to be sent, calculate the number of bits that are continuously 1 from the lowest bit upwards and the number of bits that are 1 continuous from the highest bit downwards. After the data is processed, it will move from the highest bit to The number of bits whose lower digits are 1 consecutively is saved as the number of bits whose digits are 1 consecutively from the highest bit to the last; 10-2) Let the value of the 1-connection counter be the number of bits that have been continuously counted as 1 from the highest bit to the bottom of the saved last time, and judge whether it is 1 from the lowest bit of the data to the highest bit of the data in turn, and if it is 1, then connect 1 Add 1 to the counter, and judge whether the continuous 1 counter is equal to 5. If it is found that the continuous 1 counter is equal to 5 in a certain bit, a 0 is inserted after the bit, and the continuous 1 counter is reset to 0.

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