CN1292463C - Eutectic bonding method for back side of semiconductor chip - Google Patents

Abstract

The invention relates to a method for pasting eutectic welding on the back of a semiconductor chip, which belongs to the technical field of semiconductor device manufacturing technology. In the prior art, the metal layer vapor-deposited on the back of the chip silicon substrate is either a gold-based structure or a silver-based structure, and the material cost is relatively high; the metal layer often adopts a four-layer structure. In some solutions, the A certain layer or several layers also use a mixed layer or an alloy layer, which increases the manufacturing cost to a certain extent. The present invention determines the metal layer to be a three-layer structure, all of which are single-layer layers, which are Cr, Ni and Sn in sequence from the inside to the outside, thereby overcoming the disadvantages of the prior art. The invention can be applied to the field of semiconductor device manufacturing.

Description

Eutectic bonding method for back side of semiconductor chip

Technical field

The invention belongs to the technical field of semiconductor device manufacturing technology, and furthermore relates to a chip bonding method in the semiconductor device packaging technology.

Background technique

In the field of chip bonding technology in the existing semiconductor device packaging process, compared with metal solder bonding and conductive adhesive bonding methods, the eutectic solder bonding method has the advantages of reliable bonding, low thermal resistance, low pressure drop and no pollution to chips. . The currently used automatic packaging equipment basically adopts the eutectic bonding method, especially for small packaging forms such as small chip TO-92. As shown in Figure 1, the eutectic bonding method is to vapor-deposit a metal layer 2 on the back of the chip silicon substrate 1. After the metal layer 2 is in pressure contact with the surface coating of the frame 3, bonding occurs on the contact surface at a certain temperature. Formation of eutectics enables eutectic solder paste. The structure of the metal layer 2 is the main content of the eutectic welding paste method, and there are four known technologies that are closer to the present invention in this respect,

1. The Chinese patent application with application number 02114199.1 discloses a technical solution. In this technical solution, the metal layer 2 is an AuAs mixed layer, as shown in FIG. 2 .

2. In the currently widely used eutectic bonding process, the metal layer 2 can adopt a two-layer structure of AuAs+Au from the inside to the outside, as shown in Figure 3, wherein the thickness of the AuAs layer is several hundred angstroms (A). , and the Au layer is 1-2 μm thick, and the Au layer is bonded to the surface plating layer of the frame 3 .

3. In the currently widely used eutectic bonding process, there is another scheme shown in Figure 4. The metal layer 2 adopts a four-layer structure of V+Ni+AuGeSb+Au from the inside to the outside, and the V layer is 300 thick. ～1200 Ȧ, Ni layer thickness 3000 Ȧ, wherein AuGeSb layer is alloy layer, atomic ratio (at%) is: Au 87.8%, Ge 12.0%, Sb 0.2%, thickness 1.4～2.0 μm, Au layer thickness 1000 Ȧ.

4. In some imported semiconductor devices, such a technical solution is also adopted. The metal layer 2 adopts a four-layer structure of Cr+Ag+AgSn+SnAl from the inside to the outside, as shown in Figure 5, and the Cr layer is The ohmic contact layer has a thickness of about 2000 Ȧ; the Ag layer is a barrier layer and has a thickness of about 7000 Ȧ; the AgSn layer is a kind of alloy layer, as an intermediate transition layer, its thickness is about 2700 Ȧ, and the atomic ratio (at%) is: Ag 66%, Sn 34%; SnAl layer is also an alloy layer, as a surface layer, the thickness is about 2μm, the atomic ratio (at%) is: Sn 95%, Al 5%.

Contents of Invention

The first three known technologies are all metal-based structures, and therefore, their material costs are relatively high. Taking the second known technology as an example, for a chip with a diameter of 4 inches, as far as the current situation is concerned, the material cost of the metal layer is more than 100 yuan/chip (RMB, the same below). The corresponding material cost of the known technique 3 is also between 70-80 yuan/piece. Although the known technology 4 is a silver-based structure, its corresponding material cost is also more than 40 yuan/piece. In addition, the known technologies 3 and 4 both have a four-layer structure, that is to say, four times of vapor deposition are required when making the metal layer 2 , which increases the process and increases the manufacturing cost. Furthermore, all known technologies contain a mixed layer or an alloy layer. Compared with a simple layer, the manufacturing cost is bound to increase. Products such as energy-saving lamps require that the discrete semiconductor devices used should firstly be inexpensive, secondly have better electrical performance, and thirdly be reliable in operation. Therefore, in order to reduce the cost in the packaging process of the semiconductor device and at the same time ensure that the device has good electrical performance and high reliability, we invented the eutectic bonding method for the back of the semiconductor chip of the present invention.

The present invention is realized in this way, as shown in Fig. 6, Cr, Ni, Sn are successively vapor-deposited from the inside to the outside on the back side of the silicon substrate 1 of the semiconductor chip to form a metal layer 2 with a three-layer structure, wherein the thickness of the Cr layer is 300 ∼1000 Ȧ, the thickness of the Ni layer is 3000∼5000 Ȧ, and the thickness of the Sn layer is 1.5∼2.5 μm. The Sn layer is bonded to the plating layer on the surface of the frame 3 to form a eutectic alloy.

Adopting the metal layer structure of the present invention to carry out eutectic solder paste, because neither gold (Au) nor silver (Ag) is used on the materials, the cost of materials is greatly reduced, and the cost of materials is also reduced by vapor deposition on a 4-inch chip. Just below 10 yuan/piece, about one-tenth of the known technology two, about one-fifth of the known technology four. In addition, the present invention only has a three-layer structure, and all of them are monolayers, so that the manufacturing cost is also reduced. At the same time, as a eutectic bonding method, it also has advantages that the other two chip bonding methods do not have. For example, on the technical index of thermal resistance, under the same test conditions, the device packaged by the method of the present invention, Its thermal resistance is only 50% of the thermal resistance of devices glued with silver paste, and the pressure drop can be reduced by more than 25%. Under the same application conditions, the shell temperature of the device manufactured by the method of the present invention is significantly lower than that of the device glued by silver paste. In terms of reliability, the bonding method as eutectic soldering is of course much higher than the other two chip bonding methods.

Description of drawings

Figure 1 is a schematic diagram of the eutectic solder paste method. Fig. 2 to Fig. 5 are sequentially schematic diagrams of known techniques 1 to 4 eutectic welding pasting methods. Fig. 6 is a schematic diagram of the eutectic bonding method of the present invention.

Detailed ways

As shown in FIG. 6, the thicknesses of the three-layer structure of the metal layer 2 are respectively determined as follows: 500 Ȧ for the Cr layer, 5000 Ȧ for the Ni layer, and 2.0 μm for the Sn layer. Wherein, the Cr layer can be replaced by a V layer or a Ti layer. When evaporating the Sn layer, the evaporation rate is controlled below 12 Ȧ/min, and the other two layers are treated according to the conventional process. The Sn layer can be replaced by Sn-based alloy layers such as SnSb, SnSbAg, SnAl, SnAu, etc. The so-called Sn-based means that the Sn content is above 80% (wt%). The melting point of the Sn layer is 230°C, the sticking temperature can be determined in the range of 280-380°C, and the silicon retention rate can exceed 80%. In this temperature range, if the paste temperature is set higher, the thermal resistance of the device can generally be lower. For example, when the paste temperature is 370°C, the thermal resistance is 100.9mV, and when the paste temperature is 350°C, the thermal resistance is 101.4mV. . The temperature of the frame 3 during pressure welding is 250°C. Properly lowering the temperature of the frame 3 can increase the pressure welding strength, but it cannot be lower than 230°C. During the eutectic bonding process, the Sn layer and the surface coating of the frame 3 form a eutectic, for example, when the weight ratio (wt%) of the two metals determined by the layer thickness is: Sn 96.5%, Ag 3.5%, 221 ° C The temperature is their eutectic temperature. In order to prevent the oxidation of the Sn layer, a thin layer of Ag or Au can be evaporated on the Sn layer, the thickness of which is measured in angstroms (A), so there is no significant increase in material cost. For example, according to the Ag-Sn, Au-Sn phase diagram and the thickness of the Sn layer, the thickness of the Ag layer can be calculated as 487 Ȧ, and the thickness of the Au layer can be 786 Ȧ, 1500 Ȧ or 4800 Ȧ.

Claims (10)

1, a kind of semiconductor chip back side eutectic weldering method of attaching, in chip silicon substrate (1) back side evaporated metal layer (2), at a certain temperature, make metal level (2) and framework (3) surface be subjected to press contacts, form eutectic at contact-making surface generation bonding, realize eutectic weldering stickup, it is characterized in that, at semiconductor chip silicon substrate (1) back side from the lining outside evaporation Cr successively, Ni, Sn, formation has the metal level (2) of three-decker, and wherein the Cr layer thickness is 300～1000 , and the Ni layer thickness is 3000～5000 , the Sn layer thickness is 1.5～2.5 μ m, and the coating on this Sn layer and framework (3) surface forms eutectic.

2, eutectic weldering method of attaching according to claim 1 is characterized in that the Cr layer is replaced by V layer, Ti layer.

3, eutectic weldering method of attaching according to claim 1 is characterized in that, the Sn layer is replaced by SnSb, SnSbAg, SnAl, SnAu alloy-layer based on Sn, and so-called is that the master is meant that its percentage by weight of Sn content is more than 80% with Sn.

4, eutectic according to claim 1 weldering method of attaching is characterized in that, the evaporation rate during evaporation Sn layer is controlled at 12 /below the min.

5, eutectic weldering method of attaching according to claim 1 is characterized in that sticking temperature is determined in 280～380 ℃ of scopes.

6, eutectic weldering method of attaching according to claim 1 is characterized in that the temperature of framework during pressure welding (3) is 230～250 ℃.

7, eutectic weldering method of attaching according to claim 1 is characterized in that, in order to prevent the oxidation of Sn layer, evaporation skim Ag on the Sn layer.

8, eutectic weldering method of attaching according to claim 1 is characterized in that, in order to prevent the oxidation of Sn layer, evaporation skim Au on the Sn layer.

9, eutectic weldering method of attaching according to claim 7 is characterized in that the thickness of this Ag layer is 487 .

10, eutectic weldering method of attaching according to claim 8 is characterized in that the thickness of this Au layer is 786 , 1500  or 4800 .

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