CN1292360C - A device and method for realizing automatic reading and writing of internal integrated circuit equipment - Google Patents

Abstract

The invention discloses a device and method for realizing automatic reading and writing of I2C equipment. The device is composed of an instruction generation module realized by hardware and a read and write operation execution module. The instruction generation module is respectively connected with the active device and the read and write operation execution module through an asynchronous access bus. , the read and write operation execution module is connected to the I2C device through the I2C bus. When reading and writing, the active device provides the start signal, the read/write signal, the device address of the I2C device, the register address and the data to be written into the register, and the command generation module automatically generates The instructions required to access the I2C device are sent to the read and write operation execution module in sequence, and the read and write operation execution module generates the signal timing required to access the I2C device according to the I2C bus protocol, and executes the read and write operations on the I2C device. The device of the present invention also Return command execution status to active device. The invention can simplify the software operation when accessing the I2C device and save CPU time.

Description

A device and method for realizing automatic reading and writing of internal integrated circuit equipment

technical field

The present invention relates to a device and method for reading and writing integrated circuit equipment, in particular to realizing automatic reading of I2C (inter-integrated circuit internal integrated circuit, a standard interface circuit, invented by PHILIPS) equipment in the field of data communication. or written apparatus and methods.

Background technique

In many cases, the electronic equipment system or CPU application system has a low-speed asynchronous access bus interface, but there is no I2C bus (including two signal lines of SDA and SCL, which respectively represent the data signal line and clock signal line of the I2C bus. The following I2C The bus refers to the two signal lines) interface, and at this time, the I2C device needs to be read and written. This requires conversion of the low-speed asynchronous access bus and the I2C interface bus.

Existing methods for realizing low-speed asynchronous access bus and I2C interface bus conversion are generally more complicated. On the WWW.FPGA.COM.CN website, a newest I2C bus control IP CORE (integrated circuit logic core), is to adopt this more complex method, if the active device (such as CPU) wants to access an I2C device, the CPU is required to execute step by step according to the I2C bus protocol.

For example, if the CPU wants to read an I2C device, the steps to be performed are:

1) The CPU writes the I2C device address (DEVICE ADDRESS) to the data register, and sets the write flag;

2) The CPU reads the status register to determine whether the I2C bus is busy, and if not, execute the next step;

3) The CPU writes the control register, sends "START" and sends the I2C device address (DEVICE ADDRESS);

4) The CPU reads the status register to determine whether the transmission is complete and receives a response (ACK) from the slave device. If a response is received, proceed to the next step;

5) The CPU writes the register address (WORD ADDRESS) to be accessed to the I2C device to the data register;

6) The CPU writes the control register and sends out the register address of the I2C device;

7) The CPU reads the status register, judges whether the sending is completed and receives a response (ACK) from the slave device. If a response is received, proceed to the next step;

8) The CPU writes the control register and sends "end" (STOP);

9) CPU delay (because some I2C devices require additional delay, such as AT24C04 requires a 10 millisecond delay between the last "end" and the next "start");

10) The CPU writes the I2C device address (DEVICE ADDRESS) to the data register, and sets the read flag;

11) The CPU writes the control register, sends "START" and sends the I2C device address (DEVICE ADDRESS);

12) The CPU reads the status register to determine whether the transmission is complete and receives a response (ACK) from the slave device. If a response is received, proceed to the next step;

13) The CPU sets the control register so that the logic is in the receiving state;

14) Judging the status register, whether the data reception is completed. When done, go to the next step

15) The CPU reads the data register to obtain the data to be read.

It can be seen that each step is inseparable from the operation and judgment of the CPU. Not only is the program complicated, but the CPU spends a lot of time waiting for the response of the slow device.

Since the I2C device is a relatively slow device, accessing such a slow device consumes more CPU time; if you use software to operate step by step, including sending START signal, sending data, detecting the response signal of the SLAVE device (slave device), and then sending STOP Signal. Every step of operation requires an external processor to participate in sending instructions or judgments, etc., which will waste a large number of operating cycles of the CPU. For systems with high CPU processing performance requirements, this is very uneconomical and undesirable. In addition, if the software is used to guide the operation and access the I2C device, the user is required to understand the I2C bus protocol very well, and must complete the operation step by step according to the I2C bus protocol, including the accurate calculation of the delay time.

Contents of the invention

The technical problem to be solved by the present invention is to overcome the defects of cumbersome operation and waste of CPU time in the prior art when accessing internal integrated circuit equipment, and provide a device and method for automatically reading and writing internal integrated circuit equipment.

The device for automatically reading and writing internal integrated circuit devices of the present invention includes an instruction generation module and a read-write operation execution module realized by hardware, and the instruction generation module communicates with the active device and the read-write operation execution module respectively through an asynchronous access bus connected, the read and write operation execution module is connected to the internal integrated circuit device through the internal integrated circuit bus, wherein:

The instruction generation module is used to receive the start signal provided by the active device, the read/write signal, the device address of the internal integrated circuit device, the register address and the data to be written into the register, and automatically generate the required instruction for accessing the internal integrated circuit device. The instructions are sent to the read and write operation execution module in sequence, and the execution status of the instructions and the data read from the internal integrated circuit device are returned to the active device;

The read and write operation execution module is used to generate the signal timing required to access the internal integrated circuit device according to the instructions of the instruction generation module according to the internal integrated circuit bus protocol, execute the read and write operations on the internal integrated circuit device, and send to all The instruction generation module returns the execution status of the instruction.

The above-mentioned device may have the following characteristics: when the instruction generation module detects that the active device is about to write an internal integrated circuit device, it sequentially sends a start instruction, a device address instruction and a write instruction, a register address instruction, a data instruction, and a stop instruction.

The above-mentioned device may have the following characteristics: when the instruction generation module detects that the active device wants to read an internal integrated circuit device, it sequentially sends a start instruction, a device address instruction and a write instruction, a register address instruction, a stop instruction, a start instruction, and a device address Command and read instructions, receive data instructions and stop instructions.

The above-mentioned device may have the following characteristics: the instruction generation module further includes:

Command control register, the value of the corresponding control bit is set by the start signal and the read/write signal of the active device, and the internal integrated circuit device is read or written, and an error flag is set when the execution fails;

A device address register for storing the device address of the internal integrated circuit device to be accessed;

A register address register for storing the address of the register of the internal integrated circuit device to be accessed;

Write to the data register, used to store the data to be written;

read data register, used to store the data to be read;

The frequency division setting register is used to set the multiple relationship between the frequency of the SDA/SCL signal sent and the frequency of the input CLK;

The master device selects the above-mentioned registers through the address signal of the asynchronous bus.

The above-mentioned device may have the following characteristics: the command generation module returns the execution status of the command to the active device by setting an interrupt signal after a read or write operation is completed, or setting the corresponding bit Automatic clearing, or a combination of the above two methods.

The above-mentioned device may have the following characteristics: the read-write operation execution module includes a command register, a receiving data register, a sending data register, a clock generating unit, a START generating unit, a STOP generating unit, a data sending unit and a data receiving unit, wherein:

The command register, the value of the corresponding control bit is set by the instruction of the instruction generation module, controls the startup of the START generation unit, the STOP generation unit, the data sending unit and the data receiving unit, and sets the corresponding bit after the operation is completed. Clear;

The receiving data register is used for buffering the data received by the data receiving unit;

The sending data register is used for buffering the data to be sent by the data sending unit;

A clock generating unit is used to generate clocks required by each module in the read and write operation execution module;

The START generating unit is used to generate the START timing specified in the inter-integrated circuit bus protocol;

The STOP generating unit is used to generate the STOP timing specified in the internal integrated circuit bus protocol;

The data sending unit is used to send the data in the sending data register to the internal integrated circuit bus according to the timing of SDA and SCL stipulated in the internal integrated circuit bus protocol;

The data receiving unit is used for receiving data on the internal integrated circuit bus according to the timing of SDA and SCL stipulated in the internal integrated circuit bus protocol.

The above-mentioned device may have the following characteristics: the asynchronous bus between the instruction generation module and the read and write operation execution module includes a reset signal, a clock signal, a write enable signal, a sending data register selection signal, a command register selection signal, a data bus input and An output signal, and a circuit of an error indication signal, the error indication signal is generated by the control bit of the command register, and is used to return the instruction execution status to the instruction generation module.

The method for realizing automatic writing of the internal integrated circuit device of the present invention is applied to a system in which the instruction generation module and the write operation execution module realized by the active device through hardware are connected to the internal integrated circuit bus, and the method includes the following steps:

(a) The address of the internal integrated circuit device to be accessed by the active device is written into the device address register of the instruction generation module;

(b) the active device writes the address of the internal integrated circuit device register to be accessed into the register address register of the instruction generating module;

(c) the active device writes the data to be written into the write data register of the instruction generating module;

(d) the active device sets the corresponding BIT bit of the command control register in the instruction generation module to start the write operation;

(e) The instruction generation module automatically generates the instructions needed to write the internal integrated circuit device, and sends them to the write operation execution module in sequence;

(f) The write operation execution module generates the signal sequence for writing the internal integrated circuit device according to the instruction of the instruction generation module according to the internal integrated circuit bus protocol and completes the write operation, and returns the execution status of the instruction;

(g) the command generation module returns the execution status of the command to the active device;

(h) After the active device judges that the operation is completed correctly, it ends a write operation.

In the above method, after step (h), if the next operation accesses the same internal integrated circuit device as the previous operation, then directly return to step (b), otherwise return to step (a).

In the above method, in the step (e), the instruction generating module sequentially sends a start instruction, a device address instruction and a write instruction, a register address instruction, a data instruction and a stop instruction.

In the above method, in the step (h), the active device reports through the interrupt of the instruction generation module, or detects the value of the corresponding control bit of the instruction generation module to confirm whether the operation is completed correctly; by detecting the The command generates the value of the error indication bit of the module to determine whether to perform error handling operations.

The method for automatically reading an internal integrated circuit device of the present invention is applied to a system in which an active device realizes an instruction generation module and a read operation execution module connected to the internal integrated circuit bus through hardware, and the method includes the following steps:

(a) The address of the internal integrated circuit device to be accessed by the active device is written into the device address register of the instruction generation module;

(b) the active device writes the address of the internal integrated circuit device register to be accessed into the register address register of the instruction generating module;

(c) the active device sets the corresponding BIT bit of the command control register in the instruction generation module to start a read operation;

(d) The instruction generation module automatically generates the instructions needed to read the internal integrated circuit device, and sends them to the read operation execution module in sequence;

(e) The read operation execution module generates the signal sequence for reading the internal integrated circuit device according to the instruction of the instruction generation module according to the internal integrated circuit bus protocol and completes the read operation, and returns the execution status of the instruction;

(f) The instruction generating module returns the read data and instruction execution status to the active device;

(g) After the active device judges that the operation is completed correctly, it reads data from the instruction generation module and ends a read operation.

In the above method, after step (g), if the next operation accesses the same internal integrated circuit device as the previous operation, then directly return to step (b), otherwise return to step (a).

In the above method, in the step (d), the instruction generating module sequentially sends a start instruction, a device address instruction and a write instruction, a register address instruction, a stop instruction, a start instruction, a device address instruction and a read instruction, a receive data instruction, and stop command.

In the above method, in the step (g), the active device reports through the interrupt of the instruction generation module, or detects the value of the corresponding control bit of the instruction generation module to confirm whether the operation is completed correctly; by detecting the The command generates the value of the error indication bit of the module to determine whether to perform error handling operations.

As can be seen from the above, the instruction generation module implemented by hardware in the present invention generates some instructions needed to access the internal integrated circuit device to replace some work of the software, thereby completing the tedious operation of simplified software; instructions, and follow the internal integrated circuit bus protocol to complete the specific operation of accessing the internal integrated circuit device, so that the device of the present invention is automatically compatible with the internal integrated circuit bus protocol. Thereby changing the phenomenon that the access to the internal integrated circuit device relies too much on the CPU, freeing up more time for the CPU to do other more important work. At the same time, the user does not need to understand the cumbersome internal integrated circuit bus protocol, which simplifies the workload of the software.

Description of drawings

Fig. 1 is the structural block diagram of the device of automatic reading and writing I2C equipment of the embodiment of the present invention;

Fig. 2 and Fig. 3 are respectively the asynchronous access bus write timing diagram and read timing diagram between the active device and the instruction generation module of the embodiment of the present invention;

FIG. 4A and FIG. 4B are flow charts of an active device accessing the apparatus of the present invention according to an embodiment of the present invention;

Fig. 5 is the flow chart of the generation instruction of the instruction generation module of the embodiment of the present invention;

Fig. 6 is a schematic diagram of the write sequence of the instruction generation module of the embodiment of the present invention;

Fig. 7 is a schematic diagram of the read sequence of the instruction generation module according to the embodiment of the present invention;

Fig. 8 is a transmission timing diagram of the I2C bus.

Detailed ways

The device for automatically reading and writing I2C devices in the embodiment of the present invention is shown in Figure 1. The device is composed of a command generation module 1 and a read and write operation execution module 2, and is implemented by FPGA or CPLD. The command generation module 1 is connected to the active device 4 and the read and write operation execution module 2 respectively through the asynchronous access bus, and the read and write operation execution module 2 is connected to the I2C device 3 through the I2C bus. in:

① Instruction generation module 1, implemented by hardware, is used to receive the start signal provided by the active device, the read/write signal and the device address of the I2C device, the register address and the data to be written into the register, and automatically generate the data required for accessing the I2C device. The instructions are sent to the read and write operation execution module according to certain conditions and sequence, and the execution status of the instructions and the data read from the I2C device are returned to the active device, and whether there is a response from the I2C device can be judged.

This module includes command control register 11, device address register 12, register address register 13, write data register 14, read data register 15 and frequency division setting register 16, among which:

The command control register 11 is used to start reading or writing to the I2C device. It is a 3-bit W/R register. The functions of each bit are as follows:

BIT0=1 write I2C device enable, when the write operation is completed, the bit is automatically cleared;

BIT1=1 read I2C device enable, when the read operation is completed, the bit is automatically cleared;

BIT2＝1 During the execution of the read or write operation, an error occurs, indicating that the read or write operation has not been completed correctly;

BIT2=0 is normal.

Device address register 12, used to store the device address of the I2C device to be accessed, is a 7-bit W/R register, corresponding to DEVICE ADDRESS among Fig. 6;

Register address register 13, used to store the address of the register to be accessed by the I2C device, is an 8-bit W/R register, corresponding to WORD ADDRESS in Figure 6;

Write data register 14, be used for storing the data to be written, be 8 W/R registers;

The read data register 15 is used to store the read data and is an 8-bit R register;

The frequency division setting register 16 is used to set the multiple relationship between the frequency of the SDA/SCL signal sent and the frequency of the input CLK. It is an 8-bit W/R register, and the minimum value of CLK cannot be lower than 10MHz.

The calculation formula is:

The addresses of these six registers are: 0, 1, 2, 3, 4, 5.

This module is an interface module between the device of the present invention and active equipment (such as CPU). The active device is connected to the module through a common asynchronous access bus. The signals of the asynchronous access bus can be seen in Figure 1. Table 1 shows the description of the asynchronous interface signals.

Table 1 signal name explain Data bus Data Bus. (I/O) CLK Clock, the clock signal necessary for the normal operation of the present invention. In CS Chip select signal, active low. In WR Read and write signals, low for writing, high for reading. In Reset Reset signal, active low. Must be high for normal operation. In INT Interrupt output, 0 means that the read and write operation is completed, 1 is not completed or there is no read and write operation, and the interrupt can be cleared by reading the register E of the present invention. out A[2:0] Address bus, to access a certain register of the instruction generating module, the bus must have the correct address indication. In

Fig. 2, Fig. 3 have shown the transmission sequence of above-mentioned part asynchronous interface signal when writing and reading operation, and the bus between active equipment 4 in the figure and instruction generation module can be the local bus (local equipment bus, BOOT; access bus such as FLASH), Power PC (Power PCCPU series of motorola), single-chip microcomputer (51 series), ISA (Industry Standard Architecture industry standard structure) bus of interl CPU, device bus of MIPS CPU, etc. All the asynchronous access buses of 3 timings can be connected with the present invention, and the present invention can be used directly. In the picture:

The time length of Tw-we can be indefinite, as long as there is a rising edge of CLK in the valid write cycle (CS=0 and wr=0, data bus and A[2:0] are valid);

The time length of Tw-rd can be variable and can be greater than 10 nanoseconds;

Twr-w and Tcs-w can be equal or not;

The relationship between Twr-r and Tcs-r must satisfy Twr-r≥Tcs-r.

The meanings of the character fields are as follows:

Tw-we active device accesses the access cycle time of the write operation of the present invention.

The Twr-w active device accesses the effective time of the write signal in the access period of the write operation of the present invention.

The Tcs-w active device accesses the effective time of the chip selection signal in the access period of the write operation of the present invention.

The Tw-rd active device accesses the access cycle time of the read operation of the present invention.

The Twr-r active device accesses the invalid time of the write signal in the access period of the read operation of the present invention.

The Tcs-r active device accesses the effective time of the chip selection signal in the access period of the read operation of the present invention.

② The read and write operation execution module 2 is used to generate the instructions of the module 1 according to the instructions, follow the I2C bus protocol to generate the signal timing required for accessing the I2C devices, execute the read and write operations on the I2C devices, and return to the instruction generation module The execution of the order. This module contains the following parts:

The command register 21 is used to control the startup of the START generating module 25 , the STOP generating unit 26 , the data sending unit 27 and the data receiving unit 28 . It is controlled by the instruction generation module 1, and the instruction generation module 1 achieves the purpose of controlling the work of the read and write operation execution module by setting different bits of the register, the START generation module 25, the STOP generation unit 26, the data sending unit 27 and the data The four modules of the receiving unit 28 cannot work simultaneously. In this example:

BIT0=1 START generation unit 25 is enabled, and the START generation unit sends the start sequence (start condition) in Figure 8 to the I2C bus. After the operation is completed, the BIT position is cleared to 0;

BIT1=1 send data module 27 work enable, when send data module all send out the data in send data register 23, and after receiving the response signal from equipment, this BIT position is cleared 0;

BIT2=1 receiving data module 28 is enabled, when the receiving data module receives all the 8-bit data sent by I2C from the device, and sends the response signal ACK, the BIT bit is automatically cleared to 0;

BIT3=1STOP generation unit 26 work enables, and STOP generation module sends the end sequence (stop condition) among Fig. 8 on the I2C bus, and after the operation is completed, this BIT position is cleared to 0.

The receiving data register 22 is used for buffering the data received by the data receiving unit 28;

send data register 23, cache the data to be sent by data sending unit 27;

A clock generating unit 24, configured to generate the clocks required by each module in the read and write operation execution module;

START generation unit 25 is used to generate the START timing specified in the I2C bus protocol; (the start condition start condition in Fig. 8)

STOP generation unit 26 is used to generate the STOP timing specified in the I2C bus protocol; (stop condition termination condition among Fig. 8)

The data sending unit 27 is used to send the data in the sending data register 23 to the I2C bus according to the timing of SDA and SCL stipulated in the I2C bus protocol;

The data receiving unit 28 is configured to receive data on the I2C bus according to the timing of SDA and SCL stipulated in the I2C bus protocol.

Based on the above device, Fig. 4A and Fig. 4B are the flowcharts of the active device access instruction generation module device according to the embodiment of the present invention, wherein the process of writing operation is as shown in Fig. 4A, including the following steps:

Step 100, the active device setting instruction generates the device address register in the module, and writes the address of the I2C device to be accessed into the register;

Step 110, the active device setting command generates the register address register in the module, and writes the address of the I2C device register to be accessed into the register;

Step 120, write the data to be written into the register in the write data register in the active device setting instruction generation module;

Step 130, the active device sets the corresponding BIT bit to start the write operation in the command control register of the instruction generation module. In this embodiment, set BIT0=1 during the write operation;

Step 140, the active device waits for an interrupt to report (INT signal changes), or judges whether the BIT0 bit of the command control register becomes 0, if it becomes 0, then the operation is correctly completed, and the next operation can be carried out; if the command If there is an error indication in the error indication BIT bit of the control register, the operation is not completed correctly, and the active device will perform error handling operations, such as re-executing the previous operation or doing other processing; if the operation is not completed, then wait for the completion of the operation.

If the next operation accesses the same I2C device as the previous operation, then directly return to step 110; if not the same I2C device, then return to step 100.

It can be seen from the above that for a single I2C device, the active device only needs 4 steps to complete a write operation to the I2C device, and steps 100, 110 and 130 are necessary steps for setting and starting an access to the I2C device.

The flow of the read operation is shown in Figure 4B, including the following steps:

Step 200, write the address of the I2C device to be accessed into the device address register in the active device setting instruction generation module;

Step 210, write the address of the I2C device register to be accessed into the register address register in the active device setting instruction generating module;

Step 220, the active device sets the corresponding BIT bit that starts the read operation in the command control register in the instruction generation module. In this embodiment, set BIT1=1 during the read operation;

Step 230, the active device judges whether the operation is completed correctly in the same way as the write operation, if yes, execute the next step, otherwise continue to wait or perform error handling;

In step 240, the active device reads the instruction generating module to read the data register, obtains the desired result, and then proceeds to the next operation.

If the next operation accesses the same I2C device as the previous operation, then directly return to step 210; if not the same I2C device, then return to step 200.

It can be seen from the above that for a single I2C device, the active device only needs 3 steps to complete the read operation of the I2C device. Unlike the existing technology, the active device needs 15 steps of operation and judgment to complete the read operation of an I2C device.

Fig. 7 is the flowchart of instruction generation module work, comprises the following steps:

Step 300, the instruction generation module real-time monitors the value of the BIT0 and BIT1 bits of the command control register of this module, if BIT0=1, execute the write operation process of steps 310～360, BIT1=1, execute the read operation process below step 400, Otherwise, continue to detect;

Step 310, send the START command (the start sign of I2C bus, corresponding to the start condition in Figure 8) to the read and write operation execution module;

Step 320, sending DEVICE ADDRESS (I2C device address) and writing instructions to the read and write operation execution module;

Step 330, send WORD ADDRESS instruction (the register address of I2C equipment) to read and write operation execution module;

Step 340, sending data (DATA) to the read and write operation execution module;

Step 350, send a STOP instruction (the end sign of I2C bus, corresponding to the stop condition in Figure 8) to the read and write operation execution module;

Step 360, after all instructions are correctly completed, clear the BIT0=0 of the command control register, generate an interrupt and send the INT signal simultaneously, inform the active device that the write operation is completed, and end a write operation;

Step 400, sending a START command to the read and write operation execution module;

Step 410, send DEVICE ADDRESS and write instructions to the read and write operation execution module;

Step 420, send the WORD ADDRESS command to the read and write operation execution module;

Step 430, sending a STOP command to the read and write operation execution module;

Step 440, start a 10ms delay;

Step 450, sending a START instruction to the read and write operation execution module;

Step 460, sending DEVICE ADDRESS and read instructions to the read and write operation execution module;

Step 470, sending instructions to the read and write operation execution module, setting SDA as high impedance, and preparing to receive data from the I2C device;

Step 480, after the data is received, send a STOP instruction to the read and write operation execution module;

Step 490, after all the instructions are completed correctly, clear the BIT1=0 of the command control register, and at the same time generate an interrupt INT signal to inform the active device that the read operation is completed, and end a read operation.

In the above steps, after the command generation module sends a command to the read and write operation execution module, it starts time timing at the same time. Each command of this module is designed with a maximum time value of fault alarm. When the time counted reaches this value, it has not yet detected This operation is correctly carried out, then it is considered that there is a fault, terminate this read and write operation, set the fault indication bit (set the command control register BIT2 to 1), step 500, indicate that an error occurs, and inform the active device that the write operation is unsuccessful; If the read and write operation cannot be completed correctly, the read and write operation will be terminated, and the active device will be informed of the failure of this operation with the fault indicator bit, and the active device will decide how to proceed to the next step.

The judging method of whether the execution is completed correctly is: because the read and write operation execution module executes an instruction every time, the corresponding BIT bit of the command register of the module is cleared. And several control BIT bits of the command register are sent to the instruction generation module through the error signal (see Fig. 1), and the specific implementation is: error[3:0]=BIT[3:0], BIT[3:0] is the command The BIT bit of the register. Therefore, the command generating module can know whether the correct operation of this command is completed by detecting the value of error[x].

The timing of the above-mentioned command generation module in the write operation and read operation is shown in Figure 6 and Figure 7 respectively. When it is detected that the active device wants to write an I2C device, the command generation module will send START->send DEVICE in sequence according to the order of Figure 6 ADDRESS and write instruction->send WORDADDRESS->send data->send STOP; when detecting that the active device wants to read an I2C device, send START->send DEVICE ADDRESS and write instruction->send WORD ADDRESS- >Send STOP->Send START->Send DEVICEADDRESS and read instructions->Receive data->Send STOP.

In Fig. 7, except that the DATA part is sent by the I2C slave device (ie the I2C device in Fig. 1) and received by the present invention, other parts (except ACK) are all sent by the present invention. In the figure, MSB represents the high-order BIT of the byte, LSB represents the low-order BIT of the byte, and W/R is the read and write indicator, indicating whether to read or write the I2C device in this cycle, 0 for writing, 1 for reading. There is a place where it is necessary to judge the response from the device (for example: the read-write operation execution module of the present invention, after sending DEVICE ADDRESS and read-write indication R/W, will judge the ACK signal sent back by the I2C device, (the correct ACK signal should be It is a low level of 1 clock cycle 0) If the ACK signal is detected, the read and write operation execution module considers that the instruction has been executed correctly.) The read and write operation execution module automatically completes by detecting the ACK signal in Figure 6 and Figure 7 Yes, ACK is 0 means that the slave device has a response, and ACK is 1 means that the slave device has no response, which is equivalent to the ACK cycle in Figure 8.

The following describes the situation that the read and write operation execution module generates the instructions of the module according to the instructions, generates the signal timing required to access the I2C device according to the I2C bus protocol, and executes the read and write operations on the I2C device.

Figure 8 describes the transmission timing of the I2C bus. The I2C bus includes two signal lines, one is the data signal SDA, and the other is the clock signal SCL. Each data bit corresponds to a complete clock cycle. When the clock signal SCL is 1, the data SDA cannot change. If there is a change, it will be blocked. Think of it as a start (START, start condition in Figure 8) or end (STOP, stopcondition in Figure 8) flag. When SCL=1, the falling edge of SDA is "start"; when SCL=1, the rising edge of SDA is "end". The device occupying the I2C bus is the master device, and the accessed device is the slave device. Every time the master device transmits a byte (8BIT), the slave device should respond with a low level at the 9th CLOCK of SCL (the slave device pulls SDA low for one clock cycle) (ACK in Figure 8), if the master device If the device cannot detect this "response", the data transmission is unsuccessful. The data transmission sequence starts with the high bit (MSB) and ends with the low bit (LSB).

The read and write operation execution module of this embodiment needs to generate the required transmission timing of the I2C bus according to the instructions of the instruction generation module. As shown in FIG. 1 , the instruction generation module 1 and the read and write operation execution module 2 are connected through an asynchronous bus. The meaning of each signal is shown in Table 2:

Table 2 reset reset signal. clock Clock signal necessary for the proper functioning of the module by performing read and write operations. we Write enable signal, active low. When this signal is low, the data on the Data_i bus is valid. Data_i The data bus is input, and the instruction generation module sends the read and write operation execution module. Data_o The data bus output is sent to the command generation module by the read and write operation execution module. Txreg_cs Send data register select signal. Comd_cs Command register select signal. Error[3:0] The error indication signal is used to indicate whether an operation has been performed correctly.

The access control between the two modules can be completed through the above signals. For example, when the command generation module sends the DEVICE ADDRESS command, the WE and Txreg_cs signals are valid, and the device address in the device address register of the command generation module is written to the read and write operations through Data_i. The sending data register in the module, then, the command generation module sets the BIT1=1 of the command register of the read and write operation execution module through the Comd_cs signal, and the read and write operation execution module detects the BIT1=1 of the command register, and starts the work of the sending data module, Send the value of the send data register to the I2C bus. After completing this operation, clear the BIT1 of the command register, and the command generating module detects that the BIT1 of the command register of the read and write operation execution module returns to 0, knowing that the previous operation has been completed, and starts the next operation. The specific operations of other instructions are similar to this and will not be detailed here.

To sum up, since the instruction generation module and the read and write operation execution module are implemented by hardware, the entire I2C device access process basically does not involve the CPU. condition. Therefore, this method solves the excessive dependence on software for accessing I2C devices in the prior art.

Claims (15)

1, a kind of device of realizing automatic reading and writing internal integrated device electronics, it is characterized in that, comprise with hard-wired command generation module and read-write operation execution module, described command generation module links to each other with active devices and described read-write operation execution module respectively by the asynchronous access bus, described read-write operation execution module links to each other with internal integrated circuit equipment by internal integrate circuit bus, wherein:

Described command generation module, be used to receive device address, the register address of enabling signal, read/write signal and internal integrated circuit equipment that described active devices provides and will write the data of register, automatically produce the required instruction of visit internal integrated circuit equipment, deliver to described read-write operation execution module in regular turn, and to described active devices link order implementation status and integrated device electronics data of reading internally;

Described read-write operation execution module, be used for instruction according to described command generation module, abide by the internal integrate circuit bus agreement and produce the signal sequence that visit internal integrated circuit equipment needs, execution is to the read-write operation of inner integrated device electronics, and to described command generation module link order implementation status.

2, device as claimed in claim 1, it is characterized in that, described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, data command and halt instruction when detecting active devices and will write an internal integrated circuit equipment.

3, device as claimed in claim 1, it is characterized in that, described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, halt instruction, sign on, device address instruction and read indication, reception data command and halt instruction when detecting active devices and will read an internal integrated circuit equipment.

4, device as claimed in claim 1 is characterized in that, described command generation module comprises:

The order control register by the value that the enabling signal and the read/write signal of described active devices is provided with corresponding control bit, starts inner integrated device electronics is read or write, and when carrying out failure error flag is set;

Device address register, the device address that is used to store the internal integrated circuit equipment that will visit;

The register address register, the address that is used to store the register of the internal integrated circuit equipment that will visit:

Write data register, be used to store the data that to write;

Read data register is used to store the data that will read;

Frequency division is provided with register, is used to be provided with the multiple relation between the CLK frequency of the frequency of the SDA/SCL signal of sending and input;

Described active devices is selected above-mentioned register by the address signal of asynchronous access bus.

5, device as claimed in claim 4, it is characterized in that, described command generation module is after finishing a read or write look-at-me to be set to described active devices link order implementation status, perhaps after the order control register executes operation with corresponding bit automatic clear, perhaps the combination by above dual mode realizes.

6, device as claimed in claim 1, it is characterized in that, described read-write operation execution module comprises command register, receive data register, transmitting data register, clock generating unit, START generation unit, STOP generation unit, data transmission unit and Data Receiving unit, wherein:

Described command register, the value of corresponding control bit is set by the instruction of described command generation module, control the startup of described START generation unit, STOP generation unit, data transmission unit and Data Receiving unit, and the operation complete after with the corresponding positions zero clearing;

Described receive data register is used for the data that data cached receiving element receives;

Described transmitting data register is used for the data that data cached transmitting element will send;

Clock generating unit is used for producing the required clock of each module of read-write operation execution module;

Described START generation unit is used for producing the START sequential that the internal integrate circuit bus agreement is stipulated;

Described STOP generation unit is used for producing the STOP sequential that the internal integrate circuit bus agreement is stipulated;

Described data transmission unit is used for according to the SDA of internal integrate circuit bus agreement regulation, the sequential of SCL the data in the described transmitting data register being sent on the internal integrate circuit bus;

Described Data Receiving unit is used for receiving the data on the internal integrate circuit bus according to the SDA of internal integrate circuit bus agreement regulation, the sequential of SCL.

7, device as claimed in claim 6, it is characterized in that, asynchronous access bus between described command generation module and the read-write operation execution module comprises reset signal, clock signal, writes enable signal, transmitting data register is selected signal, command register is selected signal, data bus input and output signal, and the circuit of error indication signal, described error indication signal is produced by the control bit of described command register, is used for to described command generation module link order implementation status.

8, a kind of method that realizes writing automatically internal integrated circuit equipment is applied to active devices by in hard-wired command generation module and write operation execution module and the system that internal integrate circuit bus links to each other, and this method may further comprise the steps:

(a) address of the internal integrated circuit equipment that will visit of described active devices writes the device address register of described command generation module;

(b) address of the internal integrated circuit device register that will visit of described active devices writes the register address register of described command generation module;

(c) the described active devices data that will write write the data register that writes of described command generation module;

(d) described active devices is provided with the corresponding BIT position startup write operation of order control register in the described command generation module;

(e) described command generation module produces automatically and writes the required instruction of internal integrated circuit equipment, delivers to described write operation execution module in regular turn;

(f) described write operation execution module is abideed by the generation of internal integrate circuit bus agreement and is write the signal sequence of internal integrated circuit equipment and finish write operation, the link order implementation status according to the instruction of described command generation module;

(g) described command generation module is to described active devices link order implementation status;

(h) after described active devices decision operation is correctly finished, finish one time write operation.

9, method as claimed in claim 8 is characterized in that, after the described step (h), if next operation and last operational access is same internal integrated circuit equipment, then directly returns step (b), otherwise returns step (a).

10, method as claimed in claim 8 is characterized in that, in the described step (e), described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, data command and halt instruction.

11, method as claimed in claim 8 is characterized in that, in the described step (h), described active devices is quoted by the interruption of described command generation module, perhaps detects the value of the corresponding control bit of described command generation module and confirms whether operation is correctly finished; The value of the error indication bit by detecting described command generation module judges whether to carry out the fault processing operation.

12, a kind of method that realizes reading automatically internal integrated circuit equipment is applied to active devices by in hard-wired command generation module and read operation execution module and the system that internal integrate circuit bus links to each other, and this method may further comprise the steps:

(a) address of the internal integrated circuit equipment that will visit of described active devices writes the device address register of described command generation module;

(b) address of the internal integrated circuit device register that will visit of described active devices writes the register address register of described command generation module;

(c) described active devices is provided with the corresponding BIT position startup read operation of order control register in the described command generation module;

(d) described command generation module produces automatically and reads the required instruction of internal integrated circuit equipment, delivers to described read operation execution module in regular turn;

(e) described read operation execution module is abideed by the generation of internal integrate circuit bus agreement and is read the signal sequence of internal integrated circuit equipment and finish read operation according to the instruction of described command generation module, and the link order implementation status;

(f) described command generation module is returned data and the condition execution instruction of reading to described active devices;

(g) after described active devices decision operation is correctly finished,, finish a read operation from described command generation module sense data.

13, method as claimed in claim 12 is characterized in that, after the described step (g), if next operation and last operational access is same internal integrated circuit equipment, then directly returns step (b), otherwise returns step (a).

14, method as claimed in claim 12, it is characterized in that, in the described step (d), described command generation module sends sign on, device address instruction successively and writes indication, register address instruction, halt instruction, sign on, device address instruction and read indication, reception data command and halt instruction.

15, method as claimed in claim 12 is characterized in that, in the described step (g), described active devices is quoted by the interruption of described command generation module, perhaps detects the value of the corresponding control bit of described command generation module and confirms whether operation is correctly finished; The value of the error indication bit by detecting described command generation module judges whether to carry out the fault processing operation.

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