CN1292149A - Method for fabricating gallium nitride semiconductor layer by mask lateral sprawl and gallium nitride semiconductor structure fabricated thereby - Google Patents

Abstract

The gallium nitride semiconductor layer is fabricated by masking a lower gallium nitride layer (104) with a first mask (106) having a first array of openings, and growing a first overgrown gallium nitride semiconductor layer (108a, b) on the lower gallium nitride layer through the first array of openings. The first overgrown layer is then masked with a second mask (206) having a second array of openings. The second array of apertures is laterally offset from the first array of apertures. A second overgrown gallium nitride semiconductor layer (208a, b) is grown from the first overgrown gallium nitride layer (108a, b) through the second array of openings and spread over a second mask (206). A microelectronic device (210) is formed in the second overgrown gallium nitride semiconductor layer (208a, b).

Description

Method for fabricating gallium nitride semiconductor layer by mask lateral sprawl and gallium nitride semiconductor structure fabricated thereby

The present invention relates to a microelectronic device and a manufacturing method thereof, in particular to a gallium nitride semiconductor device and a manufacturing method thereof.

Gallium nitride is widely studied for use in microelectronic devices, including but not limited to transistors, field emitters, and optoelectronic devices. The gallium nitride mentioned here also includes alloys of gallium nitride, such as aluminum gallium nitride, indium gallium nitride and indium aluminum gallium nitride.

A major problem in fabricating GaN-based microelectronic devices is fabricating GaN semiconductor layers with low defect densities. One source of defect density is known to be the growth substrate of the gallium nitride layer. Therefore, although a gallium nitride layer has been grown on a sapphire substrate, it is known that forming an aluminum nitride buffer layer on a silicon carbide substrate and then growing a gallium nitride layer on it can reduce the defect density. Despite these advances, it is desirable to continue to reduce defect densities.

It is also known to fabricate gallium nitride structures through openings in a mask. For example, gallium nitride is selectively grown on a substrate with a striped or circular pattern to fabricate an array of field emission light sources. For example, refer to the paper entitled "Selective Growth of GaN and Al _0.2 Ga _{0. 8} N (Selective Growth of GaN and Al _{0 .2} Ga _0.8 N on GaN/AlN/6H-SiC (0001) Multilayer Structures Via Organometallic Vapor Phase Epitaxy)", Proceedings of the Materials Research Society, December, 1996, and entitled "Patterned Substrates by MOVPE Growth of GaN and Al _0.2 Ga _0.8 N (Growth of GaN and Al _0.2 Ga _0.8 N on Patterned Substrates via Organometallic Vapor Phase Epitaxy)", Japanese Journal of Applied Physics, Vol. 36, Part 2, No. 5A, May 1997, pp. L532-L535. It is revealed in these articles that under certain conditions undesired ridge growth or overgrowth may occur.

It is therefore an object of the present invention to provide improved methods of making gallium nitride semiconductor layers and the improved gallium nitride layers so made.

Another object of the present invention is to provide a method of fabricating a gallium nitride semiconductor layer having a low defect density and a gallium nitride semiconductor layer thus fabricated.

These and other objects of the present invention are to produce a gallium nitride semiconductor layer which is laterally grown on an underlying gallium nitride layer to form a laterally grown gallium nitride semiconductor layer, and to form microstructures in the laterally grown gallium nitride semiconductor layer. electronic devices. In a preferred example, the gallium nitride semiconductor layer is made by using a mask to cover the lower gallium nitride layer, and the mask has an array of openings, and grows on the lower gallium nitride layer and the mask through the opening array, thereby forming sprawling gallium nitride semiconductor layer. Microelectronic devices can be formed in sprawling gallium nitride semiconductor layers.

It has been found that, in accordance with this aspect of the invention, while dislocation defects can propagate vertically from the underlying GaN layer into the GaN layer grown above the mask opening, defects are less likely in creeping GaN layers. few. Therefore, high performance microelectronic devices can be formed in the sprawling gallium nitride semiconductor layer.

According to another aspect of the present invention, the gallium nitride semiconductor layer is sprawled over the mask until it overlaps to form a continuous sprawling monocrystalline gallium nitride semiconductor layer. The creeper layer may thus contain regions of lower defect formation on the overlapped portion of the creeper and regions of higher defect formation on the mask opening.

According to another aspect of the present invention, the gallium nitride semiconductor layer can be produced in the following way: perform lateral growth on the lower gallium nitride layer to form a first lateral growth gallium nitride semiconductor layer; then grow the gallium nitride semiconductor layer from the first lateral growth Lateral growth is performed on the upper layer to form a second laterally grown gallium nitride semiconductor layer. Microelectronic devices can then be formed in the second laterally grown gallium nitride semiconductor layer.

Especially in a preferred example, the gallium nitride semiconductor layer is produced in the following way: the lower gallium nitride layer is covered with a first mask, the mask has a first opening array, and the lower gallium nitride layer is formed through the first opening array. layer and the mask to form a first sprawling gallium nitride semiconductor layer. The first creeper layer is then masked with a second mask having a second array of openings. The second hole array is laterally staggered from the first hole array. The second sprawling GaN layer is grown on the first sprawling GaN layer through the second opening array, and sprawled onto the second mask, thereby forming a second sprawling GaN semiconductor layer. Microelectronic devices can then be formed in the second sprawling GaN semiconductor layer.

It has been found that, according to this aspect of the invention, while dislocation defects can propagate vertically from the underlying GaN layer into the GaN layer grown above the mask opening, defects in the first creeping GaN layer less. Moreover, since the opening array of the second mask is laterally staggered from the opening array of the first mask, the first sprawling GaN layer with fewer defects expands through the second opening array and spreads to the second mask superior. Therefore, high performance microelectronic devices can be formed in the second sprawling GaN semiconductor layer.

According to another aspect of the present invention, the second sprawling GaN semiconductor layer is grown laterally until it overlaps the second mask to form a continuous monocrystalline GaN semiconductor layer. Thus the entire continuous creep layer has very few defects compared to the underlying GaN layer

The first and second gallium nitride semiconductor layers can be grown using metal organic vapor phase epitaxy (MOVPE). The openings of the mask are preferably strips arranged along the <1 100> direction of the lower gallium nitride layer. The sprawling gallium nitride layer can be grown using triethylgallium (TEG) and ammonia (NH ₃ ) precursors at 1000-1100°C and 45 Torr. It is more appropriate to use 13-39 μmol/min (micromol/min) of triethylgallium (TEG) and 1500 sccm (standard milliliter/min) of ammonia (NH ₃ ) together with 3000 sccm of H ₂ as the diluent. Growth is best performed with 26 μmol/min of triethylgallium (TEG), 1500 sccm NH ₃ and at 1100° C. and 45 Torr. The lower gallium nitride layer is suitably formed on a substrate, which itself includes a buffer layer such as aluminum nitride, grown on eg a 6H-SiC (0001) substrate.

The gallium nitride semiconductor structure of the present invention contains a lower gallium nitride layer, a lateral gallium nitride layer extending from the lower gallium nitride layer, and a number of microelectronic devices in the lateral gallium nitride layer. In a preferred example, the gallium nitride semiconductor structure of the present invention comprises a lower gallium nitride layer and a pattern layer (such as a mask) thereon, and the pattern layer has an array of openings. The vertical GaN layer extends upwardly from the lower GaN layer through the array of openings. The lateral gallium nitride layer extends from the vertical gallium nitride layer to the pattern layer on the lower gallium nitride layer. Many microelectronic devices, including but not limited to optoelectronic devices and field emitters are formed in the lateral gallium nitride layer.

The lateral gallium nitride layer is preferably a continuous monocrystalline gallium nitride semiconductor film. Both the lower GaN layer and the vertical GaN layer have a predetermined defect density, and the lateral GaN semiconductor layer has a defect density lower than the predetermined defect density. Therefore, a gallium nitride semiconductor layer with low defect density can be obtained, so that high-performance microelectronic devices can be produced.

Other gallium nitride semiconductor structures of the present invention comprise a lower gallium nitride layer, a first lateral gallium nitride layer extending from the lower gallium nitride layer, and a second lateral gallium nitride layer extending from the first lateral gallium nitride layer layer. Many microelectronic devices are formed in the second lateral gallium nitride layer.

In a preferred example, the GaN semiconductor structure of the present invention comprises a lower GaN layer, on which a first mask has a first array of openings. The first vertical gallium nitride layer extends upwardly from the lower gallium nitride layer through the first hole array. The first lateral GaN layer extends from the vertical GaN layer onto the mask on the lower GaN layer. The second mask on the first lateral GaN layer has a second array of openings laterally offset from the first array of openings. The second vertical GaN layer extends upwardly from the first lateral GaN layer through the second opening array. The second lateral GaN layer extends from the second vertical GaN layer onto the second mask on the first lateral GaN layer. Many microelectronic devices, including but not limited to optoelectronic devices and field emitters, can then be formed in the second vertical gallium nitride layer and the second lateral gallium nitride layer.

The second lateral gallium nitride layer is preferably a continuous monocrystalline gallium nitride semiconductor layer. The lower GaN layer has a predetermined defect density, and the second vertical and lateral GaN layers have defect densities lower than the predetermined defect density. Therefore, a continuous gallium nitride semiconductor layer with low defect density can be obtained by means of a laterally staggered mask, thereby fabricating a high-performance microelectronic device.

FIG. 1 is a cross-sectional view of a first example of a gallium nitride semiconductor structure of the present invention.

2-5 are cross-sectional views of the structure of Fig. 1 at intermediate processing steps according to the present invention.

FIG. 6 is a cross-sectional view of a second example of the gallium nitride semiconductor structure of the present invention.

7-14 are cross-sectional views of the structure of Fig. 6 at intermediate processing steps according to the present invention.

In the following the invention will be described more fully with reference to some preferred examples shown in the accompanying drawings. However, this invention may be embodied in many different forms and is not limited to those specific examples described herein; rather, these examples are provided so that this invention will be more complete and thorough, and will incorporate the The range is fully provided to those skilled in the art. The thickness of layers and regions in the drawings are exaggerated for clarity. Like numbers represent like units. It will also be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present therebetween. Moreover, each example described here also includes the case where the conductivity type thereof is a complementary conductivity type.

Referring now to FIG. 1, there is illustrated a gallium nitride semiconductor structure of the present invention. GaN structure 100 includes substrate 102 . The substrate can be sapphire or gallium nitride. However, the substrate preferably includes a 6H-SiC (0001) substrate 102a or has an aluminum nitride buffer layer 102b on a silicon carbide substrate 102a. The aluminum nitride buffer layer 102b may be 0.01 μm thick.

The preparation of substrate 102 is well known in the art and need not be further described. The preparation of silicon carbide substrates is described, for example, in Palmour 4,865,685, Davis et al. Re 34,861, Kong et al. For the description, it is cited here for reference. Furthermore, the knowledge about crystallography used here is also well known in the art and need not be described further.

On the buffer layer 102b of the substrate 102a is a gallium nitride layer 104. The thickness of the lower GaN layer 104 can be between 1.0 and 2.0 μm, and can be formed by heated metal organic vapor phase epitaxy (MOVPE). The lower gallium nitride layer generally has an undesirably high defect density, such as a dislocation density in the range of 10 ⁸ to 10 ¹⁰ cm ^-2 . Such a high defect density may result from a lattice mismatch between the buffer layer 102b and the underlying GaN layer 104 . It can affect the performance of microelectronic devices formed in the lower gallium nitride layer 104 .

Continuing with the description of FIG. 1 , there is a mask, such as a silicon dioxide mask 106 , over the lower gallium nitride layer 104 . Mask 106 has an array of openings therein. The opening is preferably strip-shaped, along <1 of the lower gallium nitride layer 104. 100> direction arrangement. Mask 106 may be 1000 Å thick and may be deposited on lower gallium nitride layer 104 by low pressure chemical vapor deposition (CVD) at 410°C. Mask 106 can be patterned using standard photolithographic techniques and etched in a buffered hydrofluoric acid (HF) solution.

Continuing with the description of FIG. 1 , the gallium nitride layer 108 a is vertically grown on the lower gallium nitride layer 104 through the opening of the mask 106 . The term “longitudinal” here means a direction perpendicular to the crystal plane of the substrate 102 . The vertical GaN layer 108a can be formed by metalorganic vapor phase epitaxy at 1000-1100° C. and 45 Torr. The vertical gallium nitride layer 108 a is grown by using 13-39 μmol/min of triethylgallium precursor (TEG) and 1500 sccm of ammonia gas (NH ₃ ) with 3000 sccm of H ₂ as diluent.

Continuing with the description of FIG. 1 , the GaN semiconductor structure 100 also includes a lateral GaN layer 108 b , which is formed by laterally extending the vertical GaN layer 108 a over the mask 106 on the lower GaN layer 104 . The lateral GaN layer 108b can be formed by the metalorganic vapor phase epitaxy described above. The term “transverse” here means a direction parallel to the crystal plane of the substrate 102 .

As shown in FIG. 1 , the lateral gallium nitride layer 108b overlaps at the interface 108c to form a continuous gallium nitride semiconductor single crystal layer 108 . It has been found that the dislocation density in the lower gallium nitride layer 104 does not propagate with the same intensity in the lateral direction as it does in the longitudinal direction. Therefore, the lateral GaN layer 108b may have a lower defect density, such as less than 10 ⁴ cm ^-2 . Thus, the lateral GaN layer 108b may form a device-quality GaN semiconductor material. Thus, as shown in FIG. 1, microelectronic devices 110 may be formed in lateral gallium nitride layer 108b.

Referring now to FIGS. 2-5, a method of fabricating a gallium nitride semiconductor structure in accordance with the present invention will be described. As shown in FIG. 2 , a lower gallium nitride layer 104 is grown on the substrate 102 . The substrate 102 may include a 6H-SiC (0001) substrate 102a and an aluminum nitride buffer layer 102b. The thickness of the gallium nitride layer 104 can be between 1.0 and 2.0 μm, and it can be grown at 1000° C. on the high temperature (1100° C.) aluminum nitride buffer layer 102b, and the aluminum nitride buffer layer 102b is grown on the cold 26 μmol/min of triethylgallium, 1500 sccm of ammonia and 3000 sccm of hydrogen were used as diluents to deposit on the 6H-SiC substrate 102a in a vertical metalorganic vapor phase epitaxy system with wall induction heating. More details on this growth technique can be found in T. W． Weeks et al. "GaN Thin Films Deposited Via Organo-metallic Vapor Phase Epitaxy on α(6H)-SiC(0001) Using OMVPE on α(6H)-SiC(0001) Using High-Temperature Mono-crystalline AlN BufferLayers)", Applied Physics Letters, Vol. 67, No. 3, July 17, 1995, pp. 401-403, incorporated herein by reference. Other substrates, with or without buffer layers, can be used.

Still referring to FIG. 2 , the lower GaN layer 104 is masked with a mask 106 having an array of openings 107 thereon. The mask may consist of 1000 Å thick silicon dioxide deposited by low pressure CVD at 410°C. Masks of other materials may also be used. Standard photolithographic techniques can be used to pattern the mask and etch in buffered HF solution. In one example, opening 107 is 3 μm wide along <1 100>directions are arranged in parallel with a distance of 3-40μm. The entire structure may be dipped in a 50% buffered hydrochloric acid (HCl) solution to remove the surface oxide of the lower GaN layer 104 before further processing.

Referring now to FIG. 3 , a vertical gallium nitride layer 108 a is grown from the underlying gallium nitride layer 104 in the opening 107 . GaN growth can be performed at 1000-1100°C and 45Torr. Can use 13-39μmol/min of TEG precursor and 1500sccm of ammonia with 3000sccm of hydrogen as diluent. To form gallium nitride alloys, for example, the usual aluminum or indium precursors can also be added. As shown in FIG. 3 , GaN layer 108 a is grown vertically to the upper end of mask 106 .

The lower GaN layer 104 can also be grown laterally without the mask 106 , which can be achieved by properly controlling the growth parameters or patterning the lower GaN layer 104 . A patterned layer can be formed on the lower GaN layer after vertical or lateral growth without using a mask.

It is also possible to perform lateral growth in two directions to form a sprawling GaN semiconductor layer. In special cases, the mask 106 can be engraved along two orthogonal directions, such as <1 100> and <11 20>, extended aperture array 107. In this way, the orthogonal strip opening pattern forms a rectangle. In this case the ratio of the sides of the rectangle is best equal to {11 20} and { 1101} surface growth rate ratio is proportional, for example, 1.4:1.

Referring now to FIG. 4, the GaN layer 108a continues to grow, causing lateral sprawl on the mask 106 to form a laterally grown GaN layer 108b. Growth conditions for creepers can remain the same as described for FIG. 3 .

Referring now to FIG. 5 , lateral growth may continue until the lateral growth fronts overlap at interface 108 c to form a continuous gallium nitride layer 108 . Total growth time is approximately 60 minutes. As shown in FIG. 1, microelectronic devices may then be formed in region 108b. Devices may also be formed in region 108a, if desired.

Referring now to FIG. 6, there is illustrated a gallium nitride semiconductor structure of a second example of the present invention. The GaN structure 200 includes the aforementioned substrate 102 . As previously mentioned, there is also a gallium nitride layer 104 on the buffer layer 102b of the substrate 102a. On the lower gallium nitride layer 104 there is a first mask, such as a first silicon dioxide mask 106 . The first mask 106 contains a first array of openings. The first group of openings is preferably the first group of stripe patterns, as previously described it is along the <1 100> direction arrangement. The first vertical GaN layer 108a is grown upwardly from the lower GaN layer 104 through the first array of openings in the first mask 106 as previously described. The GaN semiconductor structure 200 also includes a first lateral GaN layer 108b that is laterally extended from the first vertical GaN layer 108a over the first mask 106 of the lower GaN layer 104 as previously described. of.

Continuing with the description of FIG. 6 , there is a second mask, such as a second silicon dioxide mask 206 , on the first vertical GaN layer 108 a. As shown, the second mask 206 is laterally offset from the first mask 106 . The second mask may also extend over the first gallium nitride layer 108b. Preferably the second mask 206 covers the entirety of the first vertical GaN layer 108b so that defects in this layer do not propagate further. The second mask 206 does not have to be symmetrically offset from the first mask 106 . The second mask 206 contains a second array of openings. The second opening is preferably oriented as the first mask. The second mask can also be fabricated like the first mask 106 .

Still continuing the description of FIG. 6 , the second vertical GaN layer 208 a grows upward from the first lateral GaN layer 108 a through the second opening of the second mask 206 . The second vertical GaN layer 208a may be formed like the first vertical GaN layer 108a. The GaN semiconductor structure 200 also includes a second lateral GaN layer 208 b formed by laterally expanding the second vertical GaN layer 208 a on the second mask 206 of the first GaN layer 108 . The second lateral GaN layer 208b can be formed by the aforementioned metalorganic vapor phase epitaxy method.

As shown in FIG. 6 , the second lateral GaN layer 208 b overlaps at the second interface 208 c to form a second continuous single-crystal GaN layer 208 . It has been found that since the first lateral GaN layer 108b is used to grow the second GaN layer 208 comprising the second vertical GaN layer 208a and the second lateral GaN layer 208b, thus There may be a lower defect density, such as less than 10 ⁴ cm ^-2 . Thus, the entire gallium nitride layer 208 may form a device-quality gallium nitride semiconductor material. Thus, as shown in FIG. 1, the microelectronic device 210 may be formed in both the second vertical gallium nitride layer 208a and the second lateral gallium nitride layer 208b, and may also straddle between these two regions. Therefore, by offsetting the masks 106 and 206, a continuous device-quality GaN layer can be obtained.

Referring now to FIGS. 7-14, a method of fabricating a second exemplary gallium nitride semiconductor structure in accordance with the present invention will now be described. As shown in FIG. 7 , a lower gallium nitride layer 104 is grown on the substrate 102 , see the description related to FIG. 2 for details. Still referring to FIG. 7 , the lower GaN layer 104 is masked by a first mask 106 containing a first array of openings 107 , see description in relation to FIG. 2 .

Referring to FIG. 8 , a first vertical GaN layer 108 a is grown on the lower GaN layer 104 in the first openings through the first hole array 107 , as described in relation to FIG. 3 . Referring to FIG. 9 , continuing to grow the first GaN layer 108 a causes lateral sprawl on the mask 106 to form a first lateral GaN layer 108 b , see the description related to FIG. 4 . Referring now to FIG. 10 , the lateral creep is continued until its growth fronts overlap at interface 108c to form a first continuous gallium nitride layer 108 , see description in relation to FIG. 5 .

Referring now to FIG. 11 , the first vertical GaN layer 108 a is masked by a second mask 206 containing a second array 207 of openings. The second mask can be fabricated like the first mask. As described in connection with the first mask in FIG. 3, the second mask may not be required. It has been noted that the second mask 206 preferably covers the entire first vertical GaN layer 108a to prevent defects therein from propagating vertically or laterally. In order not to propagate defects, the mask 206 may also extend onto the first lateral GaN layer 108b.

Referring now to FIG. 12 , a second vertical GaN layer 208 a is formed in the second openings by vertical growth from the first lateral GaN layer 108 c through the second opening array 207 . Growth can be carried out as described in relation to FIG. 3 .

Referring now to FIG. 13 , continuing to grow the second GaN layer 208 a causes sprawl on the second mask 206 to form a second lateral GaN layer 208 b. Lateral growth can be performed as described in relation to FIG. 3 .

Referring now to FIG. 14 , the lateral sprawl preferably continues until its lateral growth fronts overlap at the second interface 208c, thereby forming a second continuous gallium nitride layer 208 . Total growth time is approximately 60 minutes. Microelectronic devices can then be formed in regions 208a and 208b, as shown in FIG. 6, because both regions have lower defect densities. As shown, the device can also straddle the two regions. Thus, a continuous device-quality gallium nitride layer 208 can be obtained.

The method and device structure of the present invention will now be discussed again. As previously mentioned, the openings 107 and 207 in the mask are preferably along <11 of the lower GaN layer 104. 20> and/or <1 100> direction is extended and becomes rectangular bar. For edge <11 The mask opening 107 and 207 of 20> direction can obtain the rectangular bar of flat head, and it has (1 101) oblique crystal plane and narrow (0001) top surface. along <1 100> direction rectangular strips can be grown to have (0001) top surface, (11 20) vertical sides and (1 101) Oblique crystal plane. Similar morphologies were obtained regardless of orientation when the growth time was less than 3 min. As it continues to grow, the strips take on different shapes.

The extent of lateral growth generally has a strong relationship with the orientation of the stripes. <1 The lateral growth rate of the 100> oriented strips is higher than that along the <11 20> The direction person is much faster. Therefore, the orientation of openings 107 and 207 is preferably along <1 100> direction.

The relationship between the different morphology and the orientation of the openings seems to be related to the crystallographic stability of the GaN structure. Along <11 20> direction bars can have wide (1 100) oblique crystal plane, and either have a very narrow top surface or no (0001) top surface, depending on the growth conditions. This may be due to the wurtzite crystal structure of GaN (1 101) is the most stable face, and the growth rate of this face is lower than that of other faces. <1 100> {1 of orientation bars 101} surface is undulating, which means there are multiple Miller indices.

It appears that {1 The preferential competitive growth of 101} faces makes these faces unstable and their growth rate is higher than that along <11 20> Orientation strip (1 101) Surface increase.

in edge<1 The morphology of the GaN layer selectively grown on the 100> orientation opening generally has a strong relationship with the growth temperature. The shape of the growth layer at 1000° C. may be a flat-ended rectangle. As the growth temperature increases, its morphology can gradually change to a rectangular cross section. This shape change may be the result of an increased diffusion coefficient, so that gallium flows from the (0001) top surface to the {1 101} surface. This causes the (0001) plane growth rate to decrease and {1 101} face increased. This phenomenon has also been observed in the selective growth of gallium arsenide on silicon dioxide. Therefore, 1100°C appears to be the optimum growth temperature.

The change in the topography of the GaN region also appears to be related to the flux of the TEG. In general, increasing the supply of TEG accelerated the growth of both transverse and longitudinal stripes. However, the lateral/vertical growth rate ratio decreased from 1.7 to 0.86 when the TEG flux was increased from 13 μmol/min to 39 μmol/min. This influence on the growth rate in the direction of <0001> is greater than that of <11 with the increase of TEG flux. 20> The increase in direction may be related to the reactor used, where the reactant gas flows in the longitudinal direction and is perpendicular to the substrate. A significant increase in gallium concentration at the surface is sufficient to prevent its migration to {1 The diffusion of the 101} plane makes it easier to chemisorption and GaN growth on the (0001) plane.

Use width 3μm, spacing 7μm along <1 The openings 107 and 207 with a 100> orientation can obtain continuous gallium nitride layers 108 and 208 with a thickness of 2 μm at 1100° C. and a TEG flow rate of 26 μmol/min. The sprawling GaN layers 108b and 208b may contain subsurface voids, which are formed when two growth fronts overlap. Such voids most often occur under lateral growth conditions, when a vertical {11 20} Rectangular strips on the sides. The overlapping GaN layers 108 and 208 may have a flat surface without pits under a microscope. The surface of the laterally grown gallium nitride layer may contain a ladder structure with an average step height of 0.32nm. This stepped structure may be related to the laterally grown GaN, since the much larger films grown only on the AlN buffer layer generally do not have such steps. Its average RMS roughness may be similar to that of the underlying GaN layer 104 .

Screwing dislocations from the interface of the lower GaN layer 104 and the buffer layer 102b appear to propagate to the upper surface of the first vertical GaN layer 108a (in the opening 107 of the first mask 106). The dislocation density of this region is about 10 ⁹ cm ^-2 . In contrast, screw dislocations do not appear to propagate easily into the first creeper region 108b. More specifically, the first sprawling GaN region 108b contains few dislocations. These small amount of dislocations are formed after longitudinal screw dislocations are bent by 90° in the regeneration region, which is parallel to the (0001) plane. It appears that these dislocations did not propagate to the upper surface of the first sprawling GaN layer. Since both the second vertical GaN layer 208a and the second lateral GaN layer 208b are grown from the low-defect first sprawling GaN layer 108b, the entire layer 208 can have a low defect density.

As mentioned, the formation mechanism for selectively growing GaN layers is lateral epitaxy. The two main stages of this mechanism are longitudinal growth and transverse growth. During vertical growth, selective deposition of GaN is much faster in mask openings 107 and 207 than on masks 106 and 206, apparently due to the adhesion coefficient s of Ga atoms on the GaN surface (s=1) is much higher than on the mask (s~1). The strength of the SiO ₂ bond is 779.6kJ/mol (kilojoule/mol), much higher than the Si-N bond (439kJ/mol), Ga-N bond (103kJ/mol) and Ga-O bond (353.6kJ/mol) mol), Ga or N atoms are not easy to form a sufficient number of bonds on the mask surface in a time sufficient to form GaN nuclei. They either evaporate or diffuse along the mask surface to the mask opening 107 or 207 or to the exposed vertical GaN surface 108a or 208a. GaN grows vertically and laterally on the mask simultaneously on the material exposed from the openings during lateral growth.

In the selective growth of GaN, the surface diffusion of Ga and N plays only a minor role. The material appears to be mainly from the vapor phase. This is evidenced by the fact that an increase in the TEG flux causes the growth rate of the (0001) top surface to become faster than that of the (1 101) sides, thus controlling lateral growth.

The laterally grown gallium nitride layers 108b and 208b are sufficiently strongly bonded to the underlying masks 106 and 206 that they generally do not peel off upon cooling. However, lateral cracking can occur on _SiO2 due to thermal stress generated upon cooling. The viscosity (p) of _SiO2 at 1050°C is 10 ^15.5 poise, which is an order of magnitude larger than the strain point (10 ^14.5 poise), and the stress release in the amorphous material at the strain point is within about 6 hours occur. Therefore, the _SiO2 mask has only limited compliance when cooling. Since the arrangement of atoms on the surface of amorphous _SiO2 is very different from that of gallium nitride, chemical bonding can only occur when suitable pairs of atoms are in close proximity. The very small relaxation of silicon and oxygen atoms and gallium and nitrogen atoms on their respective surfaces and/or in the bulk of _SiO2 accommodates and bonds gallium nitride to the oxide.

Therefore, the growth of the lateral epitaxial sprawl on the lower GaN layer from the mask opening can be realized by MOVPE. The growth process strongly depends on the opening orientation, growth temperature and TEG flux. Through width 3μm, spacing 7μm along <1 With 100> orientation openings, at 1100°C and a TEG flow rate of 26 μmol/min, overlapping sprawling GaN regions can be obtained to form GaN regions with extremely low dislocation density and smooth surface without pits. GaN lateral sprawl by MOVPE can yield continuous GaN layers with low defect density for use in microelectronic devices.

Typical preferred examples of the invention have been disclosed in the drawings and detailed description thereof, and although some specific terms are used, they are used for general description only and not for the purpose of limitation, the scope of the invention will be set forth in the following claims requesting.

Claims (59)

1. A method for making a gallium nitride semiconductor layer, comprising the following steps: masking the lower gallium nitride layer with a mask with an array of openings; A sprawling GaN semiconductor layer is formed by growing from the underlying GaN layer through an array of openings and extending onto the mask. 2. The method of claim 1, wherein the growing step is followed by forming the microelectronic device in the sprawling gallium nitride semiconductor layer. 3. The method of claim 1, wherein the growing step comprises growing the underlying gallium nitride layer through the array of openings and extending onto the mask until overlapping the mask, thereby forming a continuous sprawling monocrystalline gallium nitride semiconductor layer. 4. The method of claim 1, wherein the growing step includes growing the lower gallium nitride layer by metalorganic vapor phase epitaxy. 5. The method of claim 1, wherein a lower gallium nitride layer is formed on the substrate prior to the masking step. 6. The method according to claim 5, comprising the forming steps of: forming a buffer layer on the substrate; and forming a lower gallium nitride layer on the buffer layer of the substrate. 7. The method according to claim 1, wherein the masking step comprises: masking the lower gallium nitride layer with a mask having an array of strip-shaped openings along <1 of the lower gallium nitride layer. 100> direction arrangement. 8. The method of claim 1, wherein the lower GaN layer has a predetermined defect density, and the step of growing from the lower GaN layer through the array of openings and extending onto the mask to form a sprawling GaN semiconductor layer comprises: Vertical growth on the underlying GaN layer through an array of openings, with which a predetermined defect density is propagated; A sprawling GaN semiconductor layer having a defect density lower than a predetermined density is formed by laterally growing from the lower GaN layer onto the mask through the array of openings. 9. The method according to claim 1, wherein the growth step is carried out at 1000-1100° C. by organic metal vapor phase epitaxy, using triethylgallium 13-39 μmol/min and ammonia gas 1500 sccm on the lower gallium nitride layer. 10. According to the method of claim 7, the growth step is carried out at 1100° C. by organic metal vapor phase epitaxy, using 26 μmol/min of triethylgallium and 1500 sccm of ammonia gas on the lower gallium nitride layer. 11. The method according to claim 1, wherein said sprawling GaN semiconductor layer is a first sprawling GaN semiconductor layer, the method further comprising the steps of: masking the first sprawling gallium nitride layer with a second mask having a second hole array, the second hole array and the first hole array are laterally staggered; The second sprawling GaN layer is grown on the first sprawling GaN layer through the second opening array and sprawled onto the second mask, thereby forming a second sprawling GaN semiconductor layer. 12. The method of claim 11, wherein after growing on the first sprawling GaN layer, the microelectronic device is subsequently formed in the second sprawling GaN semiconductor layer. 13. The method of claim 11, wherein the step of growing on the first sprawling GaN layer comprises: growing on the first sprawling GaN layer through the second array of openings and sprawling onto the second mask until A continuous sprawling monocrystalline gallium nitride semiconductor layer is formed by lapping on the second mask. 14. 11. The method of claim 11, wherein the growing step includes the step of growing the lower gallium nitride layer and the first creeping gallium nitride layer by metalorganic vapor phase epitaxy. 15. The method of claim 11, wherein the first and second masking comprises: Masking the lower gallium nitride layer and the first sprawling gallium nitride layer with a first mask and a second mask respectively, the two masks respectively have first and second strip-shaped opening arrays, and the strip-shaped openings are along the <1 of the lower GaN layer 100> direction arrangement. 16. The method of claim 11, wherein the lower gallium nitride layer has a predetermined defect density, the step of forming a first sprawling gallium nitride semiconductor layer by growing on the lower gallium nitride layer through a first array of openings and sprawling onto the mask include: Vertical growth is performed on the lower GaN layer through the first array of openings, and a predetermined defect density is propagated accordingly; The first mask is grown laterally from the lower GaN layer of the first opening array, thereby forming a first sprawling GaN semiconductor layer with a defect density lower than a predetermined one. 17. The method of claim 16, wherein growing on the first sprawling GaN layer comprises the steps of: performing vertical growth on the first sprawling gallium nitride semiconductor layer through the second opening array; The second sprawling GaN semiconductor layer is grown laterally from the first sprawling GaN semiconductor layer of the second opening array onto the second mask, thereby forming a second sprawling GaN semiconductor layer with a defect density lower than a predetermined defect density. 18. The method of claim 11, wherein the lower gallium nitride layer has a predetermined defect density and the second creeping gallium nitride semiconductor layer has a defect density lower than that. 19. The method according to claim 11, wherein the growth of the lower gallium nitride layer and the first sprawling gallium nitride layer is by organometallic vapor phase epitaxy, using triethylgallium 13-39 μmol/min and ammonia gas 1500 sccm at 1000-1100 carried out at ℃. 20. The method according to claim 15, wherein the growth of the lower gallium nitride layer and the first sprawling gallium nitride layer is carried out at 1100° C. by metalorganic vapor phase epitaxy using triethylgallium 26 μmol/min and ammonia gas 1500 sccm . twenty one. A method for making a gallium nitride semiconductor layer, comprising the following steps: performing lateral growth on the lower gallium nitride layer to form a laterally grown gallium nitride semiconductor layer; Microelectronic devices are formed in the laterally grown gallium nitride semiconductor layer. twenty two. The method according to claim 21, wherein the lateral growing step comprises: performing lateral growth on the lower gallium nitride layer until the laterally grown gallium nitride layers overlap to form a continuous laterally grown monocrystalline gallium nitride semiconductor layer. twenty three. 21. The method of claim 21, wherein the lateral growing step includes laterally growing the lower gallium nitride layer by metalorganic vapor phase epitaxy. twenty four. 21. The method of claim 21, wherein the step of laterally growing includes laterally creeping the underlying gallium nitride layer. 25． The method of claim 21, wherein the lower gallium nitride layer has a predetermined defect density, and the lateral growing step comprises the steps of: Laterally grown on the lower gallium nitride layer to form a laterally grown gallium nitride semiconductor layer having a lower than predetermined defect density. 26． A method for making a gallium nitride semiconductor layer, comprising the following steps: performing lateral growth on the lower gallium nitride layer to form a first laterally grown gallium nitride semiconductor layer; Lateral growth is performed on the first laterally grown GaN layer to form a second laterally grown GaN semiconductor layer. 27． The method of claim 26, wherein the lateral growth on the first lateral gallium nitride layer is followed by forming the microelectronic device in the second lateral growth gallium nitride semiconductor layer. 28． The method according to claim 26, wherein the step of laterally growing the first lateral GaN layer comprises: performing lateral growth on the first lateral GaN layer until the second lateral GaN layer overlaps to form a continuous Laterally grown monocrystalline GaN semiconductor layer. 29． 26. The method of claim 26, wherein the lateral growing step includes laterally growing the lower gallium nitride layer and the first laterally grown gallium nitride layer by metalorganic vapor phase epitaxy. 30． 26. The method of claim 26, wherein the step of laterally growing the first laterally grown gallium nitride layer comprises laterally creeping the first laterally grown gallium nitride layer. 31． The method of claim 26, wherein the lower gallium nitride layer has a predetermined defect density, and the step of laterally growing the first lateral gallium nitride layer comprises: Lateral growth is performed on the first lateral GaN layer to form a second laterally grown GaN semiconductor layer with a defect density lower than a predetermined one. 32． A gallium nitride semiconductor structure comprising: a lower gallium nitride layer; a first patterned layer on the lower gallium nitride layer, containing a first array of openings; growing a first vertical gallium nitride layer from the lower gallium nitride layer through the first array of openings; The first lateral gallium nitride layer extends from the first vertical gallium nitride layer to the first pattern layer on the lower gallium nitride layer. 33． The structure of claim 32, further comprising: a plurality of microelectronic devices in the first lateral gallium nitride layer. 34． 32. The structure of claim 32, wherein the first lateral gallium nitride layer is a first continuous single crystal gallium nitride semiconductor layer. 35． The structure of claim 32, further comprising a substrate and a lower gallium nitride layer thereon. 36． The structure of claim 35, further comprising a buffer layer between the substrate and the underlying gallium nitride layer. 37． The structure of claim 32, wherein the first patterned layer contains an array of openings along <1 of the lower gallium nitride layer. 100> direction arrangement. 38． 32. The structure of claim 32, wherein the lower gallium nitride layer has a predetermined defect density, the first vertical gallium nitride layer also has a predetermined defect density, and the first lateral gallium nitride layer has a defect density lower than the predetermined defect density. 39． The structure of claim 32, further comprising: A second graphic layer on the first lateral gallium nitride layer, which has a second aperture array and is laterally staggered from the first aperture array; a second vertical GaN layer extending from the first lateral GaN layer through the second array of openings; On the second pattern layer on the first lateral GaN layer, a second lateral GaN layer extended from the second vertical GaN layer. 40． The structure of claim 39, further comprising: a plurality of microelectronic devices in the second lateral gallium nitride layer. 41． 39. The structure of claim 39, wherein the second lateral gallium nitride layer is a continuous monocrystalline gallium nitride semiconductor layer. 42． The structure of claim 39, wherein both the first and second arrays of openings are <1 100> direction arrangement. 43． 39. The structure of claim 39, wherein the lower gallium nitride layer has a predetermined defect density and the second vertical gallium nitride layer and the second lateral gallium nitride semiconductor layer have a defect density lower than the predetermined defect density. 44． A single crystal gallium nitride layer having a predetermined defect density includes a plurality of discrete regions having a defect density lower than the predetermined defect density. 45． The gallium nitride layer of claim 44, wherein the predetermined defect density is at least 108 cm ^-2 and the lower defect density is less than ¹⁰⁴ cm ^-2 . 46． The gallium nitride layer according to claim 44, wherein the discrete regions are <1 100〉The strip area arranged in the direction. 47． A continuous single crystal gallium nitride layer having a defect density lower than the predetermined defect density on an underlying gallium nitride layer having a predetermined defect density. 48． The gallium nitride layer of claim 47, wherein the predetermined defect density is at least 10 ⁸ cm ^-2 and the lower defect density is less than 10 ⁴ cm ^-2 . 49． A gallium nitride semiconductor structure comprising: a lower gallium nitride layer; a lateral gallium nitride layer extending from the lower gallium nitride layer; There are many microelectronic devices in the lateral gallium nitride layer. 50． The structure of claim 49, further comprising: a vertical gallium nitride layer between the lower gallium nitride layer and the lateral gallium nitride layer. 51． 49. The structure of claim 49, wherein the lateral gallium nitride layer is a continuous single crystal gallium nitride semiconductor layer. 52． The structure of claim 49, further comprising a substrate on which the lower gallium nitride layer is grown. 53． The structure of claim 52, further comprising a buffer layer between the substrate and the underlying gallium nitride layer. 54． 49. The structure of claim 49, wherein the lower gallium nitride layer has a predetermined defect density and the lateral gallium nitride semiconductor layer has a defect density lower than the predetermined defect density. 55． A gallium nitride semiconductor structure comprising: lower gallium nitride layer; a first lateral gallium nitride layer extending from the lower gallium nitride layer; a second lateral gallium nitride layer extending from the first lateral gallium nitride layer; There are many microelectronic devices in the second lateral gallium nitride layer. 56． The structure of claim 55, wherein the second lateral gallium nitride layer is a continuous single crystal gallium nitride semiconductor layer. 57． 55. The structure of claim 55, further comprising a substrate on which the lower gallium nitride layer is grown. 58． 55. The structure of claim 55, wherein the lower gallium nitride layer has a predetermined defect density and the second lateral gallium nitride semiconductor layer has a defect density lower than the predetermined defect density. 59． The structure of claim 55, further comprising: a first vertical gallium nitride layer between the lower gallium nitride layer and the first lateral gallium nitride layer; A second vertical GaN layer interposed between the first lateral GaN layer and the second lateral GaN layer.

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