CN1290038A - Piled capacitor memory units and manufacture thereof - Google Patents

Abstract

A memory cell includes a field effect transistor and a stack capacitor. The stack capacitor has a plate formed of a platinum layer on a sidewall of a portion of a dielectric layer stacked on a conductive layer in contact with a conductive plug connected to a storage node of a cell. The capacitor dielectric is stacked on the side wall and upper part of the dielectric layer part, and the other plate of the capacitor is formed by a platinum layer on the capacitor dielectric.

Description

Stacked capacitor memory cell and method of manufacturing the same

The present invention relates to a dynamic random access memory (DRAM), and more particularly to a memory cell for a DRAM including a field effect transistor and a stack capacitor and a method of manufacturing the same.

DRAM is one of the most important integrated circuits. A typical DRAM includes a large array of memory cells arranged in rows and columns, each memory cell storing a binary number (bit) that can control the reading in and out of the cell. To store data bits between write and read operations, each memory cell typically includes a capacitor in series with a switch, typically a MOS transistor. In order to provide a large array of memory cells on a single silicon chip, it is important to use memory cells that occupy a small silicon area and can be densely packed. Since such switching transistors must be located in the silicon wafer, one formation of the memory cell saves space by forming the storage capacitor on the upper surface of the silicon chip rather than inside the silicon chip. Capacitors thus formed are often referred to as stack capacitors because they are typically formed from a multilayer stack on the upper surface of a silicon chip.

Due to the small size and high density of such capacitors on the upper surface of the chip, a process for forming them is required, and the present invention provides an improved process for forming such stacked capacitors.

The present invention is directed to a memory cell including a transistor and a stacked capacitor and a method of manufacturing the same.

The storage unit was fabricated as follows:

First, a silicon chip is prepared on the upper surface of which field effect transistors having drain and source regions are formed. The source region is electrically connected to the lower plate of the stack capacitor. For convenience, this current terminal is called a drain. Typically, the top surface of the chip has an overlying dielectric layer which, in addition to the stacked capacitors, will include layers providing bit and word lines for writing to and reading from the memory cells.

To form a stacked capacitor, a contact hole aligned with a source of a storage node serving as a memory cell is first formed in the dielectric capping layer. Preferably such holes are formed using anisotropic etching so that the holes may have substantially vertical sidewalls.

After the hole is formed, it is filled with a conductor to form a conductive plug, typically of highly doped polysilicon, to form a low resistance connection to the drain region of the transistor used as the storage node. To ensure that the plug makes a good connection, it is preferable to overfill the plug and then planarize the surface, typically using chemical mechanical polishing (CMP).

Although this can be omitted, it is preferred to then cover the top surface of the plug with a diffusion barrier layer which will create a conductive connection to the plug and a metal layer which will then be deposited on the barrier layer, preferably platinum, which will act as a stack capacitor. first plate or storage node. The diffusion barrier layer will for example act as a barrier preventing any unwanted material such as polysilicon from diffusing into the metal layer. This is especially important when the metal layer consists of platinum which is not expected to react with silicon. Suitable barrier layer materials include TiN, TaSiN and TiAlN.

After the barrier layer is formed, the dielectric layer is covered. The dielectric layer is photolithographically patterned, leaving a limited portion centered on the conductive plug in the original dielectric layer. The surface area of the sidewalls of this limited portion of the dielectric layer will largely determine the capacitance provided, so the size of this portion is chosen appropriately.

A metal, preferably platinum, is then deposited on the sidewalls of the defined portion. Optionally, the metal can also cover the upper surface. This metal will serve as the lower plate of the capacitor.

Then, the barrier layer is etched to make it conformal. A layer of material suitable for use as a dielectric for a stacked capacitor is then conformally formed on the platinum layer.

Finally, a second metal layer, preferably also platinum, is deposited on the capacitor dielectric, completing the capacitor. This will form the second (upper) plate of the capacitor, which is generally held at a fixed potential, usually ground.

From a device perspective, the present invention is directed to memory cells. The memory cell comprises a semiconductor body having on its upper surface first and second regions of one conductivity type separated by an intermediate region of opposite conductivity type for forming a transistor and a capacitor. The capacitor is formed on the first region and includes: a conductive plug in electrical contact with said first region; a conductive layer forming a diffusion barrier layer overlying said plug; overlying said barrier layer and positioned on said The portion of the dielectric layer on the plug; a first metal layer on at least the sidewalls of said dielectric layer, which layer is in electrical contact with the barrier layer and serves as the inner plate of the capacitor; the upper portion conformally surrounding said portion of the dielectric layer and a layer of dielectric material on the sidewall surfaces, which serves as the capacitor dielectric; and a second metal layer, conformally superimposed on the last-mentioned layer of dielectric material, which serves as the outer plate of the capacitor.

From a process perspective, the present invention is directed to methods of forming memory cells. The method comprises the steps of: forming separated source and drain regions of transistors on the upper surface of the silicon body; forming a dielectric capping layer on the upper surface of the silicon body; Form a contact hole with a substantially vertical sidewall in a part of the dielectric covering layer; fill the contact hole with a conductor to form a conductive plug to the last-mentioned isolated region; form a conductive barrier layer on the conductive plug; A dielectric layer portion is formed on the conductive barrier layer; a conductive layer is formed on at least the sidewall of the dielectric layer portion, serving as an inner plate of a storage capacitor; a dielectric layer is formed on said last-mentioned conductive layer, the dielectric layer portion The upper part of is suitable as a dielectric layer of a storage capacitor; a conductive layer is formed on the dielectric capacitor layer to serve as an outer plate of the storage capacitor.

The present invention can be better understood from the following detailed description in conjunction with the accompanying drawings.

Figure 1 shows a circuit diagram and a semiconductor cross section of a memory cell of a typical existing DRAM;

Figure 2 shows a memory chip including stacked capacitors shown schematically on its upper surface; and

3-9 illustrate the fabrication method of the stacked capacitor of the present invention using the memory cell of FIG. 2 .

Note that the figures are not drawn to scale.

Figure 1 shows a typical existing memory cell 10 used in many current DRAMs. The memory cell 10 is shown in circuit diagram form and the semiconductor device is shown in cross-sectional view. The unit comprises a capacitor 18 having first and second plates 18a and 18b, and an insulated gate field effect transistor (IGFET), known as a metal oxide semiconductor field effect transistor (MOSFET). The IGFET is formed in a semiconductor body (substrate) 11 comprising a drain region 12 and a source region 13 separated by a portion of the substrate 11 . A dielectric layer 14 covers that portion of substrate 11 isolating regions 12 and 13, indicated as a gate oxide. Overlying layer 14 is a gate conductor 15 coupled to a word line of the DRAM. Covering at least a portion of the drain is a contact 16 coupled to a bit line of the DRAM. Covering at least a portion of area 13 is a contact 17 coupled to plate 18 a of capacitor 18 . A plate 18b of capacitor 18 is generally coupled to a fixed potential, shown as ground 19 . Region 12, which has been indicated as a drain, becomes a source during some portion of memory cell 10 operation. Region 12, which has been indicated as a source, becomes a drain during some portion of memory cell 10 operation. Substrate 11 is typically n-type silicon, and regions 12 and 13 are p-type. For an n-channel transistor, substrate 11 is p-type and regions 12 and 13 are n-type. Binary digits are written to and read from capacitor 18 after signals are applied to the bit and word lines.

Figure 2 shows a cross-sectional view of a p-type portion of a silicon body (substrate) 20 large enough to accommodate a memory cell of the present invention. In the upper surface 21 of the substrate 20, two n-type regions 20a and 20b separated by a part of the substrate 20 are formed, forming the source and drain of the transistor. Dielectric layer 22a, or gate oxide, overlies the portion of substrate 20 between regions 20a and 20b, and gate 22b overlies layer 22a. The upper surface 21 is overlaid with a layer 24 of primarily dielectric material, typically a combination of silicon oxide and silicon nitride layers, including contact plugs (not shown) that serve as bit and word lines and connect the transistor terminals to these lines. various conductive layers (not shown).

Capacitors, shown as stack capacitors, will be formed in trenches 23 extending through layer 24 down to region 20a.

FIG. 3 shows a part of the structure of FIG. 2 , including region 20 a , layer 24 and contact hole 23 . To form the stacked capacitor of the present invention, a contact hole 23 is first formed in the dielectric layer 24 to expose a part of the region 20 a of the substrate 20 . The contact hole preferably has vertical sidewalls and is typically formed by reactive ion etching (RIE) of anisotropic etching under the control of a mask formed by known photolithographic patterning techniques.

In the subsequent figures, only a portion of the dielectric layer 24 is shown, in which a stacked capacitor is formed with a low resistance connection to the n-type region 20a of the transistor.

As shown in FIG. 4 , the contact hole is filled with a conductive material, generally n-type doped polysilicon, to form a low-resistance conductive contact plug 26 to the bottom layer region 20 a of the substrate 20 . For reliable filling, enough polysilicon is typically deposited by chemical vapor deposition (CVD) to cover the surface of dielectric layer 24, and then the surface is planarized by known chemical mechanical polishing (CMP), leaving only the filling.

As also shown in FIG. 4, then, the area surrounding the contact plug 26 is preferably covered with a conductive barrier layer 27, which is generally a conductive material such as TaSiN, which can be used to limit the out-diffusion of n-type dopants or silicon from the polysilicon filling. migrate. Its thickness does not need to be thick, just enough to effectively block. The barrier layer is then covered with a dielectric layer 28, typically any of silicon oxide, silicon nitride or silicon oxynitride.

Then, as shown in FIG. 5, the dielectric layer 28 is trimmed to a layer 28a substantially centered on the contact plug 26, which generally has a cross-section larger than the plug because its sidewalls have substantially the surface area of the capacitor plates. .

Then, as shown in FIG. 6, a metal layer 29, preferably platinum, is formed at least on the sidewalls of the dielectric layer 28a. Preferably, it is also deposited overlying the upper surface of dielectric layer 28a, as shown in Figure 9, discussed later. If it is desired to limit layer 29 to the sidewalls only, it is generally preferred to deposit platinum uniformly on all exposed surfaces of layer 28a and then remove the unwanted platinum by known means such as ion milling. The remaining exposed portion of barrier layer 27 is then removed, leaving the structure shown in FIG. 7 . The platinum layer 29 remaining on the side walls of layer 28a will serve as the lower plate of the capacitor which will be connected to the current terminal of the switching transistor, as shown in FIG. 1 .

Next, as shown in FIG. 8 , a dielectric layer 30 to be used as a capacitor medium and a metal layer 31 to be used as an upper plate of a capacitor are further deposited. The dielectric layer 30 should be made of a material with a high dielectric constant, such as barium strontium titanate, to provide the high capacitance required by the storage capacitor. Metal layer 31 should consist of a good conductor, preferably platinum. It is generally necessary to extend a portion of the dielectric layer 30 serving as the capacitor dielectric to sufficiently prevent any misalignment of the capacitor parts with the contact plugs. The outer layer 31, which acts as the outer plate of the capacitor, will generally extend over the surface of the chip to serve a similar role as in other cells in the array.

In the illustrated embodiment, the height of the stack capacitor on the upper surface of contact plug 26 is about 0.25 microns, the thickness of layer 27 is about 200-500 angstroms, and the width of dielectric layer 28a between the vertical sidewalls of layer 29 is about for the three feature dimensions. The depth of layer 28 is approximately one feature dimension.

Figure 9 shows another embodiment of the invention which is very similar to the embodiment of Figure 8, except that layer 29 of Figure 7 is extended as layer 29a over layer 28a. This extension 29a of layer 29 increases the capacitance of the stack capacitor.

Since the metal layer 31 generally operates at ground potential, other layers operating at ground potential can be connected to it.

It should be understood that the examples described are only for illustration of the invention. Various modifications can be made without departing from the spirit and scope of the invention. For example, a silicon nitride layer may be used between layer 28a, typically silicon oxide, and layer 29, typically platinum, to improve the adhesion of layers 28a, 29 and 29a. In addition, materials other than the above-mentioned materials may be substituted for the above-mentioned materials as long as these other materials have the characteristics of each specific layer used. For example, metals such as iridium, copper, or gold may be used instead of platinum to form capacitors. Barium strontium titanate may be replaced by similar other materials with high dielectric constants. Furthermore, the generally substantially rectangular shape of the contact plug and the cross-section of layer 28a can be selected as desired for ease of manufacture.

Claims (12)

1. A storage unit, comprising: a semiconductor body having a part of its upper surface having first and second regions of one conductivity type separated by an intermediate region of opposite conductivity type for forming a transistor; Capacitors formed on the first region, including: a conductive plug in electrical contact with said first region; forming a conductive layer of a diffusion barrier overlying said plug; a portion of the dielectric layer overlying the barrier layer and overlying the plug; a first metal layer on at least the sidewalls of said dielectric layer, in electrical contact with the barrier layer, serving as an inner plate of a capacitor; a layer of dielectric material conformally surrounding the upper and sidewall surfaces of said dielectric layer portion for use as a capacitor dielectric; and A second metal layer conformally superimposed on said last-mentioned layer of dielectric material serves as the outer plate of the capacitor. 2. The memory cell according to claim 1, wherein the conductive plug is formed of polysilicon doped to one conductivity type. 3. The memory cell of claim 2, wherein both metal layers are composed of platinum. 4. The memory cell according to claim 3, wherein the barrier layer is composed of a material selected from TiN, TaSiN and TiAlN. 5. The memory cell of claim 1, wherein the first metal layer also extends on the upper surface of said dielectric layer. 6. A memory cell according to claim 3, wherein the dielectric layer serving as the capacitor electrode is composed of barium strontium titanate. 7. The memory cell of claim 1, wherein the semiconductor body is silicon. 8. A method of forming a memory cell, comprising the steps of: forming separated source and drain regions of the transistor on the upper surface of the silicon body; forming a dielectric capping layer on the upper surface of the silicon body; forming a contact hole having substantially vertical sidewalls in a portion of the dielectric capping layer overlying a spaced-apart region to be used as a storage node of the cell; filling the contact hole with an electrical conductor, forming a conductive plug to said last-mentioned spaced-off area; forming a conductive barrier layer on the conductive plug; forming a dielectric layer portion on the conductive barrier layer; forming a conductive layer on at least sidewalls of the dielectric layer portion to serve as an inner plate of the storage capacitor; forming a dielectric layer on said last-mentioned conductive layer, the upper part of this dielectric layer being suitable as a dielectric layer for a storage capacitor; and A conductive layer is formed on the dielectric layer to serve as the outer plate of the storage capacitor. 9. The method according to claim 8, wherein the contact hole is formed to have a vertical side wall, and the conductive layer constituting the plate of the capacitor is composed of platinum. 10. The method according to claim 8, wherein the barrier layer is selected from TiN, TaSiN and TiAlN. 11. The method of claim 9, wherein the capacitor dielectric is barium strontium titanate. 12. A method according to claim 8, wherein the semiconductor body is silicon, the conductive plug is polysilicon, the metal layers are platinum, the capacitor dielectric is barium strontium titanate, and the diffusion barrier layer is composed of a material selected from TiN, TaSiN and TiAlN.

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