CN1287452C - Window type ball grid array semiconductor package with lead frame as carrier and its manufacturing method - Google Patents

Abstract

A window-type ball grid array semiconductor package with a lead frame as a chip carrier and a method for fabricating the same are provided. The packaging piece is composed of a plurality of pins, the plurality of pins surround a through hole penetrating through the lead frame, a non-conductive material is laid on the lower surfaces of the pins, and the non-conductive material is exposed out of the lower surfaces of the pins. A chip is arranged on the upper surface of the pin in a mode of covering the through hole, and an electrical region on the action surface of the chip is exposed, so that the chip is electrically connected to the welding wire part of the pin. Forming a packaging colloid on the lead frame, coating the packaging colloid on the upper surface of the pin to coat the chip, and filling the packaging colloid in the through hole of the lead frame to coat the bonding wire; finally, solder balls are planted on the ball planting parts of the pins, and the chips are electrically connected with the outside through the solder balls. The structure does not need to use the existing substrate and solder mask, reduces the cost and complexity of the manufacturing process, and avoids the problems of layering and the like.

Description

Window type ball grid array semiconductor package with lead frame as carrier and its manufacturing method

technical field

The present invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package with a window ball grid array (Window Ball GridArray, WBGA) with a lead frame as a chip carrier (Chip Carrier), and the manufacture of the semiconductor package Method for semiconductor packaging.

Background technique

The feature of the window-type ball grid array semiconductor package is that the substrate used is provided with at least one opening through the substrate, and the chip is placed on a surface of the substrate in a manner covering the opening, and is passed through the opening. The bonding wires in the holes are electrically connected to the substrate, and a plurality of soldering balls are planted on an opposite surface of the substrate, so that the chip can be electrically connected with the outside through the soldering balls. The advantage of this packaging structure is that it is suitable for central pad type (Central-Pad Type) chips to shorten the length of bonding wires and reduce the overall thickness of the package.

This existing windowed ball grid array package structure is as shown in FIG. 6A, which uses a substrate 10 with upper and lower surfaces 100, 101, and opens an opening 102 through the substrate 10 in the substrate 10 for supplying A chip 11 is placed on the upper surface 100 of the substrate 10 in a face-down (Face-Down) manner, and covers a port of the opening 102, so that the bonding pad 111 formed on the active surface 110 of the chip 11 It is exposed in the opening 102 of the substrate 10 for a plurality of bonding wires 12 to pass through the opening 102 to electrically connect the bonding pad 111 of the chip 11 to the lower surface 101 of the substrate 10 . Then, form an encapsulant 13, 14 on the upper and lower surfaces 100, 101 of the substrate 10, respectively, so that the lower encapsulant 13 on the lower surface 101 fills the opening 102 of the substrate 10 and covers the bonding wire 12, and Make the upper packaging compound 14 on the upper surface 100 cover the chip 11; then, plant a plurality of solder balls 15 on the lower surface 101 of the substrate 10 without affecting the area of the lower packaging compound 13, so that the solder balls 15 can be used as input/ The output (Input/Output, I/O) terminal is used to electrically connect the chip 11 to an external device, such as a printed circuit board (Printed Circuit Board, not shown). Related prior art such as U.S. Patent No. 5,920,118, 6,144,102, 6,190,943 and 6,218,731 case etc.; wherein, U.S. Patent No. 5,920,118 case uses a ceramic substrate (Ceramic Substrate) as the chip carrier, and U.S. Patent No. 6,144,102, 6,190,943, 6,218,731 The numbered proposal is to use a substrate made of organic material (such as BT resin, etc.) for mounting chips; however, the manufacturing cost of this ceramic substrate and organic substrate is extremely high, thus greatly increasing the production cost of the package.

Taiwan Patent Announcement No. 411537 is a windowed ball grid array packaging structure with a lead frame as a chip carrier, wherein the lead frame is composed of a plurality of pins, so that the chip is connected to one surface of the pins, On the opposite surface of the pin, a Solder Mask is laid, and a plurality of openings are opened through the solder mask so that the preset ball planting position on the pin can be exposed through the opening, so that the solder ball can be planted on the pin. The exposed bulb site. However, this packaging structure has many disadvantages; one is that the process of applying solder repellant to the pins is extremely complicated and costly, and at the same time, it is difficult to implement solder repellant in the gaps between adjacent pins. Furthermore, due to the high hygroscopicity of the solder repellant, the solder repellant deposited on the pins is easy to accumulate moisture, resulting in delamination at the interface between the solder repellent and the pins.

In addition, the above-mentioned semiconductor packaging structure using a substrate or a lead frame is also prone to adhesive overflow problems. Taking the packaging structure of FIG. 6A as an example, when a molding process is performed to form the upper packaging compound 14 and the lower packaging compound 13 on the substrate 10, as shown in FIG. The substrate 10 is placed in an encapsulation mold 16, which is composed of an upper mold 17 and a lower mold 18, so that the substrate 10 is sandwiched between the upper and lower molds 17, 18, wherein the upper mold 17 forms a mold capable of holding The upper cavity 170 of the chip 11 is placed, and the lower mold 18 is provided with a lower cavity 180 corresponding to the opening 102 of the substrate 10, so that the arc of the welding wire 12 can be accommodated in the lower cavity 180; when a resin When materials (such as epoxy resin, etc.) are injected into the mold 16, the resin material will fill in the upper cavity 170 and the lower cavity 180, thereby forming the upper encapsulation compound 14 and the lower encapsulation compound 13 to cover the chip 11 and the bonding wire 12 respectively. . However, since the area of the upper cavity 170 covering the substrate 10 is larger than that of the lower cavity 180, the area NC (meaning "non-clamping", Non-Clamping) on the lower surface 101 of the substrate 10 adjacent to the lower encapsulant 13 lacks The clamping force (Clamping Force) of the mold 17 makes the resin material very easy to spill glue onto the lower surface 101 of the substrate 10, so that the preset ball planting position on the lower surface 101 of the substrate 10 is also polluted by overflow glue (as shown in FIG. 6C As shown by the arrow), the solder balls 15 subsequently planted at the ball planting site cannot be completely soldered to the substrate 10, thereby affecting the electrical connection quality of the finished product.

Therefore, how to solve the above problems and provide a semiconductor packaging structure that reduces costs, prevents delamination and avoids glue overflow is a problem that needs to be solved.

Contents of the invention

In order to overcome the deficiencies of the above-mentioned prior art, the main purpose of the present invention is to provide a kind of open-type ball grid array semiconductor package with lead frame as chip carrier and its manufacturing method, which does not need to use high-cost substrate as chip carrier components, which can greatly reduce the manufacturing cost of the semiconductor package.

Another object of the present invention is to provide a windowed ball grid array semiconductor package with a lead frame as a chip carrier and its manufacturing method. It lays a non-conductive (Non-Conductive) resin material on the lead frame to replace the commonly used The excellent solder repellant can eliminate the defect of delamination between the solder repellant and the lead frame, and ensure the reliability of the semiconductor package.

Another object of the present invention is to provide a windowed ball grid array semiconductor package with a lead frame as a chip carrier and its manufacturing method, which can avoid glue overflow in the wire bonding area and ball planting area on the lead frame , so that the welding wire and the solder ball can be electrically and completely planted to the welding wire area and the ball planting area, ensuring the electrical quality and excellent rate of the finished product.

Another object of the present invention is to provide a windowed ball grid array semiconductor package with a lead frame as a chip carrier and its manufacturing method, which can be completed using existing manufacturing processes, so the complexity of the manufacturing process will not be increased.

In order to achieve the above and other objects, a windowed ball grid array semiconductor package using a lead frame as a chip carrier of the present invention includes: a lead frame, which is composed of a plurality of pins, so that the plurality of pins surround a Through the through hole of the lead frame, each pin has an end facing the through hole, and each pin has an upper surface and an opposite lower surface, wherein the lower surface of each pin defines a soldering portion and A ball-planting part; a first non-conductive resin material, laid on the lower surface and the end of the pin, so that the first non-conductive resin material is exposed outside the wire-bonding part and the ball-planting part of the pin; at least one chip , has an active surface and an opposite non-active surface, so that the active surface of the chip is connected to the upper surface of the pin and covers a port of the through hole of the lead frame, so that the electrical area of the active surface is exposed to the through hole middle; a plurality of bonding wires that run through the through holes of the lead frame to electrically connect the electrical area of the chip to the bonding wire portion of the pin; a packaging compound is formed on the lead frame, so that the packaging compound has a first part and a The second part, wherein the first part is applied to the upper surface of the pin to cover the chip, and the second part of the encapsulant is filled in the through hole of the lead frame to cover the bonding wire; and a plurality of solder balls, Planted on the ball planting part of the tube foot.

A method for manufacturing a windowed ball grid array semiconductor package with a lead frame as a chip carrier is realized in the following way: a lead frame is prepared, the lead frame is composed of a plurality of pins, and the plurality of pins surround a Each of the pins has an end facing the through hole, and each of the pins has an upper surface and an opposite lower surface, wherein a solder joint is defined on the lower surface of each of the pins. wire part and a ball planting part, and a first non-conductive resin material is laid on the lower surface and the end of the pin, so that the first non-conductive resin material is exposed from the wire bonding part and the ball planting part Prepare at least one chip, the chip has an active surface and an opposite non-active surface, and connect the active surface of the chip on the upper surface of the pin, so that the active surface covers a through hole of the lead frame port, so that the electrical area of the active surface is exposed in the through hole; forming a plurality of bonding wires penetrating through the through hole, so as to electrically connect the electrical area of the chip to the pin through the bonding wire Welding part; forming a packaging glue on the lead frame, so that the packaging glue has a first part and a second part, wherein the first part is laid on the upper surface of the pin to cover the chip, and the packaging glue has a first part and a second part. The second part is filled in the through hole to cover the bonding wire; and planting a plurality of solder balls on the ball planting part of the pin.

In another embodiment, a second non-conductive resin material can be laid on the upper surface of the pin, so that the active surface of the chip is connected to the second non-conductive resin material, so that the second non-conductive resin The material is sandwiched between the chip and the lead frame; and the upper surface of each pin defines a corresponding portion for bonding wire and a corresponding portion for planting balls, so that the corresponding portion for bonding wires and the corresponding portion for planting balls correspond to the bottom of the pins respectively. The wire-bonding portion and the ball-planting portion on the surface, wherein the wire-bonding corresponding portion and the ball-planting corresponding portion expose the second non-conductive resin material, and the second non-conductive resin material and the first non-conductive resin material It may be the same resin material.

The above-mentioned semiconductor package structure can provide many advantages; one is that the lead frame is used as the chip carrier without using existing high-cost substrates (such as ceramic substrates, organic substrates, etc.), so the manufacturing cost of the overall package can be effectively reduced. Furthermore, the surface of the pins of the lead frame is laid with a non-conductive resin material instead of the existing solder repellant; compared with the solder repellant, the non-conductive material has better bonding with the pins, and its moisture absorption The hygroscopicity is much smaller than the hygroscopicity of the solder repellant, so there will be no delamination between the non-conductive material and the pins; at the same time, the laying of the non-conductive material is completed when the lead frame is prepared, so there will be no increase in the package The complexity and cost of the process. In addition, in the process of laying non-conductive materials, the pins of the lead frame can be tightly clamped in the mold, so that the preset wire bonding parts and ball planting parts on the pins can obtain moderate clamping force from the mold, making the non-conductive The non-reactive material will not overflow the glue to the wire bonding part and the ball planting part, so that the soldering wire and the solder ball can be completely welded on the wire bonding part and the ball planting part, and the electrical connection quality and excellent quality of the semiconductor package can be ensured. Rate.

Description of drawings

1A is a cross-sectional view of a semiconductor package according to Embodiment 1 of the present invention;

FIG. 1B is a bottom view showing the first non-conductive material exposed from the wire bonding portion and the ball mounting portion of the lead frame in the semiconductor package shown in FIG. 1A;

2A to 2E are schematic diagrams of the manufacturing process of the semiconductor package according to Embodiment 1 of the present invention;

3A is a cross-sectional view of a semiconductor package according to Embodiment 2 of the present invention;

3B is a schematic diagram showing the process of preparing a lead frame in the semiconductor package shown in FIG. 3A;

FIG. 3C is a top view showing the second non-conductive material exposed outside the wire-bonding corresponding portion and the ball-planting corresponding portion of the lead frame shown in FIG. 3B;

4 is a cross-sectional view of a semiconductor package according to Embodiment 3 of the present invention;

5A is a cross-sectional view of a semiconductor package according to Embodiment 4 of the present invention;

FIG. 5B shows a package structure formed by stacking the semiconductor packages shown in FIG. 5A;

6A is a cross-sectional view of a conventional semiconductor package;

FIG. 6B is a schematic diagram showing a molding process for forming an encapsulant in the semiconductor package shown in FIG. 6A; and

FIG. 6C is a schematic diagram showing glue overflow when forming the encapsulant in the semiconductor package shown in FIG. 6B .

Detailed ways

1A to FIG. 1B, FIG. 2A to FIG. 2E, FIG. 3A to FIG. 3C, FIG. 4 and FIG. 5A to FIG. 5B, the windowed ball grid array using the lead frame as the chip carrier (Chip Carrier) of the present invention will be described. (Window Ball Grid Array, WBGA) semiconductor package and its manufacturing method.

Example 1

As shown in FIG. 1A, the windowed ball grid array semiconductor package of the present invention uses a lead frame 20 as a chip carrier for carrying chips. The lead frame 20 is composed of a plurality of pins 200, so that the plurality of pins The pins 200 surround a through hole 201 through the lead frame 20, wherein each pin 200 has an end 202 facing the through hole 201, and has an upper surface 203 and an opposite lower surface 204, and each pin A wire-bonding portion 205 and a ball-implanting portion 206 are defined on the lower surface 204 of the 200 . A first non-conductive material 21 is laid on the lower surface 204 and the end portion 202 of the pin 200, so that the first non-conductive material 21 is exposed from the wire bonding portion 205 and the ball-planting portion 206 on the lower surface 204, As shown in Figure 1B. At least one chip 22 is connected on the lead frame 20 in a manner covering a port of the through hole 201; on the upper surface 203 of the pin 200, and make the electrical region 222 of the active surface 220 exposed in the through hole 201 of the lead frame 20, thereby exposing the pad 223 arranged on the electrical region 222; at the same time, the chip 22 is A plurality of welding wires 23 penetrating through the through hole 201 are electrically connected to the lead frame 20, wherein the welding wires 23 are welded to the welding pads 223 of the chip 22 and the welding wire parts 205 of the pins 200, and the welding wires 23 are connected to The active surface 220 of the chip 22 is electrically connected to the pin 200 . An encapsulant 24 is laid on the lead frame 20 to form a first part 240 and a second part 241, the first part 240 is laid on the upper surface 203 of the pin 200 to cover the chip 22, and the second part of the encapsulant 24 241 is filled in the through hole 201 of the lead frame 20 to cover the bonding wire 23 . The semiconductor package is also implanted with a plurality of solder balls 25 on the ball-planting portion 206 of the pin 200 , serving as an input/output (I/O) terminal of the semiconductor package to form an electrical connection with the outside world.

The above-mentioned semiconductor package can be manufactured according to the process steps shown in FIG. 2A to FIG. 2E ; the following manufacturing method is to manufacture the semiconductor package in batch mode, but the present invention is not limited thereto.

First, as shown in FIG. 2A , a lead frame sheet 2 is prepared, which is formed by integrating a plurality of lead frames 20 (adjacent lead frames 20 are separated by dotted lines in the figure), and each lead frame 20 is composed of a plurality of pins 200 , and the plurality of pins 200 surround a through hole 201 through the lead frame 20; wherein, each pin 200 has an end 202 facing the through hole 201, and has an upper surface 203 and an opposite lower surface 204 , and the lower surface 204 of each pin 200 defines a wire bonding portion 205 and a ball mounting portion 206 .

As shown in Figure 2B, a pre-molding (Pre-Molding) process is carried out, and the lead frame sheet 2 is placed in a prefabricated mold 26. The mold 26 is composed of an upper mold 260 and a lower mold 261, so that the lead frame sheet 2 is clamped Placed between the upper mold 260 and the lower mold 261, wherein the upper surface 203 of the pin 200 is in contact with the bottom surface 262 of the upper mold 260; 205′, the convex portion 206′ corresponding to the ball planting portion 206, and the convex portion 264 corresponding to the through hole 201 of the lead frame 20, and the size of the convex portion 264 is smaller than the size of the through hole 2C1, and the bottom of the pin 200 The surface 204 is in contact with the protrusions 205 ′, 206 ′ and 264 of the lower die 261 .

After the upper mold 260 and the lower mold 260 are closed, the pin 200 is sandwiched between the upper mold 260 and the lower mold 261, so that the wire bonding portion 205 and the ball planting portion 206 of the pin 200 are connected to the top surface 263 of the lower mold 261. The protrusions 205', 206' are in tight contact, while the upper surface 203 of the pin 200 is in tight contact with the bottom surface 262 of the upper mold 260, and the protrusion 264 of the lower mold 261 touches the bottom surface of the upper mold 260 through the through hole 201 262, and there is a gap between the convex portion 264 and the through hole 201; then, a first non-conductive material 21 (such as a resin material) is injected into the mold 26, filling the top surface 263 of the lower mold 261 and the pin 200 In the gap between the lower surface 204 and the gap between the protrusion 264 and the through hole 201, the first non-conductive material 21 will not overflow to the upper surface 203 and the lower surface of the pin 200 which are in close contact with the mold 26. The wire bonding portion 205 and the ball planting portion 206 on the surface 204 make the first non-conductive material 21 only be laid on the lower surface 204 and the end portion 202 of the pin 200, so that the wire bonding portion 205 and the ball planting portion of the pin 200 The portion 206 can expose the first non-conductive material 21 . After the laying of the first non-conductive material 21 is completed, the mold 26 is removed from the lead frame sheet 2, so that the preparation of the lead frame sheet 2 is completed; wherein, the first non-conductive material laid on the lower surface 204 of the pin 200 The flexible material 21 is formed with a predetermined thickness, which depends on the height of the convex parts 205', 206' of the lower mold 261, and needs to form a space with the wire bonding part 205 of the pin 200 enough to accommodate the subsequent wire bonding (not shown). icon) arc (detailed later).

Then, as shown in FIG. 2C , a Die-Bonding operation is performed on the lead frame sheet 2 made above, and at least one chip 22 is connected on each lead frame 20, and the chip 22 has an active surface 220. and a relative non-active surface 221, so that the active surface 220 of the chip 22 is glued on the upper surface 203 of the pin 200 and covers a port of the through hole 201 of the lead frame 20 through an adhesive (not shown), so that the The electrical area 222 of the active surface 220 is exposed in the through hole 201 to expose the pad 223 disposed on the electrical area 222 .

A wire-bonding operation is performed to electrically connect the chip 22 to the lead frame 20 by means of the bonding wire 23 . A plurality of bonding wires 23 penetrating through the through holes 201 are formed in the through holes 201 of each lead frame 20, so that the bonding wires 23 are soldered to the bonding pads 223 of the chip 22 and the bonding wire portions 205 of the pins 200, thereby electrically The active surface 220 of the chip 22 is connected to the lower surface 204 of the pin 200 . Since the first non-conductive material 21 is laid on the end 202 of the pin 200, the welding wire 23 penetrating through the through hole 201 will not touch the end 202 of the pin 200, so no short circuit or poor electrical connection will occur. Phenomenon. Moreover, the first non-conductive material 21 laid on the lower surface 204 of the pin 200 has a predetermined thickness, which is greater than the height of the arc portion of the bonding wire 23 protruding from the lower surface 204 of the pin 200, Therefore, the arc of the welding wire 23 can be conveniently accommodated in the space formed by the first non-conductive material 21 and the welding wire portion 205 .

A molding process is performed to utilize a commonly used packaging mold (not shown) to form an encapsulant 24 (existing resin materials such as epoxy resin can be used) on the lead frame sheet 2, so that the encapsulant 24 has a second A part 240 and a second part 241, wherein the first part 240 of the encapsulant 24 is laid on the upper surface 203 of the pin 200 of the lead frame 20, so as to cover all the chips 22 connected on each lead frame 20, the package The second portion 241 of the glue 24 is filled in the through hole 201 of each lead frame 20 to cover all the bonding wires 23 for electrically connecting the chip 22 to the pin 200 . Since the arc of the bonding wire 23 can be accommodated in the space formed by the first non-conductive material 21 and the bonding wire part 205 of the pin 200, the exposed bottom surface 242 of the second part 241 of the encapsulant 24 can be connected with the first The exposed surface 210 of the non-conductive material 21 is flush, so that the bonding wire 23 can be completely covered by the encapsulant 24 .

Next, as shown in FIG. 2D , a Ball-Implantation process is performed, and a plurality of solder balls 25 are implanted on the ball-implantation portion 206 exposed on the lead frame sheet 2, so that the height of the solder balls 25 is greater than that laid on the pins. 200 is the thickness of the first non-conductive material 21 on the lower surface 204 .

Finally, all single operations are performed to cut the encapsulant 24, the lead frame sheet 2 and the first non-conductive material 21 along the cutting line (arrow direction shown in FIG. 2D ), so as to separate each lead frame 20 into a plurality of independent semiconductors. package, as shown in Figure 2E. In this way, the manufacturing process of the semiconductor package according to Embodiment 1 of the present invention is completed, wherein the exposed solder balls 25 are used as the input/output terminals of the semiconductor package, so that the chip 22 can be connected to external devices such as a printed circuit board (not shown). ) into an electrical connection.

Example 2

FIG. 3A shows a semiconductor package according to Embodiment 2 of the present invention. The components of this semiconductor package are substantially the same as those of the first embodiment, so the same components are denoted by the same reference numerals.

As shown in FIG. 3A , the difference between the semiconductor package of this embodiment and the above-mentioned Embodiment 1 is that a second non-conductive material 27 is laid on the upper surface 203 of the pin 200, and it can be connected with the pin 200. The first non-conductive material 21 on the lower surface 204 is the same resin material, and is formed simultaneously with the first non-conductive material 21 when the lead frame 20 is prepared; moreover, the upper surface 203 of each pin 200 also has A wire-bonding corresponding portion 207 and a ball-planting corresponding portion 208 are defined, which respectively correspond to the wire-bonding portion 205 and the ball-planting portion 206 on the lower surface 204 of the pin 200 . In the above-mentioned pre-molding process, as shown in FIG. 3B , the lead frame 20 is sandwiched between the upper mold 260 and the lower mold 261 of the mold 26, and the bottom surface 262 of the upper mold 260 is formed with a plurality of corresponding parts corresponding to the welding wires. 207's convex portion 207' and the convex portion 208' corresponding to the ball planting corresponding portion 208; therefore, when the pre-molding process is carried out, the wire bonding corresponding portion 207 and the ball planting corresponding portion 208 on the upper surface 203 of the pin 200 are in line with the upper surface The convex portion 207 ′ of the bonding wire corresponding portion of the mold 260 and the convex portion 208 ′ of the ball planting corresponding portion are closely connected, so that the second non-conductive material 27 injected into the mold 26 is filled on the bottom surface 262 of the upper mold 260 and on the pin 200 In the gap between the surfaces 203, the glue will not overflow to the bonding wire corresponding part 207 and the ball planting corresponding part 208 closely connected with the mold 26, so that the bonding wire corresponding part 207 and the ball planting corresponding part 208 can expose the second non-conductive Sexual material 27, as shown in Figure 3C. Since the second non-conductive material 27 and the first non-conductive material 21 are the same resin material, the first non-conductive material 21 and the second non-conductive material 27 can be laid on the lead frame 20 through the mold 26 at the same time, The upper and lower surfaces 203, 204 of the pin 200 of the prepared lead frame 20 are laid with the second non-conductive material 27 and the first non-conductive material 21 respectively, and the end 202 of the pin 200 is coated with the first non-conductive material. The coating of the conductive material 21 enables the fabricated lead frame 20 to undergo a subsequent process (as shown in FIG. 3A ).

Next, at least one chip 22 is placed on the lead frame 20, so that the active surface 220 of the chip 22 is bonded to the upper surface 203 on which the pin 200 of the second non-conductive material 27 is laid in a manner covering the through hole 201. , the chip 22 is electrically connected to the bottom surface 204 of the pin 200 by a plurality of bonding wires 23 penetrating through the through hole 201 .

Then, an encapsulant 24 is formed on the lead frame 20, so that the first part 240 of the encapsulant 24 is formed on the second non-conductive material 27 on the upper surface 203 of the pin 200, so as to cover the chip 22 and cover the pin 200. The bonding wire corresponding portion 207 and the ball planting corresponding portion 208 , and the second portion 241 of the encapsulant 24 is filled in the through hole 201 of the lead frame 20 to cover the bonding wire 23 .

Finally, planting a plurality of solder balls 25 on the ball planting portion 206 on the lower surface 204 of the pin 200 completes the semiconductor package of this embodiment.

The semiconductor package described in the above-mentioned embodiment 1 and embodiment 2 has many advantages; one is that the lead frame is used as the chip carrier, and there is no need to use existing high-cost substrates (such as ceramic substrates, organic substrates, etc.), so it can effectively Reduce the manufacturing cost of the overall package. Furthermore, the surface of the pins of the lead frame is laid with non-conductive resin material instead of the existing solder repellant; compared with the solder repellent, the non-conductive material has better combination with the pins, and its The hygroscopicity is much smaller than that of solder repellent, so there will be no delamination between the non-conductive material and the pins; at the same time, the laying of the non-conductive material is completed when the lead frame is prepared, so there will be no increase in the package The complexity and cost of the process. In addition, in the process of laying non-conductive materials, the pins of the lead frame can be tightly clamped in the mold, so that the preset wire bonding parts and ball planting parts on the pins can obtain moderate clamping force from the mold, making the non-conductive The non-reactive material will not spill glue to the soldering wire and the ball-planting part, so that the soldering wire and the solder ball can be completely welded on the soldering wire and the ball-planting part, thereby ensuring the electrical connection quality and quality of the semiconductor package produced. Excellent rate.

Example 3

FIG. 4 shows a semiconductor package according to Embodiment 3 of the present invention. The components of this semiconductor package are substantially the same as those of the above-mentioned embodiment 1, so the same components are denoted by the same reference numerals.

As shown in FIG. 4 , the difference between the semiconductor package of this embodiment and the above-mentioned Embodiment 1 is that the non-active surface 221 of the chip 22 is not covered with the first part 240 of the encapsulant 24 and is exposed (that is, the bare crystal type Package), so that the non-active surface 221 is in direct contact with the outside, so that the heat generated by the operation of the chip 22 can be dissipated to the outside through the exposed non-active surface 221, thereby improving the heat dissipation efficiency of the semiconductor package.

Example 4

FIG. 5A shows a semiconductor package according to Embodiment 4 of the present invention. The components of this semiconductor package are substantially the same as those of the above-mentioned embodiment 2, so the same components are denoted by the same reference numerals.

As shown in FIG. 5A , the difference between the semiconductor package of this embodiment and the above-mentioned Embodiment 2 is that: the first part 240 of the encapsulant 24 laid on the upper surface 203 of the pin 200 completely covers the chip 22, but the The bump corresponding portion 208 on the upper surface 203 of the pin 200 exposes the encapsulant 24 , and the position where the solder ball 25 is disposed corresponds to the bump corresponding portion 208 . This kind of semiconductor package can be stacked up and down, and can be made into a package structure as shown in Figure 5B, wherein the upper and lower connected semiconductor packages make the solder balls 25 of the upper semiconductor package contact to the lower semiconductor package exposed The corresponding portion 208 of the ball planting can be electrically connected to each other, and the operation function of the overall package structure can be improved; in addition, the bare crystal semiconductor package shown in Embodiment 3 can also be applied to the stacked package shown in FIG. 5B structure.

Claims (25)

1. one kind is the open window type ball grid array semiconductor packaging piece of chip bearing member with the lead frame, it is characterized in that this semiconductor package part comprises:

One lead frame is made of many pins, makes these many pins around a through hole that runs through lead frame, respectively this pin has an end towards this through hole, and respectively this pin has a upper surface and an opposing lower surface, wherein, respectively defines a bonding wire portion and on the lower surface of this pin and plants the bulb;

One first non-conductive resin material lays to the lower surface and end of this pin, and makes this bonding wire portion and plant the bulb and expose outside this first non-conductive resin material;

At least one chip has an action face and a relative non-action face, this action face is connect put on the upper surface of this pin, and cover a port of the through hole of this lead frame, makes the electrical areas of this action face expose in this through hole;

Many the bonding wires in this through hole are in order to the electrical areas that electrically connects this chip bonding wire portion to this pin;

One packing colloid is formed on this lead frame, makes this packing colloid have first and second portion, and wherein, this first lays to the upper surface of this pin coating this chip, and this second portion is to be filled in this through hole to coat this bonding wire; And

A plurality of soldered balls plant the bulb of planting in this pin.

2. open window type ball grid array semiconductor packaging piece as claimed in claim 1, it is characterized in that, this semiconductor package part also comprises: one second non-conductive resin material, lay to the upper surface of this pin, the action face of this chip is connect to be placed on this second non-conductive resin material, make this second non-conductive resin material be interposed between this chip and this lead frame, and coated by the first of this packing colloid.

3. open window type ball grid array semiconductor packaging piece as claimed in claim 2, it is characterized in that, respectively define a bonding wire correspondence portion and on the upper surface of this pin and plant ball correspondence portion, make this bonding wire correspondence portion and plant the ball counterpart, and make this bonding wire correspondence portion and plant ball correspondence portion and expose outside this second non-conductive resin material not corresponding to this bonding wire portion respectively and plant the bulb.

4. open window type ball grid array semiconductor packaging piece as claimed in claim 2 is characterized in that, this first non-conductive resin material is identical with this second non-conductive resin material.

5. open window type ball grid array semiconductor packaging piece as claimed in claim 1 is characterized in that, the electrical areas of this chip is laid with many weld pads to be connected with this bonding wire.

6. open window type ball grid array semiconductor packaging piece as claimed in claim 1 is characterized in that, the thickness that lays the first non-conductive resin material to the lower surface of this pin protrudes in the height of the bank part on the lower surface of this pin greater than this bonding wire.

7. open window type ball grid array semiconductor packaging piece as claimed in claim 1 is characterized in that, the second portion of this packing colloid has one and exposes the bottom surface, makes this expose the bottom surface and flushes with the exposed surface of this first non-conductive resin material.

8. open window type ball grid array semiconductor packaging piece as claimed in claim 1 is characterized in that, the non-action face of this chip is to expose outside this packing colloid.

9. open window type ball grid array semiconductor packaging piece as claimed in claim 3, it is characterized in that, this is planted ball correspondence portion and exposes outside this packing colloid, many these semiconductor package parts can be spliced up and down, and make the soldered ball of upper strata semiconductor package part touch the ball correspondence portion of planting of exposing to lower floor's semiconductor package part.

10. one kind is the method for making of the open window type ball grid array semiconductor packaging piece of chip bearing member with the lead frame, it is characterized in that this method for making comprises the following steps:

Prepare a lead frame, this lead frame is made of many pins, make these many pins around a through hole that runs through lead frame, respectively this pin has an end towards this through hole, and respectively this pin has a upper surface and an opposing lower surface, wherein, respectively defines a bonding wire portion and on the lower surface of this pin and plants the bulb, and on the lower surface of this pin and end, lay one first non-conductive resin material, expose outside this first non-conductive resin material and make this bonding wire portion and plant the bulb;

Prepare at least one chip, this chip has an action face and a relative non-action face, and connect put this chip action face on the upper surface of this pin, make this action face cover a port of the through hole of this lead frame, and make the electrical areas of this action face expose in this through hole;

Form many bonding wires in this through hole, electrically connect the bonding wire portion of the electrical areas of this chip to this pin to borrow this bonding wire;

Form a packing colloid on this lead frame, and make this packing colloid have first and second portion, wherein, this first lays to the upper surface of this pin coating this chip, and this second portion is to be filled in this through hole to coat this bonding wire; And

Plant the plant bulb of a plurality of soldered balls in this pin.

11. method for making as claimed in claim 10, it is characterized in that, the step of this preparation lead frame also comprises lays one second non-conductive resin material to the upper surface of this pin, place on this second non-conductive resin material so that the action face of this chip connects, and make this second non-conductive resin material be interposed between this chip and this lead frame.

12. method for making as claimed in claim 11, it is characterized in that, respectively define a bonding wire correspondence portion and on the upper surface of this pin and plant ball correspondence portion, make this bonding wire correspondence portion and plant the ball counterpart not corresponding to this bonding wire portion respectively and plant the bulb, and make this bonding wire correspondence portion and plant ball correspondence portion to expose outside this second non-conductive resin material, and coated by the first of this packing colloid.

13. method for making as claimed in claim 11 is characterized in that, this first non-conductive resin material is to be same as this second non-conductive resin material.

14. method for making as claimed in claim 11 is characterized in that, laying of this first and second non-conductive resin material is to finish with press moulding mode.

15. method for making as claimed in claim 10 is characterized in that, the electrical areas of this chip is laid with many weld pads to be connected with this bonding wire.

16. method for making as claimed in claim 10 is characterized in that, the thickness that lays the first non-conductive resin material to the lower surface of this pin is the height that protrudes in the bank part on the lower surface of this pin greater than this bonding wire.

17. method for making as claimed in claim 10 is characterized in that, the second portion of this packing colloid has one and exposes the bottom surface, this is exposed outside bottom surface and this first non-conductive resin material reveal flush.

18. method for making as claimed in claim 10 is characterized in that, the non-action face of this chip is to expose outside this packing colloid.

19. method for making as claimed in claim 12, it is characterized in that, this is planted ball correspondence portion and exposes outside this packing colloid, so that many these semiconductor package parts can splice up and down, and makes the soldered ball of upper strata semiconductor package part touch the ball correspondence portion of planting of revealing to lower floor's semiconductor package part.

20. one kind is the method for making of the open window type ball grid array semiconductor packaging piece of chip bearing member with the lead frame, it is characterized in that this method for making comprises the following steps:

Prepare a lead frame, this lead frame is made of many pins, and make these many pins around a through hole that runs through lead frame, respectively this pin has an end towards this through hole, and respectively this pin has a upper surface and an opposing lower surface, wherein, respectively define a bonding wire portion and on the lower surface of this pin and plant the bulb, and respectively define a bonding wire correspondence portion and on the upper surface of this pin and plant ball correspondence portion, make this bonding wire correspondence portion and plant the ball counterpart not corresponding to this bonding wire portion respectively and plant the bulb, make a non-conductive resin material lay upper surface to this pin, on lower surface and the end, and make this bonding wire portion, plant the bulb, bonding wire correspondence portion and plant ball correspondence portion and expose outside this non-conductive resin material;

Prepare at least one chip, this chip has an action face and a relative non-action face, and connect put this chip action face on the non-conductive resin material of the upper surface of this pin, make this action face cover a port of the through hole of this lead frame, and make the electrical areas of this action face expose in this through hole;

Form many bonding wires in this through hole, electrically connect the bonding wire portion of the electrical areas of this chip to this pin to borrow this bonding wire;

Form a packing colloid to this lead frame, and make this packing colloid have first and second portion, wherein, this first lays to the non-conductive resin material of the upper surface of this pin coating this chip, and this second portion is to be filled in this through hole to coat this bonding wire; And plant the plant bulb of a plurality of soldered balls in this pin.

21. method for making as claimed in claim 20 is characterized in that, the electrical areas of this chip is laid with many weld pads to be connected with this bonding wire.

22. method for making as claimed in claim 20 is characterized in that, the thickness that lays the non-conductive resin material to the lower surface of this pin is the height that protrudes in the bank part on the lower surface of this pin greater than this bonding wire.

23. method for making as claimed in claim 20 is characterized in that, the second portion of this packing colloid has one and exposes the bottom surface, this is exposed outside bottom surface and this non-conductive resin material reveal flush.

24. method for making as claimed in claim 20 is characterized in that, the non-action face of this chip is to expose outside this packing colloid.

25. method for making as claimed in claim 20, it is characterized in that, this is planted ball correspondence portion and exposes outside this packing colloid, so that many these semiconductor package parts can splice up and down, makes the soldered ball of upper strata semiconductor package part touch the ball correspondence portion of planting of revealing to lower floor's semiconductor package part.

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