CN1285175C - Output wave filter for delta-sigma modulator and digital signal processor with the same output filter - Google Patents
Output wave filter for delta-sigma modulator and digital signal processor with the same output filter Download PDFInfo
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- CN1285175C CN1285175C CNB2003101209054A CN200310120905A CN1285175C CN 1285175 C CN1285175 C CN 1285175C CN B2003101209054 A CNB2003101209054 A CN B2003101209054A CN 200310120905 A CN200310120905 A CN 200310120905A CN 1285175 C CN1285175 C CN 1285175C
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000001914 filtration Methods 0.000 claims description 3
- 230000003111 delayed effect Effects 0.000 claims description 2
- 238000005755 formation reaction Methods 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/0283—Filters characterised by the filter structure
- H03H17/0286—Combinations of filter structures
- H03H17/0289—Digital and active filter structures
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
- H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
- H03M3/504—Details of the final digital/analogue conversion following the digital delta-sigma modulation the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H15/00—Transversal filters
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Networks Using Active Elements (AREA)
Abstract
In the digital signal processor, an FIR 4 whose current source is constant current sources 8a and 8b is used, output data from a delta-sigma modulator are taken out from each tap of a shift register S, MOS transistors T<SB>1</SB>-T<SB>n</SB>are controlled by taken-out delay signals, currents weighted by an FIR filter coefficient corresponding to the number of taps are obtained from the constant current sources 8a and 8b, the obtained currents are added, and the current/voltage conversion of the current obtained in such a manner is performed in the feedback resistor 6b of an all differential operational amplifier 6a.
Description
Technical field
The present invention relates to the output filter (postfilter) of the delta-sigma modulator that in the digital signal processing device of for example portable phone, PDA, music playback amplifier etc., uses, and the digital signal processing device that possesses this filter.
Background technology
Now, in the field of digital audio etc., from simplifying input and output, can using the door number of less arithmetic unit to carry out the angle of computing, available simple system composition etc., handle after by delta-sigma modulator multiple bit digital signal being quantified as 1 bit.
As everyone knows, delta-sigma modulator is by the bass boost integrator of input stage configuration at sigma modulator, simultaneously at a bass decay of output stage configuration differentiator, quantizing noise is focused on the high-frequency domain end, can obtain to improve the effect of noise reduction of the signal to noise ratio of audio-band.
The quantized data (" 1 " or " 0 ") of 1 bit that is quantized by delta-sigma modulator through being input on the output filter 1 of next stage after the D/A conversion, after this removes high-frequency noise, can obtain good reproduction waveform.
Fig. 2 is the exemplary circuit figure of this output filter (active filter) 1, and its formation is that the quantized data of 1 bit that generates in delta-sigma modulator 2 is exported after by the D/A conversion, and this output is input in the active filter 1.
At this, in order to improve the performance of delta-sigma modulator, the number of times that need be used in the noise filter in this modulator is a high order, therefore, behind the number of times that has improved this filter, correspondingly, will increase through the quantizing noise of noise reduction.In order to remove this noise, require the high-frequency cut-off characteristic of output filter 1 more precipitous, therefore, output filter 1 shown in Figure 2 also is necessary for high order.
That is to say that the dateout of delta-sigma modulator though export, in this structure, does not improve the number of times of output filter after output filter shown in Figure 21 has been removed the high-frequency noise composition, just can not remove noise contribution fully.
But behind the number of times that has improved output filter (active filter) 1, resistance value correspondingly can increase, and has the problem that noise level is worsened because of impedance.
So, in order to improve such situation, proposed output filter and used the FIR filter, improve the scheme of the characteristic of filter.
Circuit shown in Figure 3 though be not the output filter shown in Figure 2 (active filter) of patent documentation by changing, uses the FIR filter as output filter, makes the performance of filter be improved.
That is to say, the dateout after the D/A conversion that delta-sigma modulator 2 is generated, corresponding to a plurality of flip-flop circuits (F/F) F1, F2 by FIR filter 4 ... each tap of the shift register S that Fn formed postpones, according to this delayed data control MOS triode T1 ... Tn, carry out current-voltage conversion with the resistance 7a, the 7b that are connected on the current source, obtain the voltage that is weighted with the FIR filter factor, it is carried out output from the output circuit 5 that LPF constitutes after the sum operation.
In this circuit, so cause is that FIR filter 4 filter characteristics are improved, but in this FIR filter 4, be to use resistance 7a, the conversion that 7b carries out current/voltage to its current source obtain the structure of fixed voltage, therefore, except because of at resistance 7a, the last electric current of 7b flows through generation heat and takes place beyond the noise, as shown in the figure, the resistance value of the application circuit (accessory circuit) of the operational amplifier 5a of the output circuit 5 of LFP (low pass filter) structure is big, this part also produces much noise because of resistance, and, in operational amplifier 5a because of removing the noise of homophase, even, but still exist with regard to generally its noise level can not improved problem so the characteristic of filter improves.
In addition, though exist to use the FIR filter be non-existent as scheme (referring to the patent documentation 1) formation of the present invention of the output filter of delta-sigma modulator.
Patent documentation 1: the spy opens flat 7-74643 communique
Summary of the invention
The present invention proposes for the prior art problems under the situation that solves above-mentioned delta-sigma modulator use FIR filter, its first purpose is: have in output filter in the FIR filter, reduce the resistance value of this output filter, thereby reduce the thermal noise that produces because of resistance.
Second purpose is: carry out the conversion of current/voltage with the feedback resistance of operational amplifier, to reduce the resistance value of output filter.
The 3rd purpose is: by use full differential operational amplifier in the current-voltage conversion portion of output filter, remove the homophase The noise.
The output filter of one of the present invention's delta-sigma modulator, possess: by making dateout, outputing to each in a plurality of delay elements that are cascaded from delta-sigma modulator, export, control electric current according to each from current source, obtain electric current with the filtering characteristic weighting, and this electric current carried out exporting after the add operation, the FIR filter, it is characterized in that: described current source is a constant-current source.
The output filter of the present invention's two delta-sigma modulator is on one of the present invention's basis, in output one side of described FIR filter, has the current-voltage conversion portion that carries out the current/voltage conversion with the feedback resistance of full differential operational amplifier.
The output filter of the present invention's three delta-sigma modulator is on the present invention's two basis, in output one side of described full differential operational amplifier, has differential single translation operation amplifier.
The present invention's four digital signal processing device possesses: one of the present invention to three in the output filter of each described delta-sigma modulator.
Description of drawings
Fig. 1 has represented the circuit diagram of an example of the output filter of delta-sigma modulator of the present invention.
Fig. 2 is the circuit diagram of output filter of the delta-sigma modulator of prior art.
Fig. 3 is the circuit diagram of output filter of another delta-sigma modulator of prior art.
Among the figure: the 1-output filter; 2-delta-sigma modulator: 4-analog fir filter; The 5-output circuit; 6-current-voltage conversion portion; 7a, 7b-current source resistance; 8a, 8b-constant-current source.
Embodiment
The present invention will be described with reference to the accompanying drawings.
Fig. 1 is an example schematic diagram of delta-sigma modulator of the present invention.
As shown in the figure, from the output (through the D/A conversion) of delta-sigma modulator 2, be input to a plurality of bistable circuits (F/F) F1 of the shift register S of the FIR filter 4 that constitutes output filter 1, F2 ... among the elementary F/F (F1) among the Fn.The output of delta-sigma modulator 2 postpones at each F/F place, with its Q output, after paraphase Q output is taken out, is applied to the MOS triode T1 with the constant-current source cascade, T1 ' from each tap ... on each control terminal of Tn, Tn '.
MOS triode T1, T1 ' ... Tn, Tn ' are according to described each F/F (F1, F2 ... Fn) Q output or paraphase Q output are carried out conducting control to the electric current that comes from constant-current source 8a, 8b.Like this, come from the electric current output of constant- current source 8a, 8b, be weighted with the filter factor of FIR filter, and carry out exporting after the add operation.
The output of the electric current of FIR filter 4 is transformed to voltage in be connected the current-voltage conversion portion 6 that feedback resistance 6b, 6b between its input/output terminal formed by full differential operational amplifier 6a with opposite polarity.On the output stage of current-voltage conversion portion 6, be connected with the LPF structure output circuit 5 that is constituted by the application circuit that comprises single translation operation amplifier 5a and illustrated a plurality of resistance (accessory circuit).
In above structure, the output signal of delta-sigma modulator 2 is exported after being removed high-frequency noise and being converted current value in FIR filter 4, then, resulting thus output current, the feedback resistance 6b of the full differential operational amplifier 6a by current-voltage conversion portion 6 are carried out the current/voltage conversion.At this, as operational amplifier 6a, be in order to remove the noise of homophase, by can remove the noise of homophase efficiently to the differential input of full differential operational amplifier 6a with full differential operational amplifier.
Output from current-voltage conversion portion 6, be imported in the output circuit 5 that is constituted by single translation operation amplifier 5a and application circuit thereof, at this, radio-frequency component is further decayed, and obtains and the corresponding simulation output of the output signal of described delta-sigma modulator 2 from output circuit 5.
As mentioned above, the FIR filter current source of the present application does not use current/voltage of the prior art to change the resistance of usefulness because of having used constant-current source, so can prevent the generation of thermal noise.In addition, because of output stage has been used single translation operation amplifier 5a, in the circuit of reality, compare the decay that can have usually about 6db so can make, thereby can make that noise characteristic is further improved as the gain of amplification quantity.
One of the present invention's effect:,, the above level of required frequency is descended precipitously so can obtain precipitous filtering characteristic because of current source is that FIR moves.In addition, because of in the current source that constitutes FIR, not using resistance,, can prevent the noise that produces by resistance so can all adjust FIR with electric current.
The present invention's two effect: the feedback resistance of reason operational amplifier carries out the conversion of current/voltage, so compare with the resistance circuit of prior art, can reduce the thermal noise that the resistance decrease is produced, and carry out the current/voltage conversion with full differential operational amplifier, can remove the noise of homophase.
The present invention's three effect: by can further improving noise level as output stage with differential single translation operation amplifier.
Claims (4)
1, a kind of output filter of delta-sigma modulator possesses the FIR filter,
This FIR filter possesses:
A plurality of delay elements of cascade, wherein, input is from the dateout of delta-sigma modulator, from comprising the elementary described dateout from delta-sigma modulator that output is delayed respectively interior delay elements at different levels in the elementary delay element;
A plurality of 3 terminal control elements are right, wherein, each that constitutes 3 right terminal control elements all has the 1st terminal as control terminal, with the 2nd terminal and the 3rd terminal, imported the some output in described a plurality of delay element in the described control terminal of the 3 terminal control elements that described formation is right, the both sides' of the 3 terminal control elements that described formation is right described the 2nd terminal is through common constant-current source ground connection, one side's of the 3 terminal control elements that a plurality of described formations are right the 3rd terminal connects the 1st output as filter each other jointly, and the opposing party's of the 3 terminal control elements that a plurality of described formations are right the 3rd terminal connects the 2nd output as filter each other jointly;
The 1st current source, its with described a plurality of 3 terminal control elements to described in constitute a side of 3 right terminal control elements the 3rd terminal be connected; And
The 2nd current source, its with described a plurality of 3 terminal control elements to described in constitute the opposing party of 3 right terminal control elements the 3rd terminal be connected,
According to each output control of described a plurality of delay elements from the described the 1st and the electric current of the 2nd current source, thereby obtain electric current with the filtering characteristic weighting, and in the described the 1st and the 2nd output, this electric current is carried out exporting after the add operation, it is characterized in that:
The the described the 1st and the 2nd current source is a constant-current source.
2, the output filter of delta-sigma modulator as claimed in claim 1 is characterized in that: have the current-voltage conversion portion that the output of described FIR filter is carried out the current/voltage conversion as input, with the feedback resistance of full differential operational amplifier.
3, the output filter of delta-sigma modulator as claimed in claim 2 is characterized in that: have the output of the described full differential operational amplifier differential single translation operation amplifier as input.
4, a kind of digital signal processing device possesses: the output filter of each described delta-sigma modulator in the claim 1～3.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002360689A JP2004194054A (en) | 2002-12-12 | 2002-12-12 | Output filter of delta-sigma modulator and digital signal processor provided with output filter |
| JP2002360689 | 2002-12-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1507159A CN1507159A (en) | 2004-06-23 |
| CN1285175C true CN1285175C (en) | 2006-11-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101209054A Expired - Fee Related CN1285175C (en) | 2002-12-12 | 2003-11-20 | Output wave filter for delta-sigma modulator and digital signal processor with the same output filter |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7256720B2 (en) |
| JP (1) | JP2004194054A (en) |
| CN (1) | CN1285175C (en) |
| TW (1) | TWI251401B (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2004107561A1 (en) * | 2003-05-21 | 2004-12-09 | Ess Technology, Inc. | Voltage to current converter |
| US7236112B2 (en) * | 2005-01-21 | 2007-06-26 | Technoconcepts, Inc. | Self-tuning output digital filter for direct conversion delta-sigma transmitter |
| US7848402B1 (en) * | 2005-09-29 | 2010-12-07 | Altera Corporation | Phase-adjusted pre-emphasis and equalization for data communication |
| US7528754B1 (en) * | 2006-02-09 | 2009-05-05 | Arizona Board Of Regents | Finite impulse response digital to analog converter |
| US7903011B2 (en) * | 2006-09-13 | 2011-03-08 | Honeywell International Inc. | Differential current-mode translator in a sigma-delta digital-to-analog converter |
| US7705758B2 (en) * | 2008-03-20 | 2010-04-27 | Mediatek Inc. | Method and apparatus for digital to analog conversion |
| DE102008050001B4 (en) * | 2008-09-30 | 2010-11-25 | Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik | Digital-to-analog converter |
| US7956782B2 (en) * | 2009-06-11 | 2011-06-07 | Honeywell International Inc. | Current-mode sigma-delta digital-to-analog converter |
| JP5486334B2 (en) * | 2010-02-05 | 2014-05-07 | 旭化成エレクトロニクス株式会社 | Digital-to-analog converter |
| US7965212B1 (en) * | 2010-02-12 | 2011-06-21 | Bae Systems Information And Electronic Systems Integration Inc. | DAC circuit using summing junction delay compensation |
| US7978109B1 (en) * | 2010-02-18 | 2011-07-12 | Advantest Corporation | Output apparatus and test apparatus |
| JP5469134B2 (en) * | 2010-08-04 | 2014-04-09 | 旭化成エレクトロニクス株式会社 | Adder embedded dynamic preamplifier |
| US8497707B2 (en) * | 2011-09-07 | 2013-07-30 | Advanced Micro Devices, Inc. | Transmitter equalization method and circuit using unit-size and fractional-size subdrivers in output driver for high-speed serial interface |
| KR101280876B1 (en) * | 2012-01-26 | 2013-07-02 | 주식회사 레이믹스 | Continuous time sigma-delta analog to digital converter using current controlled level shifter |
| US8766840B2 (en) * | 2012-08-29 | 2014-07-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for a high resolution digital input class D amplifier with feedback |
| US8773297B2 (en) * | 2012-08-29 | 2014-07-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | System and method for pulse width modulation digital-to-analog converter |
| US10020818B1 (en) | 2016-03-25 | 2018-07-10 | MY Tech, LLC | Systems and methods for fast delta sigma modulation using parallel path feedback loops |
| US10530372B1 (en) | 2016-03-25 | 2020-01-07 | MY Tech, LLC | Systems and methods for digital synthesis of output signals using resonators |
| EP3542461B1 (en) | 2016-11-21 | 2024-07-31 | Mixed-Signal Devices Inc. | High efficiency power amplifier architectures for rf applications |
| US10951181B2 (en) | 2018-10-03 | 2021-03-16 | Semiconductor Components Industries, Llc | Methods and apparatus for an amplifier circuit |
| WO2020186255A1 (en) | 2019-03-14 | 2020-09-17 | Mixed Signal Devices Inc. | Linearization of digital-to-analog converters (dacs) and analog-to-digital converters (adcs) and associated methods |
| KR102706428B1 (en) * | 2019-10-07 | 2024-09-12 | 삼성전자주식회사 | Reconfigurable analog filter and integrated circuit including the same |
| US12123968B2 (en) | 2021-02-05 | 2024-10-22 | Mixed-Signal Devices Inc. | Systems and methods for digital signal chirp generation using frequency multipliers |
| US12231145B1 (en) | 2022-02-24 | 2025-02-18 | Mixed-Signal Devices Inc. | Systems and methods for digital signal synthesis with variable sample rate DAC |
| US11933919B2 (en) | 2022-02-24 | 2024-03-19 | Mixed-Signal Devices Inc. | Systems and methods for synthesis of modulated RF signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4658225A (en) * | 1984-07-05 | 1987-04-14 | Hewlett-Packard Company | Amplitude insensitive delay lines in a transversal filter |
| JPH06303137A (en) * | 1992-12-29 | 1994-10-28 | Hitachi Ltd | D / A converter, offset adjusting circuit, and mobile communication terminal device using the same |
| US5323157A (en) * | 1993-01-15 | 1994-06-21 | Motorola, Inc. | Sigma-delta digital-to-analog converter with reduced noise |
| US5625357A (en) * | 1995-02-16 | 1997-04-29 | Advanced Micro Devices, Inc. | Current steering semi-digital reconstruction filter |
| US5638016A (en) * | 1995-04-18 | 1997-06-10 | Cyrix Corporation | Adjustable duty cycle clock generator |
| US5727038A (en) * | 1996-09-06 | 1998-03-10 | Motorola, Inc. | Phase locked loop using digital loop filter and digitally controlled oscillator |
| US6087968A (en) * | 1997-04-16 | 2000-07-11 | U.S. Philips Corporation | Analog to digital converter comprising an asynchronous sigma delta modulator and decimating digital filter |
| EP1421688A2 (en) * | 2001-08-03 | 2004-05-26 | Koninklijke Philips Electronics N.V. | Analog fir-filter |
| US6529077B1 (en) * | 2001-08-22 | 2003-03-04 | Institute Of Microelectronics | Gain compensation circuit for CMOS amplifiers |
| US6556643B2 (en) * | 2001-08-27 | 2003-04-29 | Micron Technology, Inc. | Majority filter counter circuit |
-
2002
- 2002-12-12 JP JP2002360689A patent/JP2004194054A/en active Pending
-
2003
- 2003-09-23 TW TW092126151A patent/TWI251401B/en not_active IP Right Cessation
- 2003-11-20 CN CNB2003101209054A patent/CN1285175C/en not_active Expired - Fee Related
- 2003-12-10 US US10/730,928 patent/US7256720B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20040233085A1 (en) | 2004-11-25 |
| TW200419925A (en) | 2004-10-01 |
| US7256720B2 (en) | 2007-08-14 |
| JP2004194054A (en) | 2004-07-08 |
| CN1507159A (en) | 2004-06-23 |
| TWI251401B (en) | 2006-03-11 |
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Granted publication date: 20061115 Termination date: 20121120 |