CN1282990C - Method for fabricating strained crystalline layer on insulator and its semiconductor structure - Google Patents

Abstract

Provided is a simple method for manufacturing a semiconductor structure which has crystal of high quality and also has a highly strained crystalline semiconductor layer on an insulator. The method is provided with: a semiconductor donor substrate comprising germanium and/or an A(III)-B(V)-semiconductor; at least one first crystalline epitaxial layer, in a first step, wherein the content of germanium and/or the A(III)-B(V)-semiconductor of a buffer layer of the first layer is decreased during the first step; at least one insulator layer, in a second step; wherein the first layer is provided between the substrate and the insulator layer; the first layer, which is split in a third step; and at least one second crystalline epitaxial layer on the split first layer, in a fourth step.

Description

Method for fabricating strained crystalline layer on insulator and semiconductor structure thereof

technical field

The invention relates to a method for manufacturing a strained crystal layer on an insulator, a semiconductor structure for manufacturing a strained crystal layer on an insulator, and a semiconductor structure manufactured using the same.

Background technique

Thin strained semiconductor layers such as silicon layers have favorable electron and hole mobility properties. Therefore, such layers are very important for almost all areas of microelectronics, because they can be used to obtain high-performance devices with high speed and low power consumption. If the strained semiconductor layer is transferred onto the insulator layer to obtain a structure such as SOI (silicon-on-insulator), the strained semiconductor layer can be used more effectively, in microelectronics and microscopic Their superiority is generally known in the field of mechanics.

At the 2001 IEEE International SOI Conference, Cheng et al. disclosed a method for manufacturing SiGe-on-insulator (SiGe-on-insulator) structures under the title of "SiGe-on-insulator (SGOI): Substrate Preparation and MOSFET Fabrication for ElectronMobility Evaluation". method. In this method, a graded SiGe layer is grown on a monocrystalline silicon feedstock wafer. During the SiGe growth process, the germanium content of the SiGe gradually increases until the germanium percentage reaches about 25%. With this percentage content, a relaxed SiGe layer (relaxed SiGe layer) is grown on the graded SiGe layer. In addition, hydrogen ions are implanted into the loose SiGe layer, thereby forming a pre-weakened layer in the loose SiGe layer. Thereafter, the implanted structure is bonded to the silicon oxide wafer. After annealing, the bonding structure is separated into two parts along the pre-weakening layer, thereby obtaining a SiGe-on-insulator structure and a residual structure. Then, a strained silicon layer is grown on the SiGe layer to obtain a Si-on-SiGe-on-insulator structure.

A disadvantage of the structure of the above approach is that the strain of the strained silicon layer on the SiGe layer cannot be increased to commercially significant values. This is because the limited germanium content of a SiGe layer cannot be increased beyond 25% without the risk of developing high dislocation densities in the SiGe layer, which would significantly affect the electronic properties of the strained silicon layer.

Contents of the invention

It is an object of the present invention to provide a semiconductor structure and a simple method for producing a semiconductor structure with high crystal quality and highly strained crystalline semiconductor layers on an insulator.

This object can be achieved by a method for producing a strained crystalline layer on an insulator, the method comprising: providing a semiconductor raw substrate comprising germanium and/or A(III)-B(V)-semiconductors; in a first step, providing at least one The first crystalline epitaxial layer, in the second step, at least one insulator layer is arranged; wherein the first crystalline epitaxial layer is arranged between the semiconductor raw material substrate and the insulator layer, the first crystalline epitaxial layer includes a buffer layer, during the first step, The germanium and/or A(III)-B(V)-semiconductor content of the buffer layer is reduced to a ratio of 50% to 80% from the semiconductor raw material substrate to the direction of the insulator layer; in the third step, the first crystallized The epitaxial layer is separated into two parts; and in a fourth step, at least one second crystalline epitaxial layer is provided on the part of the first crystalline epitaxial layer on the insulator layer side. .

With the inventive method it is possible to produce semiconductor structures in which the content of germanium and/or A(III)-B(V)-semiconductors decreases in the direction from the substrate to the second layer. In this way, a very high germanium and/or A(III)-B(V)-semiconductor content can be achieved in the first layer, resulting in a highly strained second layer. The addition of germanium and/or A(III)-B(V)-semiconductors allows at least part of the first layer to be grown with a low defect density, thus obtaining a high crystalline quality second layer. Using this inventive method, a highly strained, high-quality second layer can be easily transferred onto the insulator layer, resulting in a semiconductor structure that combines the benefits of an SOI structure with the very good electronic properties of a strained crystalline layer.

According to a further embodiment of the present invention, the semiconductor raw substrate (1) is a single crystal germanium wafer, a single crystal A(III)-B(V)-semiconductor wafer, an epitaxial germanium layer or an epitaxial A(III)-B(V) - a semiconducting layer. On these substrates, first layers with high germanium content and high crystalline quality can be grown. Germanium wafers and/or A(III)-B(V)-semiconductor wafers are stable substrates so that strained crystalline layers on insulators can be handled well during fabrication.

In an advantageous embodiment of the invention, in a first step, the germanium and/or A(III)-B(V)-semiconductor content of the buffer layer is reduced to a germanium ratio of about 40% to 80%, preferably to about A ratio of 50% to 80% or about 60% to 80%. Such a large amount of germanium and/or A(III)-B(V)-semiconductors makes it possible to obtain a highly strained second layer.

In a preferred embodiment of the present invention, in the first step, the silicon content of the buffer layer is increased to a silicon ratio of about 30% to 60%, preferably to a ratio of about 20% to 50% or about 20% to 40%. In the first step, scaling up of silicon results in a well relaxed buffer layer, especially a well relaxed GeSi layer.

In another preferred embodiment of the invention, the second crystalline epitaxial layer is grown to a thickness below 50 nm. Such a layer thickness is below the critical thickness, thus preventing thermodynamic instability of the layer. In the inventive thin layer, strain can be efficiently generated.

In another preferred embodiment of the invention, the first crystalline epitaxial layer and/or the second crystalline epitaxial layer comprises carbon. A carbon concentration of a few percent, even below 1%, is preferred, resulting in good dopant stability and high strain levels in the first crystalline epitaxial layer and/or the second crystalline epitaxial layer.

This object can be further achieved with a semiconductor structure producing a strained crystalline layer on an insulator, the semiconductor structure comprising: a semiconductor raw substrate consisting of a first material comprising germanium and/or an A(III)-B(V)-semiconductor; at least one crystalline epitaxial layer; and at least one insulator layer; wherein the at least one crystalline epitaxial layer is an intermediate layer between the semiconductor source substrate and the insulator layer, the at least one crystalline epitaxial layer comprising a buffer layer comprising germanium and /or A(III)-B(V)-semiconductor compositions, the content of germanium and/or A(III)-B(V)-semiconductors is reduced from 50% to 50% in the direction from the semiconductor raw substrate to the insulator layer 80% ratio.

The inventive structure is an intermediate for fabricating a strained crystalline layer on an insulator layer. Due to the reduction of germanium and/or A(III)-B(V)-semiconductors in the crystalline epitaxial layer starting from the substrate, it is possible to use low defect densities with high germanium and/or A(III)-B(V) - Semiconductor content, growing crystalline epitaxial layers, this high content is eg the basis for further good growth of highly strained, high quality crystalline layers on the crystalline epitaxial layer of the inventive structure.

In a preferred variant of the present invention, the semiconductor raw substrate is a single crystal germanium wafer, a single crystal A(III)-B(V)-semiconductor wafer, an epitaxial germanium layer or an epitaxial A(III)-B(V)-semiconductor layer. Each wafer and epitaxial layer contains a large amount of germanium and/or A(III)-B(V)-semiconductor, so that a good growth of germanium and/or a high content of A(III)-B(V)-semiconductor is possible on the substrate The crystalline epitaxial layer, wherein the crystalline epitaxial layer has a low defect density.

In a preferred example of the invention, the germanium and/or A(III)-B(V)-semiconductor content of the crystalline epitaxial layer is reduced to a proportion of about 40% to 80%, preferably to about 50% to 80% or About 60% to 80% ratio. A proportion of about 40% to 80% of germanium and/or A(III)-B(V)-semiconductors allows good growth of strained crystalline layers on the crystalline epitaxial layer, while a proportion of about 50% to 80% is essential for the upper crystalline layer It is more advantageous to obtain higher strains in the crystalline layer, and the range of about 60% to 80% for germanium is the most preferred range for producing very high strains in the crystalline layer on the crystalline epitaxial layer.

According to an advantageous example of the invention, the silicon content of the crystalline epitaxial layer increases in the direction from the substrate to the insulator layer. The silicon is scaled up, leading to a good modification of the crystal lattice, such that a crystalline epitaxial layer with a low defect density is obtained.

In another preferred embodiment of the invention, the silicon content is increased to a silicon proportion of about 20% to 60%, preferably to a proportion of about 20% to 50% or about 20% to 40%. A silicon proportion of about 20% to 60% makes it possible to obtain a crystalline epitaxial layer with a low defect density and also to obtain a good modification of the upper crystalline epitaxial layer such as a silicon layer, while a silicon proportion of 20% to 50% contributes to a high The crystallinity is more favorable in order to obtain an upper crystalline layer with very good properties, for example a silicon layer, a silicon proportion of 20% to 40% is most favorable for producing a high quality crystalline epitaxial layer formed on the crystalline epitaxial layer Very good basis for high quality strained crystalline layers.

Furthermore, the object of the present invention can be achieved by using a semiconductor structure comprising: a semiconductor base substrate; at least one insulator layer; and at least one first crystalline epitaxial layer; at least one strained second crystalline epitaxial layer, wherein the first crystalline epitaxial layer layer is an intermediate layer between the insulator layer and the strained second crystalline epitaxial layer, the insulator layer is an intermediate layer between the semiconductor base substrate and the first crystalline epitaxial layer, and the first crystalline epitaxial layer includes a buffer layer that is Compositions comprising germanium and/or A(III)-B(V)-semiconductors, the content of germanium and/or A(III)-B(V)-semiconductors in the direction from the strained second crystalline epitaxial layer to the insulator layer Reduce to a ratio of 50% to 80%.

Due to the reduction of germanium and/or A(III)-B(V)-semiconductor in the buffer layer, at least part of the first layer has a very low defect density, which can produce additional layer. Additionally, the inventive structure combines the benefits of an SOI structure with the good conductive properties of a strained crystalline layer. The strained layer can have a very high strain, since the germanium and/or A(III)-B(V)-semiconductor content in the first layer can be adjusted to be very high.

In a further advantageous variant of the invention, the germanium and/or A(III)-B(V)-semiconductor content of the buffer layer is reduced to a germanium ratio of approximately 40% to 80%, preferably to approximately 50% to 80% % or a ratio of about 60% to 80%. 40% to 80% have higher germanium and/or A(III)-B(V)-semiconductor content, which can produce a highly strained crystalline epitaxial layer on top of the first layer, such as a silicon layer, while 50% to 80% A ratio of 100% is more favorable for upper crystalline epitaxial layers that achieve higher strains on the first layer, while a ratio of 60% to 80% is most favorable for very high strained crystalline epitaxial layers (such as silicon layers) on the first layer.

In another embodiment of the invention, the silicon content of the buffer layer increases in the direction from the second layer to the insulator layer. The addition of silicon leads to a good modification of the crystal lattice of the buffer layer in the direction of the second layer, thereby giving at least part of the first layer high-quality crystallinity, which is a good basis for obtaining a high-quality crystallinity of the second layer.

In yet another preferred embodiment of the present invention, the silicon content is increased to a silicon ratio of about 20% to 60%, preferably to a ratio of about 20% to 50% or about 20% to 40%. A silicon content of about 20% to 60% is good for growing a strained silicon layer on the first layer, while a ratio of 20% to 50% is more favorable for obtaining a higher strained silicon layer on the first layer, and 20% to 40% The ratio is most favorable to obtain a highly strained silicon layer on the first layer.

In a further advantageous example of the invention, the thickness of the strained layer is below 50 nm. This layer thickness results in a good thermodynamic stability of the second layer, so that in this thin layer, strains can easily be generated.

In yet another advantageous embodiment of the invention, the first crystalline epitaxial layer and/or the strained second crystalline epitaxial layer comprise carbon. The carbon content allows the first and/or second layer to be more stable and exhibit better strain levels.

The object of the present invention can be further achieved by a method for producing a strained crystalline layer on an insulator, the method comprising: providing a semiconductor raw substrate comprising germanium and/or A(III)-B(V)-semiconductors; in a first step, At least one first crystalline epitaxial layer is arranged, and in the second step, at least one second crystalline epitaxial layer is arranged; wherein the first crystalline epitaxial layer is arranged between the semiconductor raw material substrate and the second crystalline epitaxial layer, and the first crystalline epitaxial layer includes buffer layer, the germanium and/or A(III)-B(V)-semiconductor content of the buffer layer is reduced to 50% to 80% in the direction from the semiconductor raw material substrate to the second crystalline epitaxial layer during the first step ratio; in the third step, at least one insulator layer is provided; wherein the second crystalline epitaxial layer is provided between the first crystalline epitaxial layer and the insulator layer; and in the fourth step, between the first crystalline epitaxial layer and the second crystalline epitaxial layer separate between. Because of the reduced germanium and/or A(III)-B(V)-semiconductor content of the buffer layer, very good crystallinity and low defect density of at least part of the first layer can be obtained, resulting in a high-quality second crystalline layer , the second crystalline layer may be disposed on the first layer. Starting from germanium and/or A(III)-B(V)-semiconductors as semiconductor raw substrates, the germanium and/or A(III)-B(V)-semiconductor content of the buffer layer can be reduced to a higher Germanium and/or A(III)-B(V)-semiconductor content to form a highly strained second crystalline layer, eg a silicon layer, on the first layer. A further advantage of the inventive approach is that the good electronic properties of the strained second layer can be combined with the benefits of the SOI layer, since the second strained layer can be placed on the insulator layer. The inventive method comprises a simple sequence of steps in order to easily manufacture the inventive semiconductor structure.

In a further embodiment of the present invention, the semiconductor raw substrate (1) is a single crystal germanium wafer, a single crystal A(III)-B(V)-semiconductor wafer, an epitaxial germanium layer or an epitaxial A(III)-B(V )-semiconductor layer. These substrates provide a large amount of germanium and/or A(III)-B(V)-semiconductors such as GaAs, so that good growth with a high content of germanium and/or A(III)-B(V)- The first layer of semiconductor.

In an advantageous example of the invention, the second crystalline epitaxial layer is grown to a thickness below 50 nm. At this thickness, the second layer has thermodynamic stability, and it is possible to grow a second layer with high strain.

According to another preferred embodiment of the invention, in a first step the germanium and/or A(III)-B(V)-semiconductor content of the buffer layer is reduced to a germanium ratio of about 40% to 80%, preferably to A ratio of about 50% to 80% or about 60% to 80%. A germanium and/or A(III)-B(V)-semiconductor ratio of 40% to 80% for the buffer layer forms a good basis for a highly strained second layer, while a germanium ratio of 50% to 80% for the first layer Even more favorable for obtaining higher strains in the second layer, a germanium proportion of about 60% to 80% is the most favorable range for achieving very high strains in the second layer.

In yet another advantageous embodiment of the invention, in a first step, the silicon content of the buffer layer is increased to a silicon proportion of about 20% to 60%, preferably to a proportion of about 20% to 50% or about 20% to 40%. . A highly strained silicon layer can be grown with a silicon ratio of 20% to 60% on the first layer, while a silicon ratio of 20% to 50% is less important for achieving high strain in a second layer (such as a silicon layer) on the first layer. Advantageously, a silicon proportion of about 20% to 40% is most favorable for obtaining very high strains in the second layer, such as the silicon layer.

Furthermore, the object can be achieved with a semiconductor structure producing a strained crystalline layer on an insulator comprising: a semiconductor raw substrate consisting of a first material comprising germanium and/or an A(III)-B(V)-semiconductor ; at least one first crystalline epitaxial layer; at least one second crystalline epitaxial layer; and at least one insulator layer, wherein the first crystalline epitaxial layer is an intermediate layer between the semiconductor raw material substrate and the second crystalline epitaxial layer, and the second crystalline epitaxial layer layer is an intermediate layer between a first crystalline epitaxial layer and an insulator layer, the first crystalline epitaxial layer comprising a buffer layer which is a composition comprising germanium and/or an A(III)-B(V)-semiconductor, germanium And/or the content of A(III)-B(V)-semiconductor decreases to a ratio of 50% to 80% in the direction from the semiconductor raw material substrate to the second crystalline epitaxial layer.

The inventive structure is an intermediate structure for fabricating a strained crystalline layer on an insulator layer. Because the germanium and/or A(III)-B(V)-semiconductor content in the buffer layer decreases from the substrate to the second layer, it is possible to make the germanium and/or A(III)-B(V)- The semiconductor content is reduced to a higher content of germanium and/or A(III)-B(V)-semiconductors, so that a highly strained second layer is produced on the first layer. The scaling down of germanium and/or A(III)-B(V)-semiconductors further renders at least part of the first layer low defect density, resulting in a high quality second layer. A further advantage of the inventive structure is that a second strained layer can be created on the insulator layer, so SOI structures can be easily formed starting from the inventive structure.

In a further advantageous embodiment of the invention, the semiconductor raw material substrate is a monocrystalline germanium wafer, a monocrystalline A(III)-B(V)-semiconductor wafer, an epitaxial germanium layer or an epitaxial A(III)-B(V)- semiconductor layer. These substrates comprise a large amount of germanium and/or A(III)-B(V)-semiconductors, which facilitates high-quality growth of the first layer containing germanium and/or A(III)-B(V)-semiconductors.

In another advantageous embodiment of the invention, the germanium and/or A(III)-B(V)-semiconductor content of the first layer is reduced to a ratio of about 40% to 80%, preferably to about 50% to 80% or about a 60% to 80% ratio. A germanium and/or A(III)-B(V)-semiconductor ratio of 40% to 80% allows for the growth of a highly strained second layer on the first layer, while a ratio of 50% to 80% is useful for producing Higher strains are more favorable, with a ratio of 60% to 80% being the most favorable range for forming a very highly strained second layer on the first layer.

In another advantageous example of the invention, the silicon content of the buffer layer increases in the direction from the substrate to the insulator layer. Said increase of silicon allows the crystal lattice of the first layer to be well adapted to the substrate, resulting in a low defect density of at least part of the first layer.

In a further advantageous embodiment of the invention, the silicon content is increased to a silicon proportion of approximately 20% to 60%, preferably to a proportion of approximately 20% to 50% or approximately 20% to 40%. A silicon proportion of about 20% to 60% allows good growth of a highly strained second layer, such as a silicon layer, while a silicon proportion of about 20% to 50% is more favorable for obtaining higher strains in a second layer such as a silicon layer, A silicon proportion of about 20% to 40% is the most favorable range for obtaining very high strains in the second layer, such as the silicon layer.

In yet another advantageous embodiment of the invention, the first crystalline epitaxial layer and/or the second crystalline epitaxial layer comprise carbon. A low content of carbon is preferred, eg below a few percent, even below 1% carbon, resulting in high dopant stability and good strain behavior in the first and/or second layer.

Description of drawings

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings, which include:

1 shows a schematic diagram of a semiconductor substrate used in a first step of a method according to a first embodiment of the invention;

Fig. 2 shows the schematic diagram of the first step of the first embodiment of the present invention;

3 shows a schematic diagram of the second step of the first embodiment of the present invention to obtain a semiconductor structure according to the third embodiment of the present invention;

Figure 4 shows a schematic diagram of the implantation steps applied to the structure shown in Figure 3;

Figure 5 shows a schematic diagram of the joining step of the structure shown in Figure 4;

Fig. 6 shows the third step according to the first embodiment of the present invention, a schematic diagram of the separation step of the structure shown in Fig. 5;

FIG. 7 shows a schematic view of an inventive semiconductor structure fabricated using the method according to the first embodiment of the invention shown in FIGS. 1 to 6;

8 shows a schematic diagram of a semiconductor substrate used in a first step according to a second embodiment of the present invention;

Fig. 9 shows a schematic diagram of the first step of the second embodiment of the present invention;

Fig. 10 shows a schematic diagram of a second step according to a second embodiment of the present invention;

11 shows a schematic diagram of the third step of the second embodiment of the present invention to obtain a semiconductor structure according to the fourth embodiment of the present invention;

Figure 12 shows a schematic diagram of the implantation steps applied to the structure shown in Figure 11;

Figure 13 shows a schematic diagram of the joining step applied to the structure shown in Figure 12;

Fig. 14 shows a schematic diagram of the fourth step of the second embodiment of the present invention applied to the structure shown in Fig. 13;

Figure 15 shows a schematic view of an inventive structure manufactured using the method according to the second embodiment of the invention illustrated in Figures 8 to 14; and

FIG. 16 is a schematic diagram showing the relationship between concentration distribution and thickness of the semiconductor structures shown in FIGS. 2 and 9 .

Detailed ways

FIG. 1 shows a schematic view of a semiconductor substrate used in the first step of the method according to the first embodiment of the invention. The semiconductor substrate 1 is a single crystal germanium wafer, which preferably has generally available dimensions and electronic properties. A germanium wafer or feedstock wafer 1 has a polished and cleaned upper surface 11 .

In another embodiment of the present invention, the semiconductor raw substrate may be an A(III)-B(V) semiconductor wafer such as a GaAs wafer, which has an epitaxial Ge layer or an epitaxial A(III) layer such as a GaAs layer. - B(V) semiconductor layer. For example, the substrate may contain a GaAs layer or a GaAs wafer covered by a Ge layer.

Fig. 2 shows a schematic diagram of the first step of the first embodiment of the present invention. In a first step, a first crystalline epitaxial layer 2 is grown on a semiconductor raw material substrate 1 shown in FIG. 1 . The first crystalline epitaxial layer 2 is composed of a composition of germanium and silicon forming a GeSi layer. GeSi layer 2 is formed directly on upper surface 11 of germanium wafer 1 .

In yet another embodiment of the present invention, a Ge seed layer may be formed on the upper surface 11 before growing the GeSi layer 2 .

The GeSi layer 2 includes two layers, namely, a graded buffer GeSi layer 21 and a loose GeSi layer 22 . The silicon concentration of the slowly changing buffer GeSi layer 21 near the surface 11 of the germanium wafer 1 is about 0%, while the silicon content of the buffer GeSi layer 21 gradually increases from the surface 11 of the germanium wafer 1 to the layer 23, and the GeSi in the layer 23 The silicon content of the layer is about 20% to 60%. Thus, the germanium content of the buffer GeSi layer 21 gradually decreases from about 100% of the surface 11 to a layer 23 in which the proportion of germanium is about 40% to 80%.

The GeSi layer 2 is doped with carbon in a proportion of less than 1%.

A layer of loose GeSi is on top of layer 23 and its silicon to germanium ratio corresponds to the maximum ratio of silicon to germanium of buffer layer 21 . In particular, the defect density of the loose GeSi layer 22 is very low, about 10 ⁴ cm ^-2 .

Fig. 3 shows a schematic diagram of the second step of the first embodiment of the present invention. In a second step, an insulator layer 3 is deposited on the first layer 2 so that the first layer 2 becomes an intermediate layer between the substrate 1 and the insulator layer 3 . The insulator layer 3 consists of silicon dioxide and/or silicon nitride. In the illustrated embodiment, the insulator layer 3 is deposited at a temperature below 900°C. In another example of the present invention, the insulator layer 3 may be a thermal oxide. The thickness of the insulator layer is adjusted to the target layer thickness of the SiGe/strained silicon layer to be transferred onto the base wafer. The insulator layer 3 has an upper surface 13 .

The semiconductor structure shown in FIG. 3 is an inventive structure according to a third embodiment of the present invention, which is an intermediate product of fabricating a strained crystalline layer on an insulator.

FIG. 4 shows the implantation steps carried out on the structure shown in FIG. 3 . In this implantation step, hydrogen species (hydrogen species) 4 are implanted into the structure shown in FIG. 3 with an appropriate energy below about 180 keV and an implantation dose greater than 5×10 ¹⁶ cm ⁻² . The hydrogen species 4 passes through the upper surface 13 and then through the insulator layer 3 into the first layer 2 and thus into the layer 24 of the first layer 2 . Layer 24 preferably corresponds to layer 23 in first layer 2 between buffer GeSi layer 21 and loose GeSi layer 22 . Due to the implantation process, the layer 24 is pre-weakened and a predetermined separation zone is formed.

In a next step, not shown in the above figures, the surface 13 of the insulator layer 3 is cleaned using a standard silicon IC manufacturing post-implantation process. If desired, the insulator layer 3 can be removed and a fresh insulator layer can be deposited.

FIG. 5 shows a joining step applied to the structure shown in FIG. 4 . In this bonding step, the base wafer 6 made of silicon, germanium, A(III)-B(V)-semiconductor, quartz, glass, etc. The processed insulator layers 3 are bonded together. Surface preparation prior to bonding may be performed using chemical mechanical polishing techniques, surface cleaning techniques, oxygen plasma treatment techniques, and other available surface treatment techniques. The base wafer 6 can be directly bonded to the surface 13 of the insulator layer 3 . According to another embodiment of the invention, the base wafer 6 can have a dielectric layer on its bonding face, which is to be bonded to the surface 13 of the insulator layer 3 .

Fig. 6 shows a third step according to the first embodiment of the present invention. The third step is a separation step of separating the structure shown in FIG. 5 into two semiconductor structure portions 31 and 32 . Portions 31 and 32 are separated along predetermined separation line 24 formed during the implantation step shown in FIG. 4 . The portion 31 obtained consists of the base wafer 6 on which the insulator layer 3 is formed, while the portion 31 is above the portion 7 of the GeSi layer 2 . Portion 7 preferably consists of loose GeSi material.

The other part 32 formed by the separation step consists of the raw germanium wafer 1 on which the remaining part 8 of the GeSi layer 2 is formed. The remaining portion 8 preferably contains the remaining portion of the graded buffer GeSi layer 21 and the aforementioned loose GeSi layer 22 .

In the separation process shown in Figure 6, the parameters used are actually the parameters commonly used by the so-called Smart Cut method, for example, the Smart Cut method is described in WO00/24059, and the content of WO00/24059 is quoted here for refer to. Separation can be performed, for example, by subjecting the structure shown in FIG. 5 to heat treatment or vibration treatment.

In a further step, not shown, the portion 7 of the GeSi layer 2 is finished by means of chemical mechanical polishing and, optionally, thermal treatment.

Fig. 7 shows a schematic diagram of the fourth step of the method according to the first embodiment of the present invention. In a fourth step, on the surface 17 of the separation portion 31, a second crystalline epitaxial layer is grown. The second layer 9 is a layer of strained silicon with a thickness below 50 nm and a carbon content below 1%. The strain of the strained silicon layer is very high, while the defect density is low.

The semiconductor structure shown in FIG. 7 is an inventive structure corresponding to the final product of the method according to the first embodiment of the present invention. The structure comprises a base wafer 6, an insulator layer 3, a portion 7 of the GeSi layer 2, and a second layer 9, wherein the insulator layer 3 is an intermediate layer between the base wafer 6 and the portion 7, and the portion 7 is the insulator layer 3 and the second layer 9. Intermediate layer between layers 9. In another embodiment of the present invention, additional layers such as seed layers are respectively present between the layers of the structure shown in FIG. 7 .

The strain of the silicon layer 9 is the strain produced when epitaxially growing a crystalline silicon layer less than 50 nm thick on a GeSi layer whose germanium content is about 40% to 80%, which is higher than that of a GeSi layer whose germanium content is less than 40% Strain of a prior art silicon layer grown on the layer whose thickness is below 50nm.

The structure shown in FIG. 7 may be thermally annealed after growing the strained silicon layer 9 .

8 to 13 show schematic diagrams of steps of a method according to a second embodiment of the present invention. In Figs. 8 to 15, the same reference numerals as used in Figs. 1 to 7 are used to designate the same parts and components as in Figs. 1 to 7 .

FIG. 8 shows a schematic view of a semiconductor substrate 1 used in the first step according to the second embodiment of the present invention. The semiconductor substrate 1 is a single-crystal germanium wafer, and has an upper surface 11 .

Fig. 9 shows a schematic diagram of the first step of the second embodiment of the present invention. In a first step, a fourth crystalline epitaxial layer is grown on the upper surface 11 of the germanium wafer 1 . As mentioned above, with reference to Figures 1 to 7, in another embodiment, an A(III)-B(V)-semiconductor may be used or have an epitaxial Ge or A(III)-B(V)-semiconductor layer thereon Substrates instead of Ge wafers.

The first crystalline epitaxial layer 2 is a GeSi layer composed of a slowly changing buffer GeSi layer 21 and a loose GeSi 22. A graded buffer GeSi layer 21 is grown on the upper surface 11 of the germanium wafer 1 with increasing silicon content.

The silicon content increases from the surface 11 with a silicon content of about 0% to the first layer 2 with a silicon content of about 20% to 60%. On top of layer 23, loose GeSi 22 is grown with an approximately constant silicon to germanium ratio that approximately corresponds to the maximum ratio of silicon to germanium of graded buffer GeSi layer 21. Thus, the germanium content of the graded buffer layer 21 decreases from surface 11 having a germanium content of about 100% to layer 23 having a germanium content of about 40% to 80%. The GeSi layer 2 is doped with carbon at a carbon proportion of less than 1%. The first layer 2 has an upper surface 12 .

Fig. 10 shows a schematic diagram of the second step of the method according to the second embodiment of the present invention. In a second step, a second crystalline epitaxial layer 9 having a carbon content below 1% is grown on the first layer 2 . The second crystalline epitaxial layer 9 is a strained silicon layer with a thickness below 50 nm. The strained silicon layer 9 has a very low crystal defect density and a high strain. The second layer has an upper surface 19 .

Fig. 11 shows a schematic diagram of the third step of the method according to the second embodiment of the present invention. In a third step, an insulator layer 3 is deposited on the surface 19 of the strained silicon layer 9 . The insulator layer 3 consists of silicon dioxide and/or silicon nitride. The thickness of the insulator layer 3 depends on the target layer signal that has to be transferred to the SiGe/strained silicon layer on the base wafer. The insulator layer 3 has an upper surface 13 .

FIG. 12 shows a schematic diagram of the implantation step applied to the structure 40 shown in FIG. 11 . In the implantation step, the hydrogen species 4 is implanted through the upper surface 13 and the insulator layer 3 up to a layer close to the above-mentioned surface 12 , thus forming the interface between the GeSi layer 2 and the strained silicon layer 9 . Because of the injection, the interface 12 is pre-weakened, so that a predetermined separation zone is formed on the interface 12 .

The implantation is performed with a dose of hydrogen greater than 5 x ¹⁰¹⁴ cm ^-2 at a suitable energy below about 180 keV.

After implantation, the surface 13 is cleaned using standard silicon IC fabrication post-implantation processes. If desired, the insulator layer 3 can be removed and a fresh fresh insulator layer can be deposited. These steps are not shown.

Then, surface treatment is performed on the structure shown in FIG. 12 parallel to the base wafer composed of silicon, germanium, A(III)-B(V)-semiconductor, quartz, glass, or the like. Surface treatment may be performed using chemical mechanical polishing techniques, surface cleaning techniques, oxygen plasma treatment techniques, or the like.

FIG. 13 shows a bonding step for bonding the structure shown in FIG. 12 and the base wafer 6 together. The base wafer 6 is bonded on the surface 13 of the insulator layer 3 . According to another embodiment of the invention, the base wafer 6 may comprise, on its bonding face, an insulator layer bonded to the surface 13 of the insulator layer 3 .

Fig. 14 shows the fourth step of the method according to the second embodiment of the invention. In a fourth step, the structure shown in FIG. 13 is separated into two parts 41 and 42 . The separation step is performed in a separation method similar to the Smart Cut method in which the structure is separated into two parts along a predetermined separation line, for example, using heat treatment or vibration treatment.

In FIG. 14 , the separation line between portions 41 and 42 corresponds to a predetermined separation region on the interface 12 between the first layer 2 and the second strained silicon layer 9 . The first separation part 41 consists of the base wafer 6 on which the insulator layer 3 is formed and has the strained silicon layer 9 on the insulator layer 3 , so that the insulator layer 3 is an intermediate layer between the base wafer 6 and the strained layer 9 . In another embodiment of the invention, there may be additional layers between the base wafer 6 and the insulator layer 3 and/or between the insulator layer 3 and the strained layer 9 . The separation portion 42 is composed of the raw germanium wafer 1 on which the GeSi layer 2 is formed.

FIG. 15 shows a schematic diagram of the final product of the method according to the second embodiment of the invention, corresponding to the separation section 41 shown in FIG. 14 . Thermal annealing can be performed on the structure 41 and the GeSi residues on the strained silicon layer 9 can be removed.

The strained silicon layer 9 of the structure 41 shown in FIG. 15 has a very high strain and a very low defect density, below 10 ⁴ cm ⁻² . The strain of the silicon layer 9 is the strain produced when epitaxially growing a crystalline silicon layer with a thickness of less than 50 nm on a GeSi layer having a germanium content of about 40% to 70%, which is higher than that of a GeSi layer having a germanium content of less than 40%. Strain of prior art silicon layers grown on layers with a thickness below 50nm.

FIG. 16 is a schematic diagram showing the relationship between concentration distribution and thickness of the semiconductor structures shown in FIGS. 2 and 9 . The same reference numerals shown in FIG. 16 as those used in FIGS. 2 and 9 denote the same components as in FIGS. 2 and 9 .

In FIG. 16, a solid line 51 indicates the germanium content of the semiconductor structure shown in FIGS. 2 and 9, which in the germanium substrate 1 is about 100%. The dotted line 52 indicates the silicon content of the semiconductor structure shown in FIGS. 2 and 9, which in the germanium substrate 1 is about 0%. In the graded buffer GeSi layer 21 the silicon content 52 increases from 0% to about 30%, while in the buffer layer 21 the germanium content 51 decreases to a value of about 70%. In FIG. 16, the increase in silicon 52 and the decrease in germanium 51 are shown as continuous. A graded or stepwise change in the silicon and/germanium content in the buffer layer 21 may be used instead of a continuously changing silicon and/germanium content. Additionally, there may be one or more regions within buffer layer 21 where the germanium and/or silicon content does not change.

The germanium to silicon ratio of the loose GeSi layer 22 over the buffer layer 21 is approximately constant, about 30% to 60% silicon, and about 40% to 70% germanium. The loose layer 22 is almost free of dislocations. The crystal defect density of the loose layer 22 is lower than 10 ⁴ cm ^-2 .

Although the preferred embodiment described above uses Smart Cut technology for layer transfer, any other layer transfer technology can be used, such as Bond-and-Etchback technology or other fragilization techniques using porous layer formation processes.

Claims (23)

1. A method of manufacturing a strained crystalline layer on an insulator, the method comprising: providing a semiconductor raw material substrate (1) comprising germanium and/or A(III)-B(V)-semiconductors; In a first step, at least one first crystalline epitaxial layer (2) is provided; In a second step, at least one insulator layer (3) is provided; Wherein the first crystalline epitaxial layer (2) is arranged between the semiconductor raw material substrate (1) and the insulator layer (3), the first crystalline epitaxial layer (2) comprises a buffer layer (21), during the first step, the buffer layer (21) The content of germanium and/or A(III)-B(V)-semiconductor decreases to a ratio of 50% to 80% in the direction from the semiconductor raw material substrate (1) to the insulator layer (3); In a third step, the first crystalline epitaxial layer (2) is separated into two parts; and In a fourth step, at least one second crystalline epitaxial layer (9) is provided on the portion (7) of the first crystalline epitaxial layer (2) on the insulator layer (3) side. 2. The method of claim 1, It is characterized in that the semiconductor raw material substrate (1) is a single crystal germanium wafer, a single crystal A(III)-B(V)-semiconductor wafer, an epitaxial germanium layer or an epitaxial A(III)-B(V)-semiconductor layer. 3. A method according to any one of the preceding claims, It is characterized by In a first step, the silicon content of the buffer layer (21) is increased to a ratio of 20% to 50%. 4. The method of claim 1, It is characterized by The second crystalline epitaxial layer (9) is grown to a thickness below 50nm. 5. The method of claim 1, It is characterized by The first crystalline epitaxial layer (2) and/or the second crystalline epitaxial layer (9) comprises carbon. 6. A semiconductor structure for fabricating a strained crystalline layer on an insulator, the semiconductor structure comprising: a semiconductor raw material substrate (1) consisting of a first material comprising germanium and/or A(III)-B(V)-semiconductors; at least one crystalline epitaxial layer (2); and at least one insulator layer (3); Wherein the at least one crystalline epitaxial layer (2) is an intermediate layer between the semiconductor raw material substrate (1) and the insulator layer (3), and the at least one crystalline epitaxial layer (2) comprises a buffer layer (21), the buffer layer (21) is a composition comprising germanium and/or A(III)-B(V)-semiconductors, the content of germanium and/or A(III)-B(V)-semiconductors is obtained from the semiconductor raw material substrate (1) The direction to the insulator layer (3) is reduced to a ratio of 50% to 80%. 7. The structure of claim 6, It is characterized by The semiconductor raw substrate (1) is a monocrystalline germanium wafer, a monocrystalline A(III)-B(V)-semiconductor wafer, an epitaxial germanium layer or an epitaxial A(III)-B(V)-semiconductor layer. 8. A structure according to claim 6 or 7, It is characterized by The silicon content of the crystalline epitaxial layer (2) increases in the direction from the semiconductor raw substrate (1) to the insulator layer (3). 9. The structure of claim 8, It is characterized by The silicon content is increased to a ratio of 20% to 50%. 10. A semiconductor structure comprising: A semiconductor base substrate (6); at least one insulator layer (3); and at least one first crystalline epitaxial layer (2); at least one strained second crystalline epitaxial layer (9), Wherein the first crystalline epitaxial layer (2) is an intermediate layer between the insulator layer (3) and the strained second crystalline epitaxial layer (9), and the insulator layer (3) is the semiconductor base substrate (6) and the first crystalline epitaxial layer (2) and the first crystalline epitaxial layer (2) comprises a buffer layer (21) which is composed of germanium and/or A(III)-B(V)-semiconductor The content of germanium and/or A(III)-B(V)-semiconductor decreases to a ratio of 50% to 80% in the direction from the strained second crystalline epitaxial layer (9) to the insulator layer (3). 11. The structure of claim 10, It is characterized by The silicon content of the buffer layer (21) increases in the direction from the strained second crystalline epitaxial layer (9) to the insulator layer (3). 12. The structure of claim 11, It is characterized by The silicon content is increased to a ratio of 20% to 50%. 13. The structure of claim 10, It is characterized by The thickness of the strained second crystalline epitaxial layer (9) is less than 50 nm. 14. The structure of claim 10, It is characterized by The first crystalline epitaxial layer (2) and/or the strained second crystalline epitaxial layer (9) comprises carbon. 15. A method of fabricating a strained crystalline layer on an insulator, the method comprising: providing a semiconductor raw material substrate (1) comprising germanium and/or A(III)-B(V)-semiconductors; In a first step, at least one first crystalline epitaxial layer (2) is provided; In a second step, at least one second crystalline epitaxial layer (9) is provided; Wherein the first crystalline epitaxial layer (2) is disposed between the semiconductor raw material substrate (1) and the second crystalline epitaxial layer (9), the first crystalline epitaxial layer (2) comprising a buffer layer (21), during the first step , the germanium and/or A(III)-B(V)-semiconductor content of the buffer layer (21) is reduced to 50% to 80% from the direction of the semiconductor raw material substrate (1) to the second crystalline epitaxial layer (9) proportion; In a third step, at least one insulator layer (3) is provided; wherein the second crystalline epitaxial layer (9) is disposed between the first crystalline epitaxial layer (2) and the insulator layer (3); and In the fourth step, separation is performed between the first crystalline epitaxial layer (2) and the second crystalline epitaxial layer (9). 16. The method of claim 15, It is characterized by The semiconductor raw material substrate (1) is a single crystal germanium wafer, a single crystal A(III)-B(V)-semiconductor wafer, an epitaxial germanium layer or an epitaxial A(III)-B(V)-semiconductor layer. 17. The method of claim 15, It is characterized by The second crystalline epitaxial layer (9) is grown to a thickness below 50nm. 18. A method according to any one of claims 15 to 17, It is characterized by In a first step, the silicon content of the buffer layer (21) is increased to a ratio of 20% to 50%. 19. A semiconductor structure for fabricating a strained crystalline layer on an insulator, the semiconductor structure comprising: a semiconductor raw material substrate (1) consisting of a first material comprising germanium and/or A(III)-B(V)-semiconductors; at least one first crystalline epitaxial layer (2); at least one second crystalline epitaxial layer (9); and at least one insulator layer(3) Wherein the first crystalline epitaxial layer (2) is an intermediate layer between the semiconductor raw material substrate (1) and the second crystalline epitaxial layer (9), and the second crystalline epitaxial layer (9) is formed between the first crystalline epitaxial layer (2) and the second crystalline epitaxial layer (9). An intermediate layer between the insulator layers (3), the first crystalline epitaxial layer (2) comprises a buffer layer (21) comprising germanium and/or A(III)-B(V)-semiconductor The composition, germanium and/or A(III)-B(V)-semiconductor content decreases to a ratio of 50% to 80% in the direction from the semiconductor raw material substrate (1) to the second crystalline epitaxial layer (9). 20. The structure of claim 19, It is characterized by The semiconductor raw substrate (1) is a monocrystalline germanium wafer, a monocrystalline A(III)-B(V)-semiconductor wafer, an epitaxial germanium layer or an epitaxial A(III)-B(V)-semiconductor layer. 21. A structure as claimed in claim 19 or 20, It is characterized by The silicon content of the buffer layer (21) increases in the direction from the semiconductor raw substrate (1) to the insulator layer (3). 22. The structure of claim 21, It is characterized by The silicon content is increased to a ratio of 20% to 50%. 23. The structure of claim 19, It is characterized by The first crystalline epitaxial layer (2) and/or the second crystalline epitaxial layer (9) comprises carbon.

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