CN1281259A - Integration scheme for raising deep groove capacity in semiconductor integrated circuit device - Google Patents

Abstract

A trench capacitor structure suitable for semiconductor integrated circuit devices and a process flow for making the structure. Trench capacitors provide increased capacitance by containing capacitor plates composed of textured hemispherical grains of silicon. In order to reduce the consumption of stored charge in the capacitor, trench capacitors also include buried plates.

Description

An Integrated Solution for Improving Deep Trench Capacitance in Semiconductor Integrated Circuit Devices

The present invention relates generally to semiconductor integrated circuits, and more particularly to deep trench (DT) capacitors fabricated in integrated circuit devices. The present invention also relates to a method of manufacturing a deep trench capacitor in such a semiconductor integrated circuit.

Semiconductor integrated circuit memory stores memory in the form of charges stored on capacitors. The increase in integration density achieved in integrated circuits in recent years has been limited by the amount of charge that can be stored in a capacitor within a given surface area. In order to meet the demand for increased integration, it is necessary to increase the amount of charge stored in a given surface area of a semiconductor integrated circuit device.

In order to increase the amount of charge stored in a capacitor within a given surface area in a memory cell, there are several options: (1) reduce the dielectric thickness, (2) increase the dielectric constant by changing to a different dielectric material, Or (3) increase the surface area of the capacitor. The first option, reducing the dielectric layer thickness, results in increased leakage current, which reduces memory retention and adversely affects device reliability. Changing to a different dielectric material requires significant process development, new integration schemes, and new technologies, which have a significant impact on production costs. Thus, the third option of increasing the surface area of the capacitor is the most preferable way to increase the amount of charge stored within a given surface area.

Trench capacitors have gained popularity in recent years; trench capacitors provide a structure that greatly increases the amount of charge that can be stored per unit surface area of a semiconductor substrate. As the trench depth increases, the amount of charge stored within a given surface area also increases. However, methods of increasing the capacitor area of trench capacitors by making deeper trenches are limited by the manufacturing costs associated with the silicon etch process involved in deep trench fabrication.

Once the trenches are made, this approach is also limited by the processing techniques available to make capacitors in deep trenches. As the aspect ratio of trench capacitors increases (trench depth increases relative to width), it becomes increasingly difficult to fabricate capacitors in trenches. Fabrication of a capacitor in a trench typically requires making a plate in the trench, adding a dielectric to the trench, and then adding another plate to the trench. As the critical dimensions shrink, the process required to create such structures in the trenches becomes less controllable. In addition, this process also complicates the use of deeper trenches to increase capacitance.

The prior art provides methods for fabricating deep trench capacitors. An attractive approach to increasing the amount of charge stored in trenches of a given size, and thus stored by the memory, involves the use of capacitor plates with textured surfaces. A textured surface increases the exposed effective charge storage area within a given cross-sectional area. Thus, it is desirable to manufacture capacitors in which the trench depth is maximized and the texture of the capacitor plate on which the dielectric is deposited is also maximized. As mentioned above, the possibility of fabricating such trench capacitors is limited by the available processing techniques.

The ability to store charge is compromised when the stored charge is depleted due to the physical structure of the capacitor in which it is stored. As the process complexity of integration increases the need to combine greater charge storage capabilities within a given surface area, minimizing the depleted amount of charge stored in the capacitor becomes increasingly important.

As the device size and critical dimensions in device integration shrink and increase, the processing technology must also be improved accordingly. In the semiconductor industry, improvements in device integration are limited by the available processing techniques used to fabricate these devices. It is therefore an object of the present invention to provide associated manufacturing processes capable of producing newly designed structures required for improved integration. This purpose applies to the individual processes and process flows used. The prior art is limited by the processing technology available to produce the devices required in the increased integration scheme.

To achieve this and other objects, and in view of its objects, the present invention provides improvements over existing deep trench capacitor processes that exist in the prior art. This improvement includes increasing the effective capacitor plate area for a given trench size and combining buried plates to minimize charge depletion. The present invention also provides a reliable and repeatable process flow for producing such deep trench capacitors.

In particular, the present invention relates to the fabrication of deep trench capacitor devices in which one capacitor plate is formed from hemispherical grain silicon. Hemispherical grain silicon is made from an amorphous silicon film deposited on the substrate and in the trenches. One electrode plate of the capacitor is made of a partially hemispherical grained silicon film together with a "buried plate". The buried plate is made by doping the semiconductor material that forms the walls of the trench. Part of the hemispherical grained silicon film in contact with the buried plate is doped with the same impurity type as the buried plate. The doped portion of the hemispherical grain silicon combines with the buried plate to form one plate of the capacitor.

The invention also includes the dielectric node material in the trench. A dielectric material covers at least a portion of the hemispherical grain silicon and the buried slab. A conductive material fills the trench to form the second plate of the capacitor such that the dielectric material is located between the first plate of the capacitor and the second plate of the capacitor.

The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various parts of the drawings are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. These drawings include:

1 is a cross-sectional view of a deep trench made in a semiconductor substrate used as a starting point for a process according to the invention;

Figure 2 is a cross-sectional view of the deep trench of Figure 1 after the next step in the process flow according to the present invention;

Figure 3 is a cross-sectional view of the deep trench of Figure 2 after the next step in the process flow according to the present invention;

Figure 4 is a cross-sectional view of the deep trench of Figure 3 after the next step in the process flow according to the present invention;

Figure 5 is a cross-sectional view of the deep trench of Figure 4 after the next step in the process flow according to the present invention;

Figure 6 is a cross-sectional view of the deep trench of Figure 5 after the next step in the process flow according to the present invention;

Figure 7 is a cross-sectional view of the deep trench of Figure 6 after the next step in the process flow according to the present invention;

Figure 8 is a cross-sectional view of the deep trench of Figure 7 after the next step in the process flow according to the present invention;

Figure 9 is a cross-sectional view of the deep trench of Figure 8 after the next step in the process flow according to the present invention;

Figure 10 is a cross-sectional view of the deep trench of Figure 9 after the next step in the process flow according to the present invention;

Figure 11 is a cross-sectional view of the deep trench of Figure 10 after the next step in the process flow according to the present invention;

Figure 12 is a cross-sectional view of the deep trench of Figure 11 after the next step in the process flow according to the present invention;

Figure 13 is a cross-sectional view of the deep trench of Figure 12 after the next step in the process flow according to the present invention;

Figure 14 is a cross-sectional view of the deep trench of Figure 13 after the next step in the process flow according to the present invention;

Figure 15 is a cross-sectional view of the deep trench of Figure 14 after the next step in the process flow according to the present invention;

Figure 16 is a cross-sectional view of the deep trench of Figure 15 after the next step in the process flow according to the present invention;

Figure 17 is a cross-sectional view of the deep trench of Figure 16 after the final step of the process flow according to the present invention;

Figure 18 is a cross-sectional view of a deep trench fabricated in a semiconductor substrate used as a starting point for an alternative embodiment of a process according to the present invention;

19 is a cross-sectional view of the deep trench of FIG. 18 after the next step in the process flow according to an alternate embodiment of the present invention;

Figure 20 is a cross-sectional view of the deep trench of Figure 19 after the next step in the process flow according to an alternate embodiment of the present invention;

21 is a cross-sectional view of the deep trench of FIG. 20 after the next step in the process flow according to an alternate embodiment of the present invention;

22 is a cross-sectional view of the deep trench of FIG. 21 after the next step in the process flow according to an alternate embodiment of the present invention;

23 is a cross-sectional view of the deep trench of FIG. 22 after the next step in the process flow according to an alternate embodiment of the present invention;

24 is a cross-sectional view of the deep trench of FIG. 23 after the next step in the process flow according to an alternate embodiment of the present invention;

25 is a cross-sectional view of the deep trench of FIG. 24 after the next step in the process flow according to an alternate embodiment of the present invention;

Figure 26 is a cross-sectional view of the deep trench of Figure 25 after the next step in the process flow according to an alternate embodiment of the present invention;

27 is a cross-sectional view of the deep trench of FIG. 26 after the next step in the process flow according to an alternate embodiment of the present invention;

28 is a cross-sectional view of the deep trench of FIG. 27 after the final step of the process flow according to an alternate embodiment of the invention.

Reference is now made to the drawings, wherein like reference numerals indicate like elements. FIG. 1 shows a cross-sectional view of a deep trench 1 fabricated in a structure comprising a semiconductor substrate 100 with a top surface 4 . On top surface 4 are deposited a pad oxide film 5 and a pad nitride film 6 (typically silicon nitride). In a preferred embodiment, semiconductor substrate 100 may be a silicon substrate. Deep trench 1 cuts through membranes 4 and 5 and into semiconductor substrate 100 .

The deep trench 1 comprises side walls 2 and a trench bottom 3 . The trench 1 is also determined by the trench depth 8 and the width 9 , the trench depth 8 being the distance from the top surface 4 of the semiconductor substrate 100 to the trench bottom 3 . In a preferred embodiment, the depth 8 may exceed the width by at least 25 times. Also, in a preferred embodiment, depth 8 may be approximately 6 microns and width may be approximately 0.175 microns.

On top of the structure now defined by the top surface 13 of the pad nitride film 6, and on the sidewalls 2 of the deep trench 1, an arsenic silicon glass (ASG) film 7 is formed. The ASG film 7 was made of TEOS (tetraethylorthosilicate) and triethylarsenate. The ASG film 7 is an oxide doped with arsenic (As). In the preferred embodiment, the process conditions for fabricating the ASG film 7 can be determined as a temperature of 650° C. and a pressure of 1 Torr in an LPCVD (low pressure chemical vapor deposition) batch furnace. The thickness of the ASG film 7 is preferably between 500-1000 angstroms. This ASG film 7 will later act as a source of a conductor (arsenic) for doping the trench sidewall 2 to form a buried plate.

Figure 2 is a cross-sectional view showing the next step in the process flow. A photoresist film 11 is applied to the semiconductor substrate 100 and recessed to a depth 10 above the trench bottom 3 . Any suitable photoresist film commonly used in the semiconductor industry may be used, as may any suitable method for applying the photoresist film to semiconductor substrate 100 . The method used for grooving the photoresist film 11 in the trench 1 may be CDE (Chemical Downstream Etching) in the preferred embodiment, but any suitable method commonly used in the art may be used. With the photoresist film 11 in place, an etching process can be used to selectively remove part of the ASG film 7 . In a preferred embodiment, the exposed portion of the ASG film 7 can be cleaned with 40:1 BHF (40 parts water to 1 part buffered hydrofluoric acid in a hydrofluoric acid solution).

Figure 3 shows the structure after only a part of the original ASG film 7 remains; the other parts have been removed by the etching process. FIG. 3 also shows the structure after the photoresist film 11 (shown in FIG. 2 ) is removed. Any photoresist removal method commonly used in the industry can be used to remove the photoresist film 11 . A plasma stripping process can be used in the preferred embodiment.

Figure 4 shows the next step in the process flow. A TEOS (tetraethylorthosilicate) film 12 is deposited on the structure. The TEOS film covers the top of the structure (the top surface 13 of the liner nitride film 6 at this point in the process flow) and covers the sidewalls of the trench 1 . TEOS can be deposited by LPCVD or PECVD (Plasma Enhanced Chemical Vapor Deposition) processes. This oxide film is used as a cap layer to prevent outdiffusion of arsenic from the ASG film 7 in the subsequent process. In a preferred embodiment, the thickness of TEOS film 12 may be between 400-800 Angstroms.

Figure 5 shows the buried slab 14 formed by arsenic diffusion from the portion of the ASG film 7 left after a portion thereof has been selectively removed. An n ⁺ -doped buried plate 14 is formed under the trench bottom 3 and around part of the sidewall 2 of the trench 1 . In one embodiment, the conditions for producing the buried plate 14 can be determined as 2-30 minutes in an inert atmosphere at a temperature of 1050°C. In a preferred embodiment, the process conditions for making the buried slab may include a two-step process, whereby the first step is a furnace treatment in an inert atmosphere such as argon for 2 minutes at a furnace temperature of 1050°C, followed by a dry oxygen atmosphere Heat treatment at 950°C for 10 minutes.

In FIG. 6 a deep trench 1 with side walls 2 and a trench bottom 3 fabricated in a semiconductor substrate 100 now comprising a buried slab 14 formed around the trench 1 is shown. As shown in FIG. 6, the trench 1 is created by removing the ASG film 7 and the TEOS film 12 from the substrate. In the preferred embodiment, both films are removed simultaneously using an etch in a 40:1 BHF solution.

FIG. 7 shows a structure with an amorphous silicon (a-Si) film 16 fabricated on the structure. On the side walls 2 of the deep trench 1, on the bottom 3 of the trench, and on the top surface of this structure, an amorphous silicon film 16 is formed. In a preferred embodiment, the thickness of the amorphous silicon film 16 may be between 100-200 Angstroms. The conditions for forming the amorphous silicon film 16 on the semiconductor substrate 100 in the LPCVD batch reactor may be 500°C and 200 mTorr. The amorphous silicon film 16 may or may not be doped as deposited; it may be doped after deposition. Any suitable doping method commonly used in the art may be used, such as vapor phase doping, hydrogen-free vapor phase doping (where a carrier gas other than hydrogen is used), or plasma doping. In an exemplary embodiment, the vapor phase doping may include arsenic, phosphorus, or diborane. In an alternative embodiment, a portion of the amorphous silicon film 16 can be formed initially on the surface, then doped with an appropriate doping method, and the rest of the film is added to form the amorphous silicon film 16 .

FIG. 8 shows the structure after the amorphous silicon film 16 has been converted into a hemispherical grain silicon (HSG) film 18 . The best process for forming the HSG film 18 from the amorphous silicon film 16 may be to seed the amorphous silicon film 16 with silane (SiH ₄ ) and then anneal. In a preferred embodiment, the process flow may include forming nucleation sites by depositing silane using an LPCVD process. In order to form nucleation sites on the amorphous silicon film 16, a vapor containing silane diluted with helium may be introduced at 550-560°C. The nucleation sites are then annealed to crystallize the amorphous silicon film 16 into the HSG film 18 . The annealing process is carried out in ultra-high vacuum.

After the HSG film 18 is formed, cleaning and etching processes may be used to increase the spacing between grains. Another option for the process flow at this point is to dope the HSG film 18 by means of plasma doping, vapor phase doping, hydrogen-free vapor phase doping, or simply immerse the HSG film 18 in arsine (AsH ₃ ) , followed by heat treatment to drive arsenic from the arsenic source into the HSG film 18 . In a preferred embodiment, heat treatment may be performed at 620°C. If the film is doped to amorphous silicon before the amorphous silicon is converted to HSG, the film may not need to be doped at this point in the process.

FIG. 9 shows silicon nitride film 20 deposited on top surface 13 and on HSG film 18 in trench 1 . The silicon nitride film 20 will be used as a mask in subsequent processes to determine the position of oxide growth in the trench 1 . The optimum process for depositing the silicon nitride film 20 may be an LPCVD process at 770°C and 200 mTorr.

FIG. 10 shows a structure with a photoresist film 22 deposited and recessed in the trench 1 at a depth 24 . As previously mentioned, any photoresist film and any suitable film coating method commonly used in the art may be used. In a preferred embodiment, photoresist film 22 may be grooved to depth 24 using a CDE process.

FIG. 11 shows the structure after the photoresist film 22 has been used as a photolithography mask in the etching process of the silicon nitride film 20 . After etching, only part of the silicon nitride film 20 remains. In the preferred embodiment, the method of etching silicon nitride film 20 may include the use of phosphoric acid at 160-165°C, but any suitable method for removing silicon nitride may be used. After the silicon nitride film 20 is etched to leave only part of the silicon nitride film 20 in the trench 1, the photoresist film 22 is removed from the trench 1. Referring to FIG. Any suitable method of removing photoresist may be used, such as plasma stripping in the preferred embodiment.

FIG. 12 shows the structure after oxide films 26 and 28 have been formed from the exposed HSG not protected by silicon nitride film 20 . In trench 1 , a collar oxide 26 is formed from the exposed HSG film and semiconductor material from sidewall 2 of trench 1 . A thin oxide 28 is also formed from other exposed areas of the HSG film 18 . In a preferred embodiment, the process conditions may be 1050°C in an oxygen atmosphere, and the thickness of the collar oxide 26 may be 300 Angstroms. During this process, backdiffusion of arsenic from the buried plate 14 to the HSG film 18 may occur. This back-diffusion may be necessary if the HSG film 18 was not previously doped.

FIG. 13 shows the structure after the silicon nitride film 20 has been removed. Any suitable method of selectively removing silicon nitride film 20 may be used. In a preferred embodiment, the silicon nitride film 20 may be removed with hot phosphoric acid at 160-165°C.

Figure 14 shows the structure after the thin oxide film 28 has been removed from the top surface 13 of the structure and from the parts of the trench 1 where no collar oxide 26 has been produced. In the preferred embodiment, buffered HF (hydrofluoric acid), ie, a diluted HF solution, is used for oxide removal, but any oxide removal method commonly used in the semiconductor industry may be used.

FIG. 15 shows a structure in which node silicon nitride film 30 has been formed on the structure and in deep trench 1 . The node silicon nitride film 30 can be formed by an LPCVD process. If HSG film 18 has not been doped, the process conditions for depositing node silicon nitride film 30 can be selected to cause arsenic to diffuse from buried plate 14 into HSG film 18 . Alternatively, node silicon nitride film 30 may be deposited by LPCVD at 770°C and 200 mTorr, followed by heat treatment to diffuse arsenic from buried plate 14 into HSG film 18. The silicon nitride film 30 at this node will act as the dielectric of the deep trench capacitor, isolating the two plates of the capacitor.

Figure 16 shows the structure after an arsenic-doped polysilicon film 32 has been added to fill the trench 1 and create the other electrodes of the capacitor. In the preferred embodiment, the arsenic-doped polysilicon film 32 is formed by alternating deposition and doping steps. In the preferred embodiment, the deposition step includes an LPCVD process using silane at 550°C to deposit an intrinsic polysilicon film on the structure. After this deposition process, the structure is dipped in arsine. This process flow is then repeated until the desired doping level is achieved. Trench 1 is then filled with intrinsic polysilicon to produce arsenic-doped polysilicon film 32 . The heat provided in subsequent deposition steps spreads the arsenic throughout the film. In a preferred embodiment, the film may have a total film thickness of 2500 Angstroms.

FIG. 17 shows the completed deep trench capacitor 34 of the present invention. This structure comprises a first plate consisting of a buried plate 14 and a HSG film 18 which may be doped with the same material. A dielectric node material 30 isolates the first plate from a second plate consisting of arsenic-doped polysilicon 32 . FIG. 17 shows the structure after it has been polished down to the original top surface 4 of the silicon substrate 100 . Any suitable method of polishing a semiconductor substrate may be used, such as chemical mechanical polishing (CMP). In a preferred embodiment, the polishing process may include a selective etch process to remove portions of the structure extending over the original semiconductor top surface 4, followed by chemical mechanical polishing to produce an upper surface having a surface substantially coplanar with the original semiconductor top surface 4. surface 35 devices.

Figures 18-26 are cross-sectional views illustrating the process used to fabricate the deep trench capacitor of the present invention in an alternate embodiment. Features of this alternative embodiment include forming the collar oxide prior to forming the buried plate. In this fabrication sequence, buried plates are fabricated later in the trenches in areas not protected by the collar oxide. Furthermore, the HSG film is doped at the same time as the buried slab is made: the dopant species dope the HSG and simultaneously penetrate through it to dope the trench sidewalls.

FIG. 18 shows a deep trench 40 in a semiconductor substrate 101 . Deep trench 40 includes a trench bottom 44 , sidewalls 42 , depth 43 and width 45 . Deep trench 40 is formed in a structure including semiconductor substrate 101 having pad oxide film 46 formed on top thereof and pad silicon nitride film 48 formed on top of pad oxide film 46 . The semiconductor substrate 101 has a top surface 50 . Trench dimensions and aspect ratios can be the same as described in previous embodiments.

FIG. 19 shows the structure after the silicon nitride film 52 has been formed on the structure and in the trench 40 . The silicon nitride film 52 will be used as a mask in subsequent processes to determine where the oxide grows in the trench 40 . The optimum process for forming the silicon nitride film 52 may be an LPCVD process at 770°C and 200 mTorr.

FIG. 20 shows the structure after a photoresist film 54 has been applied and trenches 40 have been grooved to a depth 56 . The photoresist film 54 will be used to photomask the silicon nitride film 52, and the silicon nitride film 52 in the exposed areas will be etched subsequently. Any suitable photoresist film and film coating method commonly used in the art may be used. In a preferred embodiment, the photoresist film 54 in the trench 40 is recessed to a depth 56 using a CDE process.

FIG. 21 shows the structure after the silicon nitride film 52 in the regions not protected by the photoresist film 54 has been selectively removed. After etching, only a portion of the original silicon nitride film 52 remains. The best method for removing silicon nitride may be hot phosphoric acid at 160-165°C, but any suitable method for selectively removing silicon nitride may be used. After selective removal, only a portion of silicon nitride film 52 fills trench 40 to depth 56 . Other regions of the sidewalls 42 of the trench 40 are exposed. The photoresist film 54 (shown in FIG. 20) has been removed. The photoresist film 54 may be removed from the trench 40 by any method suitable in the art. In a preferred embodiment, a plasma stripping method is used.

Figure 22 shows the structure after the collar oxide 58 has been fabricated. Collar oxide 58 is formed by oxidation of the structure of FIG. 21 . In the region of the trench 40 protected by the silicon nitride film 52 (shown in FIG. 21 ), no oxide is formed. The exposed portion of semiconductor substrate 101 along sidewall 42 is consumed to produce collar oxide 58 . A typical process for forming collar oxide 58 would be to heat the semiconductor substrate to 1050°C in an oxygen atmosphere, but any suitable oxidation method could be used. After forming the collar oxide 58, the silicon nitride film 52 is removed. In the preferred embodiment, hot phosphoric acid at 160-165°C is used to remove silicon nitride film 52, but any suitable method may be used.

Turning to FIG. 23 , the structure now includes an amorphous silicon film 60 deposited on top of the structure and in the trench 40 . A typical thickness of the amorphous silicon film 60 may be 100-200 angstroms, and in the preferred embodiment, film deposition may be performed in a LPCVD batch reactor at a temperature of 500°C and a pressure of 200 mTorr.

FIG. 24 shows the structure after the amorphous silicon film 60 has been converted into a hemispherical grained silicon (HSG) film 62 . The process of forming the HSG film 62 from the amorphous silicon film 60 is similar to the process described in FIG. 8 of the previous embodiment.

FIG. 25 shows the structure after the addition of the buried slab 64 . The buried plate 64 is produced by doping the structure. Typical doping processes include plasma doping, plasma impregnation or hydrogen-free vapor phase doping. This doping process will dope both the HSG film 62 and the portion of the trench 40 that is not protected by the collar oxide 58 . In this embodiment, the buried plate 64 and the HSG film 62 in contact with the buried plate 64 are simultaneously doped with the same substance. Together they form one electrode of the trench capacitor.

FIG. 26 shows the structure after a conformal node silicon nitride dielectric film 66 has been formed thereon. The node silicon nitride dielectric film 66 is usually deposited by LPCVD process. The node silicon nitride dielectric film 66 will be used as the dielectric in the capacitor. As shown, the device in FIG. 26 includes a first plate consisting of a buried plate 64 and an HSG film 62 in contact with the buried plate 64 . The capacitor dielectric serves as the node silicon nitride dielectric film 66 .

Figure 27 shows the structure after an arsenic-doped polysilicon film 68 has been added to fill the trench 40 and create the other electrodes of the capacitor. In the preferred embodiment, the arsenic-doped polysilicon film 68 is formed by alternating deposition and doping steps. In the preferred embodiment, the deposition step includes an LPCVD process using silane at 550°C to form an intrinsic polysilicon film on the structure. After this deposition process, the structure is dipped in arsine. This process flow is then repeated until the desired doping level is achieved. Trench 40 is then filled with intrinsic polysilicon to produce arsenic-doped polysilicon film 68 . In a preferred embodiment, the film may have a total thickness of 2500 Angstroms.

FIG. 28 shows the completed deep trench capacitor 70 . This structure includes a first plate consisting of a buried plate 64 and an HSG film 62 . A node silicon nitride dielectric film 66 isolates the first plate from a second plate consisting of arsenic-doped polysilicon film 68 . Figure 28 shows the structure after it has been polished to the original substrate top surface 50. The polishing method is described with reference to FIG. 17 of the previous embodiment. The completed structure includes an upper surface 73 that is substantially coplanar with the original semiconductor top surface 50 .

The foregoing description has been made of the preferred embodiment of the present invention in order to illustrate the gist of the present invention. However, the present invention is not limited to these examples. For example, alternative embodiments may include different process conditions than those detailed above, and may include films having thicknesses outside the ranges detailed above.

The present invention constructively uses a buried plate and a hemispherical grained silicon structure to form the first plate of a deep trench capacitor. The present invention maximizes the capacitor plate surface area in a given trench and minimizes the amount of charge that typically occurs to deplete the capacitor. The foregoing description has been presented for the purpose of describing two embodiments of the present invention. However, those skilled in the art understand that the present invention can be implemented with modifications within the concept and scope of the appended claims.

Claims (34)

1. the groove structure of groove in the definite Semiconductor substrate, the silicon that described groove structure comprises trenched side-wall, mix with the conductive materials in the described Semiconductor substrate around the described trenched side-wall constitutes buries flat board and along the texture silicon structure of the described trenched side-wall of part, contacts with the described flat board of burying to the described texture silicon structure of small part.

2. the groove structure of claim 1, wherein said texture silicon comprises hemisphere grain silicon.

3. the groove structure of claim 1, wherein said texture silicon and the described flat board of burying are combined to form capacitor plate.

4. the groove structure of claim 3, wherein the texture silicon structure uses the material with described conductive materials identical charges type to mix.

5. trench capacitor that is arranged in Semiconductor substrate, described trench capacitor comprises:

Determine the trenched side-wall of groove;

Bury flat board by what doped silicon was formed in the described Semiconductor substrate around the described trenched side-wall;

Along to the hemisphere grain silicon structure of the described trenched side-wall of small part, contact to form first flat board of described trench capacitor with the described flat board of burying to the described hemisphere grain silicon structure of small part;

Dielectric gusset material in the described groove, described gusset material be the described hemisphere grain silicon structure in cover part at least; And

At least the electric conducting material of the described groove of filling part, described electric conducting material forms second flat board of described trench capacitor;

Wherein said dielectric gusset material is deposited between described first flat board and described second flat board.

6. the trench capacitor of claim 5, the electric conducting material of the described groove of wherein said filling part at least comprises the polysilicon of mixing arsenic.

7. the trench capacitor of claim 5 also comprises the neck ring oxide that the electricity that is produced on around the described trenched side-wall is isolated described first flat board.

8. technology of making the trench capacitor in the Semiconductor substrate, described technology comprises:

The Semiconductor substrate that wherein has groove is provided, and described groove has trenched side-wall;

With conductive materials the described Semiconductor substrate of part around the described trenched side-wall is mixed and to bury flat board with formation;

In described groove to the described trenched side-wall of small part the deposition of amorphous silicon layer;

Described amorphous silicon is heated, thereby becomes hemisphere grain silicon on the described trenched side-wall to the described recrystallized amorphous silicon of small part, to the described hemisphere grain silicon of small part with bury dull and stereotyped the contact to small part is described to form first flat board of described capacitor;

At least on the hemisphere grain silicon of the described doping of part, make conformal dielectric node layer; And

Cover described dielectric node layer to form second flat board of described capacitor with electric conducting material.

9. the technology of claim 8 also comprises the step of cleaning and corroding described hemisphere grain silicon.

10. the technology of claim 9 is wherein cleaned and the described step of corroding described hemisphere grain silicon has increased the intercrystalline distance of described hemisphere grain silicon.

11. the technology of claim 8 also comprises and uses and the described identical conductive materials of charge type of burying the described conductive materials in the flat board, and described hemisphere grain silicon is mixed.

12. the technology of claim 11, wherein to described hemisphere grain silicon mix described rapid, comprise described substrate heated, make the described described conductive materials of part of burying in the flat board protect to loose and enter the described hemisphere grain silicon from the described flat board of burying.

13. the technology of claim 11, wherein the described step that described hemisphere grain silicon is mixed comprises no hydrogen and mixes mutually.

14. the technology of claim 11, the described step that described hemisphere grain silicon is mixed wherein comprises and is immersed in AsH ₃In.

15. the technology of claim 14 also comprises described substrate is heated to order about described AsH ₃In arsenic enter in the described hemisphere grain silicon.

16. the technology of claim 8, also be included in the described amorphous silicon of heating with before the described step that forms hemisphere grain silicon, with with the described identical conductive materials impurity of charge type of burying the described conductive materials in the flat board, described amorphous silicon film is mixed, thereby when making, described hemisphere grain silicon is mixed.

17. the technology of claim 16, wherein the described step that described amorphous silicon film is mixed comprises plasma doping.

18. the technology of claim 16, wherein the described step that described amorphous silicon film is mixed comprises gas phase doping.

19. the technology of claim 8, the step of wherein said deposition of amorphous silicon layer comprises the first of the described amorphous silicon film of deposit; Described first to described amorphous silicon film mixes; And the second portion of the described amorphous silicon film of deposit, thereby when making, described hemisphere grain silicon is mixed.

20. the technology of claim 8 wherein covers the described step of described dielectric node layer, comprises to go up substantially with described electric conducting material to fill described groove.

21. the technology of claim 8 also comprises removing and does not contact described step of burying dull and stereotyped described hemisphere grain silicon part.

22. the technology of claim 8, wherein the described step that the described Semiconductor substrate of part is mixed comprises the film that comprises arsenic along described trenched side-wall deposit; Optionally remove described film district from described trenched side-wall; And substrate heated to impel described arsenic to diffuse into the described part of described Semiconductor substrate from described film.

23. the technology of claim 8 also comprises the described hemisphere grain silicon of part on the described trenched side-wall of optionally oxidation to form the step of oxidation film, described oxidation film carries out electricity isolation to described first flat board of described capacitor.

24. the technology of claim 23, wherein optionally the step of the described hemisphere grain silicon of oxidized portion comprises:

Cover described hemisphere grain silicon with silicon nitride film;

Optionally remove the described silicon nitride film of part from described trenched side-wall, to produce the expose portion of the hemisphere grain silicon on the described trenched side-wall;

Described substrate is heated, with the described expose portion of the described hemisphere grain silicon on the described trenched side-wall of oxidation; And

Remove remaining silicon nitride film from trenched side-wall.

25. the technology of claim 8, wherein said electric conducting material are the polysilicons of mixing arsenic.

26. the technology of claim 25 wherein covers the described step of described dielectric node layer, comprises alternately the deposition of intrinsic polysilicon film and described film is mixed.

27. the technology of claim 26, the step of wherein said deposition of intrinsic polysilicon film comprises low pressure chemical vapor deposition.

28. a technology of making the trench capacitor in the Semiconductor substrate, described technology comprises:

The Semiconductor substrate that wherein has groove is provided, and described groove has trenched side-wall;

In described groove to the described trenched side-wall of small part the deposition of amorphous silicon layer;

Described amorphous silicon is heated, thereby become hemisphere grain silicon on the described trenched side-wall to the described recrystallized amorphous silicon of small part;

Mix with the respective regions of conductive materials, with the flat board of burying in the doped region that forms described trenched side-wall and described hemisphere grain silicon to described Semiconductor substrate of part around the described trenched side-wall and the described hemisphere grain silicon that contacts with described part; Describedly bury first flat board that dull and stereotyped and described doped region forms described trench capacitor;

At least on the described doped region of the part of described hemisphere grain silicon, make conformal dielectric node layer; And

Cover described dielectric node layer with electric conducting material, to form second flat board of described trench capacitor.

29. the technology of claim 28 also is included in before the described step of deposition of amorphous silicon layer in the described groove, makes the neck ring oxidation film around the described trenched side-wall of part.

30. the technology of claim 29, wherein said electric conducting material comprises the polysilicon of mixing arsenic.

31. the technology of claim 28, wherein said doping step comprises plasma doping.

32. comprising plasma, the technology of claim 28, wherein said doping step immerses.

33. the technology of claim 28, wherein said doping step comprises no hydrogen and mixes mutually.

34. the trench capacitor structure of claim 5, wherein said groove determines that by the degree of depth and width the described degree of depth surpasses 25 times of described width or more.

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