CN1280688C - Power management system for computer systems - Google Patents

Abstract

A power management system actively adjusts the frequency and voltage of the computer system by hardware. The north bridge chip detects the system execution state, and the south bridge chip transmits the corresponding control signal to the voltage controller and the frequency generator through the System Management Bus (SMBUS) according to the detection result, so as to adjust the voltage and the frequency of the internal components. The invention replaces the control of the software of the operating system by hardware, and provides a faster real-time power-saving mechanism.

Description

Power management system for computer systems

technical field

The invention relates to a computer system power management method, in particular to a computer system power management method and system that can automatically perform power saving management without software control.

Background technique

In today's computer systems, power saving has always been an important issue. Especially more critical on portable computers that use batteries as the main power source. The power management specifications implemented by today's computer systems are mainly derived from the Advanced Configuration and Power Interface (ACPI) specification. Its architecture is shown in Figure 1.

ACPI is a specification for the mutual matching of software and hardware. The principle of power saving is that the operating system detects the operating status, and through the software driver, sends commands according to a specific communication protocol, so that the hardware can reduce the working voltage and frequency according to the design, so as to achieve the purpose of power saving. The known system architecture 100 shown in FIG. 1 includes a software layer 101 , a system hardware layer 103 and an ACPI control layer 112 in between. Known power management is that the operating system power management (OSPM) 106 is executed by the operating system 104 of the system software layer 101, and the execution status of the application program 102 is detected, through the device driver 108 and the ACPI driver/machine language interpreter 110 Issue a command to the ACPI control layer 112 to convert the power saving operation into a hardware signal and send it to the system hardware layer 103 . The ACPI control layer 112 is a structure between hardware and software, including programs, ACPI control tables (tables), and ACPI registers (registers). In the system hardware layer 103 , the control signal is controlled by the south bridge chipset 124 and transmitted to the voltage controller 122 and the frequency generator 126 through the system management bus 128 . The voltage controller 122 can change the operating voltages of the central processing unit 114, the graphic acceleration port 116 and the memory 120 according to the control signal sent from the system management bus 128, and the frequency generator 126 can be used for each according to the control signal sent from the system management bus 128. Hardware components generate different clocks.

Overall, this is a technology in which software controls hardware. Programs and hardware components that support the ACPI standard need to be matched together to complete. Because the operating system and software rely on hardware execution, and the power management of hardware relies on software execution, when the hardware is slowed down due to power-saving mode, the execution performance of the software is also reduced, and there are bottlenecks in control capability and reliability. For example, when the central processing unit 4 enters the C3 sleep state, the contents of the registers are not saved, the cache cannot maintain consistency, and the system cannot accept the master cycle and interrupt service. When the main control request and the interrupt request occur, the operation is resumed, but it is extremely time-consuming. Because all the power-saving status of the hardware is determined by the software, it cannot reflect the real execution status of the hardware in real time, so the power-saving effect is also greatly reduced.

Contents of the invention

In view of this, the object of the present invention is to provide an automatic power management method for automatically adjusting the power consumption of a computer system. The automatic power management method includes the following steps. Firstly, a system flow coding table is established to define the relationship between the load levels and the working parameters of these internal components. Next, a load value of an internal component is detected, and the load value is graded to obtain a load level. Finally, a control signal is obtained by comparing the system flow code table and the load series to adjust the working parameters of the internal components.

The system flow code table is set by the firmware according to the type and characteristics of the system when the system is started. The system flow code table may be a voltage control parameter table, and the working parameter may be a voltage value. If the system flow code table is a frequency control parameter table, the working parameter may be a frequency value. The system internal components can be CPU, memory or graphics acceleration port. power consumption. The power management system includes the following components: a first chip, a second chip, a system management

Another object of the present invention is to provide a power management system for automatically adjusting the bus of a computer system, and a controller. The first chip detects the operating state of the system and generates a load value. The second chip includes a system flow code table for generating a control signal according to the system flow code table and the load value. The system management bus (SMBUS) is used to transmit the control signal, and the controller receives the control signal to adjust the working parameters of an internal component.

Wherein the first chip is a north bridge chip, the second chip is a south bridge chip, and the system management bus follows the communication protocol of the system management bus (SMBUS) to transmit the control signal. The second chip further includes a system flow code table, which is set by the firmware according to the type and characteristics of the system when the system starts up.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is an architectural diagram 100 of a known computer system.

FIG. 2 is a computer system architecture diagram 200 of Embodiment 1 of the present invention.

FIG. 3 is a system flow encoding table 202 of Embodiment 1 of the present invention.

Description of reference symbols

101～software layer 102～application program

103～system hardware layer 104～operating system

106～Operating System Power Management 108～Device Driver

110～ACPI driver 112～ACPI control layer

114～central processing unit 116～graphic acceleration port

118～North Bridge Chipset 120～Memory

122～Voltage Controller 124～South Bridge Chipset

126～frequency generator 128～system management bus

202～system traffic code table 224～South Bridge chipset

Detailed ways

Taking the computer system as an example, since the Southbridge chipset is the key to controlling the frequency and voltage of the entire system, and the electronic circuit can control the power consumption as long as these two elements are mastered, so as long as the Southbridge can accurately and real-time according to the use of the system By automatically controlling the frequency and voltage of the system, the natural system can efficiently control the power supply of the system. And because these controls are all initiated by the South Bridge, the real-time performance is far better than that of software, and the control is closer to the real application of the system.

As shown in FIG. 2, in the computer system architecture 200 of the present invention, the power management does not require the intervention of software. Instead, a group of registers are implemented in the Southbridge chipset 224 to establish the system flow code table 202 as Basis for power saving control. Among the hardware components, the northbridge chipset 118 controls all traffic information to the CPU 114 , graphics acceleration port 116 , memory 120 and the southbridge chipset 224 , which can be said to be the most thorough unit for understanding the system load. Therefore, the north bridge chipset 118 detects various loads of the system, including CPU 114 usage, memory 120 usage, graphics acceleration port 116 usage, etc., and transmits the information to the south bridge chipset 224 . The monitoring of the system load can be a performance of the hardware status, that is, no additional sampling operation is required, and the data itself exists in real time. The system flow code table 202 in the southbridge chipset 224, as shown in Figure 3, can be a usage status list, which is used to define what corresponding voltage or frequency should be under what conditions, for example, when the central processing unit 114 When the usage is less than 1%, the core voltage (Vcore) of the CPU 114 is reduced by 5%, or the frequency (CPUCLK) of the CPU 114 is reduced by 50%. For a 3.3V, 2.4GHz central processing unit, it is to make it work at 3.23V or 1.2GHz. In contrast, the system flow encoding table 202 can simultaneously include voltage and frequency, and even be an overall definition table of other operating parameters of system hardware components, which is not limited to the description in this embodiment. The system flow code table 202 can be automatically generated by the southbridge chipset 224 according to the overall status of the system when the system is started, or it can be a self-determined value fine-tuned by a program. For example, the load classification method, or the rated operating voltage and operating frequency of each component in the system are usually recorded in the firmware when leaving the factory, and these information are read into the South Bridge chipset 224 when starting up to establish The system traffic code table 202 . In addition, through firmware upgrade or software control, the system flow encoding table 202 can also be dynamically set.

Then, by comparing the information from the northbridge chipset 118 with the system traffic code table 202 , the southbridge chipset 224 generates a corresponding control signal, which is sent from the system management bus 128 to the voltage controller 122 and the frequency generator 126 . In this example, the voltage controller 122 has the function of controlling the operating voltages of the CPU 114 , the graphics acceleration port 116 and the north bridge chipset 118 . After receiving the control signal, the voltage controller 122 outputs corresponding operating voltages to these components to make them work within a predetermined range. Relatively, the frequency generator 126 is responsible for generating the working frequency of the corresponding components in the system, and the power saving and power consumption of the components are determined as the frequency increases or decreases. After receiving the control signal, the frequency generator 126 generates a corresponding frequency for each corresponding component.

Wherein, the transmission of the control signal is sent through the system management bus 128 with the SMBUS communication protocol, which is compatible with most known components. Therefore, the architecture can be implemented in existing computer systems without increasing the cost.

Another preferred embodiment is cited with Fig. 2, assume that the normal working voltage of central processing unit 114 is 3.3 volts (V), and the normal working frequency is 2.0G hertz (Hz), and it is known to define in this system traffic coding table 202, When the CPU 114 is under a load of 99%, it is boosted by 1% and overclocked by 10%. When northbridge chipset 118 detects that the workload of central processing unit 114 is 100%, the load value is passed to southbridge chipset 224 and compared with system traffic code table 202, which meets the condition of overclocking, and this southbridge chipset 224 is just for The voltage controller 122 and the frequency generator 126 send out a control signal, so that the voltage controller 122 outputs 3.33V to the CPU 114 , and the frequency generator 126 generates a frequency of 2.2GHz for the CPU 114 . In other words, the architecture of the present invention, within the allowable range of component work, not only effectively solves the known power-saving management problems, but also can generate higher performance than expected when needed.

To sum up, the present invention provides a southbridge chipset 224 for managing system voltage and frequency, which is combined with the Northbridge chipset 118 to complete the monitoring mechanism of internal components of the system, eliminating the inconvenience caused by software monitoring and controlling hardware, and making the system more effective Play to the maximum, while the energy consumption is reduced to the minimum.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims of the present invention.

Claims (13)

1. A power management method, applied in a computer system, can automatically perform power saving management without software control; wherein the computer system includes a plurality of internal components, and the power management method includes the following steps: Establish a system flow code table to define the relationship between the load level and the working parameters of these internal components; Detecting a load value of an internal component through the north bridge chip; classify the load value to obtain a load series; and Comparing the system flow code table and the load level, a control signal is obtained, and the working parameters of the internal components are adjusted through the system management bus according to the control signal. 2. The power management method according to claim 1, wherein the step of establishing the system traffic encoding table comprises: define multiple load stages; and Define operating parameters corresponding to these load levels. 3. The power management method according to claim 2, wherein: The system flow coding table is a voltage control parameter table, and the working parameter is a voltage value. 4. The power management method as claimed in claim 2, wherein: The system flow coding table is a frequency control parameter table, and the working parameter is a frequency value. 5. The power management method as claimed in claim 1, wherein the internal component is a CPU. 6. The power management method as claimed in claim 1, wherein the internal component is a memory. 7. The power management method as claimed in claim 1, wherein the internal component is a graphics acceleration port. 8. A power management system, which is applied to a computer system, can automatically perform power saving management without software control, and includes the following components: A north bridge chip is used to detect the operating state of the computer system and generate a load value; A south bridge chip, including a system flow code table, used to generate a control signal corresponding to the load value; a system management bus for transmitting the control signal; and A controller is used for receiving the control signal and adjusting the working parameters of the internal components of the computer system according to the control signal through the system management bus. 9. The power management system as claimed in claim 8, wherein the south bridge chip further classifies the load value to obtain a load level number, and compares the system flow code table with the load level number to generate the control signal . 10. The power management system as claimed in claim 8, wherein the system management bus transmits the control signal according to the communication protocol of Advanced Power Management Interface. 11. The power management system as claimed in claim 8, wherein the system flow code table is set after the south bridge chip reads a setting value in a firmware when the system is turned on. 12. The power management system of claim 8, wherein: The system flow code table is a voltage control parameter table; and The controller is a voltage controller for receiving the control signal and adjusting the voltage of the internal components. 13. The power management system of claim 8, wherein: The system flow code table is a frequency control parameter table; and The controller is a frequency controller for receiving the control signal and adjusting the frequency of the internal components.

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