CN1277161C - Programmable interrupt controller - Google Patents

Abstract

The present invention relates to a programmable interrupt controller, particularly to an interrupt control device which can select interrupt with the highest priority from plenty of primary device interrupt, slave device interrupt, soft interrupt and external interrupt and send an interrupt request to a processor core (ARM core). The present invention comprises a bus interface module, an interrupt sampling module, an IRQ (interrupt request) logic processing module, an FIQ (fast interrupt request) logic processing module, a priority comparison module and a signal mixing module. The programmable interrupt controller described by the present invention solves the defects of single function, inflexible configuration and bad reusability of interrupt controllers in the prior art; the present invention can be flexibly applied to the design of an SOC (system on chip) and can be flexibly configured according to the requirements of the system.

Description

Programmable Interrupt Controller

technical field

The invention relates to the processing technology of many master interrupts, slave interrupts, soft interrupts and external interrupts on the SOC (system on chip). Specifically, it relates to an interrupt control device that can select the interrupt with the highest priority from many master interrupts, slave interrupts, soft interrupts and external interrupts, and initiate an interrupt request to the processor core (ARM core).

Background technique

Programmable interrupt controller is a module used in SOC (system on chip) design. The SOC design includes many hardware modules and software designs. Many hardware modules will output one or several interrupts, as well as software interrupts and external interrupts. In the entire system, there will be dozens of interrupts, and the processor core (ARM core) only two interrupt request signals can be input, so the interrupt must be processed before entering the processor core. The programmable interrupt controller is used to process the interrupt before entering the processor core.

In the existing technology, the function of the interrupt controller is relatively single, the configuration is inflexible, and the reusability is poor. The interrupt controller generally has several registers: interrupt source register, interrupt mask register, interrupt pending register, and each bit of the register corresponds to an external interrupt source. The interrupt source register receives the interrupt request from the external interrupt source, and the interrupt mask register performs mask detection on the external interrupt source, and the interrupt detected by the mask is put into the interrupt pending register, and the interrupt pending register initiates a bit-OR operation to the processor core. Interrupt, the processor core reads the interrupt pending register, and judges the priority of the interrupt according to the position of the bit, and executes the corresponding interrupt program. The function of the interrupt controller in the prior art is greatly limited, and the interrupt priority, interrupt trigger type, interrupt type, soft interrupt, etc. cannot be flexibly configured, and functions such as interrupt nesting and interrupt sharing are not supported.

The Chinese Patent No. 01101691 is titled: Flexible Interrupt Controller Containing an Interrupt Force Register. This patent solves the configuration of soft interrupts on the basis of ordinary interrupt controllers. It triggers corresponding interrupts by writing interrupt force registers through software, but it cannot flexibly configure interrupt priorities, interrupt trigger types, and interrupt types. Functions such as interrupt nesting and interrupt sharing are not supported.

The US Patent No. 06581120 is entitled: Interrupt Controller. The interrupt controller described in this patent sends an interrupt request to the processor core after the interrupt is detected by the interrupt mask and the priority is judged, and outputs the relevant interrupt source information to the interrupt status module. The interrupt status module generates a register selection signal to the interrupt In the instruction module, the interrupt instruction module selects an interrupt instruction corresponding to the interrupt and provides it to the processor core for reading. The interrupt command module is the logic for storing the interrupt command, and the interrupt command of the corresponding interrupt is written by the software at the time of initialization. It cannot be flexibly configured for interrupt priority, interrupt trigger type, interrupt type, etc. Functions such as interrupt nesting and interrupt sharing are not supported.

The US Patent No. 05603035 is entitled: Programmable Interrupt Controller, Interrupt System and Interrupt Control Process. The patent is configurable for the interrupt priority, internally compares the priority, and supports the nesting of interrupts, but it can configure 8 levels of priority, and it cannot flexibly configure the interrupt trigger type and interrupt type. Functions such as interrupt sharing are not supported.

Contents of the invention

The invention proposes a programmable interrupt controller with comprehensive functions, flexible configuration and good reusability, which mainly solves the problems of relatively single function, inflexible configuration and poor reusability of the interrupt controller in the prior art.

Technical scheme of the present invention is as follows:

The programmable interrupt controller includes a bus interface module, an interrupt sampling module, an IRQ (ordinary interrupt request) logic processing module, a FIQ (fast interrupt request) logic processing module, a priority comparison module and a signal mixing module.

The bus interface module is the interface between the programmable interrupt controller and the APB (Advanced Peripheral Bus) bus, and the bus accesses the registers of the interrupt controller through this module. Various registers are mainly stored in the bus interface module. The processor core can read and write the internal registers of the programmable interrupt controller through the bus. Each module accesses the registers through the interface module.

There are multiple interrupt mode registers inside the bus interface module, and each interrupt corresponds to an interrupt mode register, which records the configuration information of the corresponding interrupt. The interrupt mode register is set by software during initialization, and can also be modified during operation.

There is an interrupt mask register inside the bus interface module, and each bit in the interrupt mask register corresponds to an external interrupt source.

There is an interrupt enable register and an interrupt disable register inside the bus interface module. Used to modify individual bits of the interrupt mask register.

There are multiple interrupt vector registers inside the bus interface module, and each interrupt corresponds to an interrupt vector register, which records the program entry address corresponding to the interrupt. The interrupt vector register is set by software during initialization.

There is an ordinary interrupt vector register and a fast interrupt vector register inside the bus interface module, which are read by the processor core. The normal interrupt vector register is a register that stores the vector of the current highest priority interrupt, and the fast interrupt vector register is a register that stores the fast interrupt vector.

There is an interrupt scene register inside the bus interface module, which is used to store the interrupt scene currently being executed.

There is an interrupt setting register and an interrupt clearing register inside the bus interface module. It is used to initiate or cancel interrupt requests in soft interrupt mode and test mode.

There is an interrupt test mode register inside the bus interface module, which is used to control the programmable interrupt controller to work in normal mode and test mode.

The interrupt sampling module is a module for sampling interrupt sources, and it contains multiple interrupt sampling sub-modules. It samples external interrupts, internal interrupts and soft interrupts, judges the interrupt type, and detects the interrupt mask in the module. When sampling an asynchronous interrupt signal, synchronous processing must be performed at the edge of the module, and processing to eliminate glitches must also be performed. The interrupt sampling module contains multiple interrupt sampling sub-modules, and each interrupt source corresponds to an interrupt sampling sub-module.

The interrupt types supported by the interrupt sampling module are fiq (fast interrupt request) and irq (ordinary interrupt request) modes. By setting the interrupt mode register, each interrupt source can be set to fiq or irq mode, but only one interrupt source can be set to fiq mode. The programmable interrupt controller supports interrupt sharing for level interrupts. The programmable interrupt controller supports soft interrupt mode.

The interrupt trigger types supported by the interrupt sampling module include four modes: low level, high level, rising edge, and falling edge. The software can set the trigger type of the interrupt by setting the interrupt mode register. Interrupt sources can be masked and enabled individually, and software can perform interrupt masking and enabling by writing to the interrupt mask register.

The interrupt sampling module combines level-sensitive, edge-sensitive, soft interrupts and interrupts in test mode, and can issue fiq and irq interrupts. The sampled interrupt is placed in the interrupt request register, and the software can get the current pending interrupt status by reading the register. The irq interrupt line of each sampling module is connected to the interrupt priority comparison module for use when interrupt priority comparison. The fiq interrupt lines of each sampling module are connected to the fiq logic processing module to generate fiq interrupts.

The interrupt sampling sub-module processes the interrupt request through the response signal returned from the signal mixing module, and also processes the interrupt sampling permission. The interrupt sharing of the level interrupt is controlled by sampling permission. Before an interrupt is processed, the programmable interrupt controller will no longer sample the same interrupt.

The priority comparison module is the core module of the programmable interrupt controller, which includes multiple interrupt priority comparison sub-modules. The priority comparison module performs pipeline priority comparison work on all irq interrupts. The priority comparison module compares the priority of each requested interrupt. After the interrupt priority level comparison is completed, relevant information is sent to the IRQ logic processing module.

The priority of the interrupt can be set, and the priority of the interrupt can be modified by writing to the interrupt mode register. The software sets the priority of the interrupt during initialization, and the software can also modify the priority during operation. There are a total of 32 levels of interrupt priority, with level 31 being the highest and level 0 being the lowest. Priority can be set repeatedly.

The priority comparison sub-module is the most basic priority comparison part. It compares the priority of two interrupt sources and outputs a higher priority interrupt for later comparison. The input of each comparison sub-module is two interrupt flags, interrupt mode, interrupt vector, and the output is an interrupt flag, higher priority interrupt mode and vector register. Its priority comparison rules are as follows: first compare the priority of the interrupt, the higher the priority set in the interrupt mode register, the higher the priority of the interrupt (fiq interrupt has the highest priority, which is 31), if two If the priority of the interrupt is the same, compare the code of the interrupt source in the interrupt mode register. The larger the code, the higher its priority.

In the priority comparison module, there are multiple priority comparison sub-modules. Interrupt sources are compared in pairs and output a higher priority interrupt, and then the output interrupts are compared again, and finally a highest priority interrupt is obtained, which is output to the irq logic processing module. This is a typical pipeline comparison method.

The FIQ logic processing module is a module that sends FIQ interrupts to the ARM core, and provides fast interrupt vector registers and interrupt field registers for the bus interface module. When the interrupt sampling module samples a fast interrupt, it sends a corresponding fiq request to the FIQ logic processing module, and the FIQ logic processing module puts the interrupt vector corresponding to the interrupt into the fast interrupt vector register, and sends a fiq interrupt request to the ARM core.

The Irq logic processing module is a module that sends an irq interrupt to the APRM core, and provides a common interrupt vector register and an interrupt field register for the bus interface module. When the interrupt sampling module samples the irq interrupt, it sends an irq request to the priority comparison module, and the priority comparison module obtains a highest priority interrupt through the priority comparison and sends it to the Irq logic processing module, and the irq logic processing module sends the interrupt The corresponding interrupt vector is placed in the ordinary interrupt vector register, and an irq interrupt request is sent to the ARM core.

The programmable interrupt controller supports software interrupt nesting. The interrupt nesting is realized in the software. In order to protect the normal progress of the interrupt and prevent abnormal processing, the interrupt site needs to be protected. In the programmable interrupt controller, the interrupt site register is used to protect the interrupt site, and the interrupt can be normally processed through the operation of the interrupt site register.

The signal mixing module processes the partial response signals generated by the fiq logic processing module and the irq logic processing module and outputs them to the interrupt sampling module or the bus interface module. It also outputs part of the signals of the bus interface module to the fiq logic processing module or the irq logic processing module.

The programmable interrupt controller supports soft interrupt mode for interrupt sources. Soft interrupt mode refers to the interrupt request initiated by software. The software can set each interrupt source to soft interrupt mode by setting the interrupt mode register. After setting to soft interrupt mode, the corresponding interrupt will no longer respond to the request of the external interrupt source until the soft interrupt mode is cancelled. Software can initiate or cancel an interrupt request by setting the interrupt set register and interrupt clear register.

The programmable interrupt controller described in the present invention solves the shortcoming of single function, inflexible configuration and poor reusability of the interrupt controller in the prior art, and it can be flexibly applied in the design of SOC (system on chip), according to the system Flexible configuration is possible.

Description of drawings

Fig. 1 is a structural block diagram of a simple SOC (system on a chip);

Fig. 2 is a structural block diagram of the present invention;

Fig. 3 is the structural block diagram of bus interface module;

Fig. 4 is a structural diagram of the interrupt sampling module;

Fig. 5 is the synchronization circuit of the present invention when sampling the external interrupt source;

Fig. 6 is the deburring circuit of the present invention when sampling the external interrupt source;

Fig. 7 is the structural diagram of priority comparison module;

Fig. 8 is the pipeline comparison method that the present invention adopts when carrying out priority comparison:

Figure 9 is a waveform diagram of the deburring circuit;

Fig. 10 is a flow diagram of software and hardware cooperative processing of a typical interrupt nesting process;

Detailed ways

In the design of SOC (system on chip), the interrupt controller is a necessary module. The invention provides a programmable interrupt controller with comprehensive functions and flexible configuration. The system can configure the programmable interrupt controller according to its own attributes, so that the programmable interrupt controller can meet the requirements of the system. The items configured by the system for the programmable interrupt controller can be: interrupt priority, interrupt trigger type, interrupt type, soft interrupt mode, interrupt test mode, interrupt source can be masked separately, and the interrupt service routine of each interrupt source can also be configured The entry address of . The programmable interrupt controller supports the sharing of level interrupts and can issue fiq or irq interrupts to the processor core.

The present invention can be better understood with reference to FIGS. 1-10. Fig. 1 is a structural block diagram of a simple SOC (system on chip) based on the present invention. The system has ARM core (processor core), SDRAM (synchronous dynamic memory) controller, SRAM (static memory) controller, other modules hanging on the AHB bus (for example: DMA (direct memory access) and other modules), AHB-APB bridge, programmable interrupt controller and other modules hanging on APBbus (for example: Timer (clock), UART (asynchronous serial interface), SSP (synchronous serial interface) and other modules). There can be many modules hanging on the bus, and the modules will generate interrupts. These interrupt requests can be different interrupt priorities, different interrupt trigger types, different interrupt types, and the interrupts of the modules are connected to different programmable interrupt controllers. The software configures the interrupt mode register of each interrupt according to the connection relationship of the hardware, so that the programmable interrupt controller can correctly sample the external interrupt.

Fig. 2 is a structural block diagram of the present invention. It includes bus interface module, interrupt sampling module, IRQ logic processing module, FIQ logic processing module, priority comparison module and signal mixing module.

The bus interface module is the interface between the programmable interrupt controller and the APB bus, and the bus accesses the registers of the interrupt controller through this module. Various registers are mainly stored in the bus interface module. Each sub-module accesses the register through the interface module.

The interrupt sampling module (refer to FIG. 4 ) is a module for sampling interrupt sources, and it includes multiple interrupt sampling sub-modules. It samples external interrupts, internal interrupts and soft interrupts, judges the interrupt type, and detects the interrupt mask in the module. When sampling an asynchronous interrupt signal, synchronous processing (refer to Figure 5) must be performed at the edge of the module, and deburring processing (refer to Figure 6) must also be performed at the same time.

The interrupt sampling module combines level-sensitive, edge-sensitive, soft interrupts and interrupts in test mode, and can issue fiq and irq interrupts. The sampled interrupt is placed in the interrupt request register, and the software can get the current pending interrupt status by reading the register. The ordinary interrupt requests sampled by each sub-module are connected to the interrupt priority comparison module for use in interrupt priority comparison; the fast interrupt requests sampled by each sub-module are connected to the fast interrupt request logic processing module to generate a fast interrupt request interrupt;

The interrupt sampling module processes the interrupt request through the response signal returned from the signal mixing module, and also processes the interrupt sampling permission. The interrupt sharing of the level interrupt is controlled by sampling permission. Before an interrupt is processed, the programmable interrupt controller will no longer sample the same interrupt.

The priority comparison module (refer to FIG. 7 ) is the core module of the programmable interrupt controller, which includes multiple interrupt priority comparison sub-modules. The priority comparison module can perform pipeline interrupt priority comparison (refer to Figure 8). The priority comparison module compares the priority of each common interrupt. The priority is set by the interrupt source mode register and set when the system is initialized. After the interrupt priority level comparison is completed, relevant information is sent to the IRQ logic processing module.

The priority comparison sub-module is the most basic priority comparison part. It compares the priority of two interrupt sources and outputs a higher priority interrupt for later comparison. The input of each comparison sub-module is two interrupt flags, interrupt mode, interrupt vector, and the output is an interrupt flag, higher priority interrupt mode and vector register. Its priority comparison rules are as follows: first compare the priority of the interrupt, the higher the priority set in the interrupt mode register, the higher the priority of the interrupt (fiq interrupt has the highest priority, which is 31), if two If the priority of the interrupt is the same, compare the code of the interrupt source in the interrupt mode register. The larger the code, the higher its priority.

In the priority comparison module, there are multiple priority comparison sub-modules. Interrupt sources are compared in pairs and output a higher priority interrupt, and then the output interrupts are compared again, and finally a highest priority interrupt is obtained, which is output to the irq logic processing module. Because of the comparison method of the pipeline, it takes 5 cycles from the time when the interrupt sampling module outputs an interrupt to when the priority comparison module outputs a highest priority interrupt.

The FIQ logic processing module is a module that sends FIQ interrupts to the ARM core, and provides fast interrupt vector registers and interrupt field registers for the bus interface module. The nesting of interrupts is implemented in software (refer to Figure 10), and the corresponding register operation is read when the ARM responds to the interrupt to ensure that the interrupt controller supports the nesting of interrupts. The process of ARM responding to a fiq interrupt is as follows: After receiving a fiq interrupt, ARM first reads the fiq interrupt vector register, then reads the interrupt field register, pushes it into the stack set by the software, and then executes the interrupt operation. Finally, a data is popped from the stack, the interrupt controller is written to the interrupt field register, and a fiq interrupted routine ends.

The Irq logic processing module is a module that sends an irq interrupt to the ARM core, and provides a common interrupt vector register and an interrupt field register for the bus interface module. The nesting of interrupts is implemented in software (refer to Figure 10), and the corresponding register operation is read when the ARM responds to the interrupt to ensure that the interrupt controller supports the nesting of interrupts. The process of ARM responding to an irq interrupt is as follows: After receiving an irq interrupt, ARM first reads the irq interrupt vector register, then reads the interrupt field register, pushes it into the stack set by the software, and then executes the interrupt operation. Finally, a data is popped from the stack, and the interrupt field register is written to the interrupt controller, and an irq interrupted routine ends.

The signal mixing module processes the partial response signals generated by the fiq logic processing module and the irq logic processing module and outputs them to the interrupt sampling module or the bus interface module. It also outputs part of the signals of the bus interface module to the fiq logic processing module or the irq logic processing module.

Fig. 3 is a structural diagram of the bus interface module of the present invention. The register file contains all the registers used in the programmable interrupt controller; the read logic is the logic for reading the register file; the write logic is the logic for writing the register file; the application logic is to provide the contents of the register file to The logic used by other modules; the modification logic is the logic used by other modules to modify the contents of the register during operation.

Fig. 4 is a structural diagram of the interrupt sampling module of the present invention. It includes multiple interrupt sampling sub-modules, each sub-module samples an external interrupt source, and can output irq interrupt or fiq interrupt. Each interrupt sampling sub-module includes 3 processes: synchronization, deburring, and sampling.

Fig. 5 is the synchronous circuit of the present invention when sampling the external interrupt source. The external interrupt source can be synchronous or asynchronous. Therefore, when the interrupt sampling module samples the external interrupt source, it must first perform synchronous processing to reduce the occurrence of metastability. The metastable state means that when the clock is sampling the signal, it is just on the edge of the signal change, so the sampled signal is unstable. After synchronous processing, the occurrence of metastable conditions can be well reduced. The synchronous circuit described in Fig. 5 is a simple synchronous circuit, which uses a clock to beat the asynchronous signal twice before outputting it.

Fig. 6 is a deburring circuit of the present invention when sampling an external interrupt source. The peripheral module may send out some glitch signals due to other reasons, which may cause misjudgment when the sampling is interrupted. In this way, it is judged whether the signal is glitched or not when the sampling is interrupted. In the circuit described in Figure 6, int_flag is low level, when the interrupt signal int_in after synchronization is high level (refer to Figure 9), the rising edge of clock 1 is sampled to int_in high level, and FF1 outputs the detect signal as high level At this time, the output of FF2 is still at low level; at the rising edge of clock 2, int_in is still at high level, and after int_in and detect are ANDed, it is at high level, and the output of FF2 is at high level, and the programmable interrupt controller samples To a valid interrupt, the output int_out is high, at this time the output of FF1 is low; at the rising edge of clock 3, int_in becomes low, at this time the outputs of FF1 and FF2 are both low, and int_out is only reserved A valid period at the end of which the programmable interrupt controller records the corresponding interrupt as a valid interrupt. Referring to Figure 9, the int_in signal must cross two clock rising edges to ensure that the programmable interrupt controller can sample a valid interrupt. Therefore, the valid period of the interrupt signal sent by the peripheral must span two clock cycles (programmable interrupt control If it does not span two clock cycles, the programmable interrupt controller judges the interrupt request as a glitch signal.

Fig. 7 is a structural block diagram of the interrupt priority comparison module of the present invention. It includes multiple interrupt priority comparison sub-modules. Each interrupt priority comparison sub-module compares the two input interrupt information, outputs the interrupt information of the higher priority interrupt, compares it according to the pipeline method, and finally outputs the interrupt information of the highest priority interrupt.

Fig. 8 is the method adopted by the interrupt priority comparison of the present invention. This is a typical binary tree model. The interrupt information for each external input includes interrupt flag, interrupt mode and interrupt vector. The priority of every two externally input interrupts is compared, and a higher priority interrupt is found for the next level. The higher priority interrupt information output after comparison includes interrupt flag, interrupt mode and interrupt vector; the output interrupt The information is compared again until an interrupt with the highest priority is finally output. This interrupt is provided to the irq logic processing module. The irq logic processing module stores the interrupt vector into the common interrupt vector register and sends out an IRQ interrupt request.

Fig. 10 is a typical irq interrupt processing process of the present invention. This figure is an illustration of the joint operation of software and hardware. The operation in the dashed box is the operation of the hardware, and it is assumed that the first interrupt is processed. After the processor core receives the irq interrupt request from the programmable interrupt controller, it has the following execution steps:

The first step is to read the general interrupt vector register of the programmable interrupt controller, and if it is a fiq interrupt, read the fast interrupt vector register.

The second step is to read the interrupt field register of the programmable interrupt controller, and push the contents of this register into a stack. At this time, the interrupt field register stores the content of the previous state, that is, the state when there is no interrupt.

In the third step, the programmable interrupt controller updates the scene, and the programmable interrupt controller stores some information of the interrupt being processed into the interrupt field register.

In the fourth step, before the software finishes processing the interrupt, the hardware continues to sample other interrupts and perform priority judgment. If there is an interrupt with a higher priority than the interrupt being processed, the programmable interrupt controller sends an irq interrupt request; or the received interrupt For fiq interrupt, the programmable interrupt controller issues fiq interrupt request. At this time, the interrupt routine executed by the software is also interrupted, and the interrupt with higher priority is executed first, and the first, second, and third steps above are repeated. If there is no interrupt or fiq interrupt with higher priority, and The software finishes processing the current interrupt and enters the fifth step.

The fifth step, after the current interrupt is processed, the software pops the data in the stack. If there is interrupt nesting, write 1 to the corresponding nesting flag bit, and if there is no interrupt nesting, write 0 to the corresponding nesting flag bit, and write the data to In the interrupt scene register of the programmable interrupt controller, return to the scene.

In the sixth step, the programmable interrupt controller judges whether there is interrupt nesting according to the returned scene, if there is no nesting, execute the seventh step, and if there is nesting, continue to execute the fourth step.

In the seventh step, the interruption ends.

To sum up, the present invention provides a programmable interrupt controller with comprehensive functions, flexible configuration and good reusability. The invention can be flexibly applied in the design of SOC (system on chip), and the system can configure the programmable interrupt controller according to its own attributes, so that the programmable interrupt controller can meet the requirements of the system.

Claims (3)

1, a kind of programmable interrupt controller comprises bus interface module, interruption sampling module, regular interrupt request logic processing module, quick interrupt request logic processing module, priority comparison module and signal mixing module;

Described bus interface module is the interface of programmable interrupt controller and advanced peripheral bus, in register file is arranged, advanced peripheral bus is visited the register in this module, processor cores can carry out read-write operation to the register in this module by bus, and other each module can be visited the register in this module;

Described interruption sampling module is the module of sampling interrupt source, comprises the submodule that a plurality of structures are identical, interrupts sampling module sampling external interrupt, internal interrupt and soft interruption, judges interrupt type, and carry out the detection of interrupt mask in module; The interruption that samples is placed in the interrupt request register; The regular interrupt request that each submodule samples is connected to the priority of interrupt comparison module, uses when comparing for interrupt priority level; The quick interrupt request that each submodule samples is connected to quick interrupt request logic processing module, produces quick interrupt request and interrupts; Interrupt sampling module and come interrupt request is handled, also the sampling of interrupting is allowed to handle by the response signal of returning from signal mixing module;

Described priority comparison module comprises a plurality of priority of interrupt comparison sub-module; The interrupt priority level that the priority comparison module can carry out the streamline form compares; The priority comparison module carries out the comparison of priority to each regular interrupt; After interrupt priority level is relatively finished, send relevant information to regular interrupt request logic processing module;

Described quick interrupt request logic processing module provides quick interrupt vector register and interrupt spot register for bus interface module; Interrupt sampling module when sampling quick interruption, send corresponding interrupt request fast to quick interrupt request logic processing module, quick interrupt request logic processing module will be interrupted corresponding interrupt vector and will be put in the quick interrupt vector register, and send quick interrupt request interrupt request to processor cores;

Described regular interrupt request logic processing module provides regular interrupt vector registor and interrupt spot register for bus interface module; Interrupt sampling module when sampling regular interrupt, send the regular interrupt request to the priority comparison module, the priority comparison module is given regular interrupt request logic processing module by the interruption that priority ratio draws a limit priority, regular interrupt request logic processing module will be interrupted corresponding interrupt vector and will be put in the regular interrupt vector registor, and send regular interrupt request interrupt request to processor cores.

Described signal mixing module is to export to after the partial response signal of quick interrupt request logic processing module and the generation of regular interrupt request logic processing module is handled to interrupt sampling module or bus interface module; Also the part signal of bus interface module is exported to quick interrupt request logic processing module or regular interrupt request logic processing module.

2, the described programmable interrupt controller of claim 1 is characterized in that, the register file in the described bus interface module comprises:

A plurality of interrupt mode registers, each interrupts corresponding interrupt mode register, is writing down the corresponding configuration information that interrupts;

An interrupt mask register, each corresponding exterior interrupt in the interrupt mask register;

Enable register is gone in an OIER and an interruption, is used for being made amendment in the independent position of interrupt mask register;

A plurality of interrupt vector registers are writing down corresponding program entry address of interrupting;

A regular interrupt vector registor and a quick interrupt vector register read for processor cores;

An interrupt spot register is used for storing the scene of the interruption of current execution;

One interrupts the set register and interrupts clear bit register; Be used in soft interrupt mode and test pattern, initiating or the cancellation interrupt request;

An interrupt test mode register is used for controlling programmable interrupt controller and is operated in normal mode and test pattern.

3, the described programmable interrupt controller of claim 1 is characterized in that, described interruption sampling submodule comprises synchronizing circuit, deburring circuit, sample circuit; In the sampling asynchronous interrupt, synchronizing circuit carries out synchronous processing to the edge of module, and the deburring circuit is eliminated the processing of burr to it.

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