CN1271706C - Collar Dielectric Layer Process to Prevent Top Dimension Expansion of Deep Trench - Google Patents

Abstract

A collar-type dielectric layer process for preventing the top size of deep channel from being enlarged is carried out by ion injection to form an ion injection area on the surface of semiconductor silicon substrate around the top opening of deep channel, removing silicon nitride layer outside the capacitor of deep channel, and growing a first oxide layer on the exposed side wall of deep channel outside the ion injection area. The ion implantation process uses N₂The ion source is used for inhibiting the growth of the first oxide layer, and the depth of the ion implantation area is corresponding to the depth of a preset buried strap diffusion area, at least surrounds a part of the periphery of the top opening of the deep trench and is adjacent to the preset buried strap diffusion area.

Description

Collar Dielectric Layer Process to Prevent Top Dimension Expansion of Deep Trench

technical field

The invention relates to a deep trench capacitor manufacturing process, in particular to a deep trench collar-shaped dielectric layer manufacturing process, which can effectively prevent the top size of the deep trench from expanding.

Background technique

A dynamic random access memory cell (DRAM cell) is composed of a transistor and a capacitor. The current planar transistor design is to match a deep trench capacitor (deep trench capacitor), and the three-dimensional capacitor structure is fabricated in the semiconductor silicon substrate. In deep trenches, the size and power consumption of memory cells can be reduced, thereby speeding up their operation.

As shown in FIG. 1A , it shows a plan view of a conventional deep trench arrangement of DRAM cells. Applied to a folded bit line structure, each active area contains two word lines WL ₁ , WL ₂ and a bit line BL, where the symbol DT represents a deep trench, and the symbol BC represents a bit contact plug.

As shown in FIG. 1B , it shows a schematic cross-sectional view of a deep trench capacitor of a conventional DRAM cell. A deep trench DT is formed in a semiconductor silicon substrate 10, and the region below the deep trench DT is formed as a deep trench capacitor 12, which consists of a buried plate, a node dielectric layer ( node dielectric) and a storage node (storage node). The fabrication method of the deep trench capacitor 12 is as follows. Firstly, a deep trench DT can be formed in the p-type semiconductor silicon substrate 10 by reactive ion etching (RIE). Then, by means of a heavily doped oxide (for example: arsenic glass (ASG)) and a high-temperature short-time annealing process, the n ⁺ type ions can be diffused to the area under the deep trench DT to form an n ⁺ type diffusion region 14, used as the buried electrode plate of the deep trench capacitor 12. Then, a silicon nitride layer 16 is formed on the inner sidewall and bottom of the region below the deep trench trench DT, which is used as a node dielectric layer of the deep trench capacitor 12 . Subsequently, deposit an n ⁺ type doped first polysilicon layer 18 in the deep trench DT, and etch back (recess) the first polysilicon layer 18 to a predetermined depth, then it can be used as a deep trench capacitor 12 storage nodes.

After the above-mentioned deep trench capacitor 12 is completed, a collar dielectric (collar dielectric) layer 20 is formed on the sidewall of the area above the deep trench DT, and then an n ⁺ type doped layer is formed in the area above the deep trench DT. Impurity second polysilicon layer 22, and then continue to make a third polysilicon layer 24. Subsequent processes such as a shallow trench isolation (STI) structure 26 , word lines WL ₁ , WL ₂ , source/drain diffusion regions 28 , bit contact plugs BC and bit lines BL can be performed. The shallow trench isolation structure 26 is used to distinguish two adjacent DRAM cells.

In addition, in order to connect the deep trench capacitor 12 and the transistor on the surface, a buried strapout diffusion region 30 is formed in the silicon substrate 10 around the top opening of the deep trench DT, which is also called a node junction interface ( node junction), which is formed by n ⁺ -type ions in the second polysilicon layer 22 through the third polysilicon layer 24 and outwardly diffused into the adjacent silicon substrate 10 . Therefore, the third polysilicon layer 24 is also called a buried strap 24 . The purpose of the collar dielectric layer 20 is to achieve effective isolation between the buried out-of-band diffusion region 30 and the buried electrode plate 14, so as to prevent the leakage current problem here from affecting the retention time of the DRAM cell.

However, the conventional fabrication of the collar-shaped dielectric layer 20 will increase the size of the top opening of the deep trench DT, which will affect the overlap tolerance between the word line WL and the deep trench DT and the distribution of the buried out-of-band diffusion region 30, In particular, the overlapping edge region L between the source/drain diffusion region 28 and the buried out-of-band diffusion region 30 will be shortened, resulting in a serious leakage current at the buried out-of-band diffusion region 30 and affecting the sub-voltage ( sub-Vt) performance.

As shown in FIGS. 2A to 2E , they are schematic cross-sectional views of a conventional collar-shaped dielectric layer manufacturing process. As shown in FIG. 2A, a p-type semiconductor silicon substrate 10 has completed the fabrication of a deep trench capacitor 12, including: a silicon nitride pad layer 32, a deep trench DT, an n ⁺ -type diffusion region 14, a nitrogen SiO layer 16 and a first polysilicon layer 18 doped with n ⁺ type. Then, as shown in FIG. 2B, after removing the silicon nitride layer 16 in the region above the deep trench trench DT and performing an etch-back step of the first polysilicon layer 18, a first polysilicon layer is grown on the exposed surface of the silicon substrate 10 by an oxidation method. The silicon monoxide layer 34 is used to cover the sidewall of the area above the deep trench DT to ensure the insulating effect between the n ⁺ -type diffusion region 14 and the subsequent buried out-of-band diffusion region 30 . Next, as shown in FIG. 2C , a second silicon oxide layer 36 is deposited by CVD, and then the second silicon oxide layer 36 on top of the first polysilicon layer 18 is removed by anisotropic dry etching.

Subsequently, as shown in FIG. 2D , an n ⁺ type doped second polysilicon layer 22 is deposited in the deep trench DT, and the second polysilicon layer 22 is etched back to a predetermined depth. Finally, as shown in FIG. 2E , wet etching is used to remove part of the first silicon oxide layer 34 and the second silicon oxide layer 36 until the top of the second polysilicon layer 22 protrudes, and the remaining first silicon oxide layer 34 and the second silicon oxide layer 36 are used as a collar dielectric layer 20 .

However, since the oxidation growth process of the first silicon oxide layer 34 will transform a part of the silicon substrate 10 into SiO ₂ , the subsequent wet etching step will expand the opening size of the top of the deep trench DT, thereby shortening the source/drain diffusion region 28 The overlapping edge region L between the buried out-of-band diffusion region 30 further deteriorates leakage current phenomenon and sub-Vt performance. Although the fabrication of the first silicon oxide layer 34 is the most important factor that causes the top opening of the deep trench DT to expand, the oxidation growth step of the first silicon oxide layer 34 is very important. If this step is omitted or the size of the first silicon oxide layer is reduced The thickness of the layer 34 will lead to a more serious junction leakage problem between the n ⁺ -type diffusion region 14 and the buried out-of-band diffusion region 30 . In view of this, under the premise that the oxidation growth step of the first silicon oxide layer 34 must be performed, how to improve the manufacturing process of the collar-shaped dielectric layer so as to avoid enlarging the top opening size of the deep trench DT is the focus of urgent research.

Contents of the invention

The main purpose of the present invention is to provide a collar-shaped dielectric layer process, which can selectively grow silicon oxide on the sidewalls of deep trenches other than the buried out-of-band diffusion region through an ion implantation process, which can effectively prevent deep trenches from The top dimension of the trench expands rapidly in the subsequent etching process.

To achieve the above object, the present invention provides a collar-shaped dielectric layer manufacturing process for preventing the enlargement of the top size of the deep trench, which includes the following steps: providing a semiconductor silicon substrate including a deep trench and a deep trench capacitor. The deep trench capacitor includes a node dielectric layer and a storage node, the node dielectric layer is formed on the sidewall and the bottom of the deep trench, and the storage node is filled into the deep trench to a predetermined depth. An ion implantation process is performed to form an ion implantation region on the surface area of the semiconductor silicon substrate around the top opening of the deep ditch. A portion of the node dielectric layer is removed, so that the node dielectric layer is flush with the top of the storage node, and the sidewall of the deep trench outside the deep trench capacitor is exposed. An oxidation process is performed to grow a first oxide layer on the exposed sidewall of the deep trench outside the ion implantation area.

The ion implantation process utilizes N ₂ as an ion source to suppress the growth of the first oxide layer. The ion implantation region has a depth corresponding to a buried diffusion region, surrounds at least a part of the periphery of the top opening of the deep trench, and is adjacent to a buried diffusion region.

Description of drawings

FIG. 1A shows a plan view of a conventional deep trench arrangement of DRAM cells.

FIG. 1B shows a schematic cross-sectional view of a deep trench capacitor of a conventional DRAM cell.

2A to 2E are schematic cross-sectional views showing a conventional collar-shaped dielectric layer manufacturing process.

3A to 3F are schematic cross-sectional views showing the manufacturing process of the collar-shaped dielectric layer of the present invention.

FIG. 4A shows a schematic cross-sectional view of a DRAM cell used in the collar-shaped dielectric layer manufacturing process of the present invention.

4B and 4C show plan views of the ion implantation region and the deep trench of FIG. 4A.

Symbol Description:

WL ₁ , WL ₂ - character lines;

BL - bit line;

DT-deep trench;

BC-bit contact plug;

10-semiconductor silicon substrate;

12 - deep trench capacitor;

14-n ⁺ type diffusion region;

16-silicon nitride;

18 - the first polysilicon layer;

20-collar dielectric layer;

22 - the second polysilicon layer;

24 - the third polysilicon layer;

26-Shallow trench isolation structure;

28 - source/drain diffusion area;

30 - Buried out-of-band diffusion region;

L - overlapping edge area;

32 - silicon nitride pad;

34 - a first silicon oxide layer;

36 - a second silicon oxide layer;

40-semiconductor silicon substrate;

42 - deep trench capacitor;

44-n ⁺ type diffusion region;

46 - silicon nitride layer;

48 - the first polysilicon layer;

50-collar dielectric layer;

51 - the first silicon oxide layer;

52 - Cushion;

53 - a second silicon oxide layer;

54-ion implantation process;

56-ion implantation area;

I - depth;

58 - second polysilicon layer;

60 - the third polysilicon layer;

62 - Buried out-of-band diffusion region;

64-shallow trench isolation structure;

66 - source/drain diffusion area,

WL ₁ , WL ₂ - character lines;

BL - bit line;

DT-deep trench;

BC-bit contact plug.

Detailed ways

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and in conjunction with the attached drawings, the detailed description is as follows:

The invention provides a collar-type dielectric layer manufacturing process, which is mainly applied to the area above the capacitor of the deep trench trench, which can make the buried out-of-band diffusion area at the top opening of the deep trench trench and the buried electrode plate in the region below the deep trench trench An effective isolation effect is achieved to prevent the leakage current problem here from harming the performance of the sub-voltage (sub-Vt). The collar-shaped dielectric layer manufacturing process of the present invention can be applied to the manufacture of a state random access memory cell (DRAM cell), and its structure can be a planar transistor or a vertical transistor designed to match a deep trench capacitor.

As shown in FIGS. 3A to 3F , they are schematic cross-sectional views of the manufacturing process of the collar-shaped dielectric layer of the present invention.

First, as shown in FIG. 3A , a semiconductor silicon substrate 40 is provided, in which a deep trench capacitor 42 has been fabricated, including a buried electrode plate, a node dielectric layer and a storage node. The fabrication method of deep trench capacitor 42 is as follows. Taking a p-type semiconductor silicon substrate 40 as an example, a deep trench DT can be formed in the silicon substrate 40 by patterning a pad layer 52 and a reactive ion etching (RIE) method. The material of the pad layer 52 can be silicon nitride. Then, by means of a heavily doped oxide (for example: arsenic glass (ASG)) and a high-temperature short-time annealing process, the n ⁺ type ions can be diffused to the area under the deep trench DT to form an n ⁺ type diffusion region 44, used as the buried electrode plate of the capacitor. Then, a silicon nitride layer 46 is formed on the inner sidewall and bottom of the deep trench DT, and then an n ⁺ type doped first polysilicon layer 48 is deposited in the deep trench DT, and the first polysilicon Layer 48 is etched back to a predetermined depth. In this way, the remaining first polysilicon layer 48 is used as a storage node of the capacitor, and the silicon nitride layer 46a interposed between the n ⁺ -type diffusion region 44 and the first polysilicon layer 48 is used as a storage node. Used as a node dielectric layer for capacitors.

Then, as shown in FIG. 3B , before removing the silicon nitride layer 46b in the area above the deep trench DT, an ion implantation process 54 is performed using the silicon nitride layer 46b as a screen layer, so that the deep trench DT An ion implantation region 56 is formed in the surface area of the silicon substrate 40 around the top opening of the trench DT, and the depth I of the ion implantation region 56 is corresponding to the depth of the buried out-of-band diffusion region formed by the subsequent buried band. A preferred ion implantation process 54 is to use N ₂ as an ion source and perform implantation at a tilt angle, and the depth I of the ion implantation region 56 is about 800-1500 Å.

As shown in FIG. 3C, after removing the silicon nitride layer 46b in the area above the deep trench DT, a first silicon oxide layer 51 is grown on the exposed surface of the silicon substrate 40 by an oxidation method to cover the area above the deep trench DT. The sidewalls can ensure the insulating effect between the n ⁺ -type diffusion region 44 and the subsequent buried out-of-band diffusion region. In particular, since the ion implantation region 56 completed in the preceding steps can suppress the transformation of the silicon substrate 40 around the top opening of the deep trench DT into SiO ₂ , the first silicon oxide layer 51 will only grow on the silicon substrate 40 outside the ion implantation region 56 on exposed surfaces.

Next, as shown in FIG. 3D, a second silicon oxide layer 53 is deposited in the deep trench DT by CVD or other deposition methods, and then the first polysilicon layer 48 on the top of the first polysilicon layer 48 is removed by anisotropic dry etching. Silicon dioxide layer 53 .

Subsequently, as shown in FIG. 3E , an n ⁺ type doped second polysilicon layer 58 is deposited in the deep trench DT, and the second polysilicon layer 58 is etched back to a predetermined depth.

Finally, as shown in FIG. 3F , wet etching is used to remove part of the first silicon oxide layer 51 and the second silicon oxide layer 53 until the top of the second polysilicon layer 58 protrudes, and the first silicon oxide layer 51 and the top of the second silicon oxide layer 53 are aligned, then the first silicon oxide layer 51 and the second silicon oxide layer 53 remaining on the sidewall of the area above the deep trench DT are used as a collar dielectric layer 50 .

As shown in FIG. 4A , it shows a schematic cross-sectional view of a DRAM cell used in the collar-shaped dielectric layer manufacturing process of the present invention. After the collar-type dielectric layer 50 process is completed, a third polysilicon layer 60 (also called a buried strap 60), a buried out-of-band diffusion region 62, and a shallow trench isolation (STI) can be performed subsequently. Structure 64 , a word line WL ₁ , WL ₂ , a source/drain diffusion region 66 , a bit contact plug BC, and a bit line BL. These processes do not belong to the technical features of the present invention, so the description is omitted here.

As can be seen from the above, the present invention forms the ion implantation region 56 in the buried out-of-band diffusion region 62 before removing the silicon nitride layer 62b, so that the first silicon oxide layer 51 can be selectively grown outside the buried out-of-band diffusion region 62 On the surface of the silicon substrate 40, the subsequent wet etching step will not expand the top opening size of the deep trench DT. From the results of experimental verification, it can be known that compared with the enlarged size of the top opening of the deep trench DT caused by the known technology, the method of the present invention can reduce the radius of the top opening of the known deep trench DT by about 40-60 Å, so that the source/drain can be prevented. The overlapping edge region between the pole diffusion region 66 and the buried out-of-band diffusion region 62 is shortened, thereby effectively preventing leakage current and improving sub-Vt performance. In addition, the present invention only needs to add an additional ion implantation process to complete the ion implantation region 56, and does not need to consume an additional photoresist definition process, and other process steps can be implemented as usual, so it has the advantages of simplicity and low cost, and can be used in The need for mass production.

As shown in FIGS. 4B and 4C , they show a plan view of the arrangement of the word lines WL1 , WL2 , the deep trenches DT and the bit lines BL of the DRAM cell in FIG. 4A . As shown in FIG. 4B, in a preferred embodiment of the present invention, the ion implantation region 56 using N2 as the ion source and implanting the dip angle is located at a part of the periphery of the top opening of the deep trench DT, and is adjacent to the second The character line WL1. As shown in FIG. 4C , in another preferred embodiment of the present invention, the ion implantation region 56 using N 2 as the ion source and implanting at an angle of inclination angle surrounds the entire periphery of the top opening of the deep trench DT.

Claims (9)

1. A collar-shaped dielectric layer process that prevents the expansion of the top size of the deep ditch, is characterized in that comprising the following steps: providing a substrate having a major surface comprising a deep trench; performing an ion implantation process to form an ion implantation region in the surface area of the semiconductor silicon substrate around the top opening of the deep trench; sequentially forming a first oxide layer and a second oxide layer on the sidewall of the deep trench; filling a layer of material, the layer of material having an upper surface, then removing part of the layer of material such that the upper surface of the material is lower than the main surface of the substrate; and Using the material layer as a mask, etching the first oxide layer and the second oxide layer to define a collar-shaped dielectric layer. 2. The collar-shaped dielectric layer process for preventing the top dimension of the deep trench from expanding according to claim 1, wherein the ion implantation process uses _N2 as an ion source to suppress the growth of the first oxide layer. 3. The collar-shaped dielectric layer manufacturing process for preventing the top of the deep trench from expanding in size as claimed in claim 1, wherein the ion implantation region has a depth corresponding to a buried diffusion zone region. 4. The collar-type dielectric layer process for preventing the top dimension of the deep trench from expanding according to claim 1, wherein the ion implantation region surrounds a portion of the periphery of the top opening of the deep trench and is adjacent to a buried strap diffusion area. 5 . The collar-shaped dielectric layer manufacturing process for preventing the enlargement of the top of the deep trench according to claim 1 , wherein the ion implantation region surrounds the entire periphery of the top opening of the deep trench. 6 . 6 . The collar-shaped dielectric layer manufacturing process for preventing the enlargement of the top of the deep trench according to claim 1 , wherein the ion implantation region has a depth of 800-1500 Å. 7. The collar-shaped dielectric layer manufacturing process for preventing the enlargement of the top of the deep trench according to claim 1, wherein the first oxide layer is formed by an oxidation method. 8. The manufacturing process of the collar-shaped dielectric layer for preventing the enlargement of the top of the deep trench according to claim 1, wherein the formation method of the second oxide layer is a deposition method. 9. The manufacturing process of the collar-shaped dielectric layer for preventing the top dimension of the deep trench from expanding according to claim 1, wherein the method of removing part of the material layer is an etching method.

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