CN1260823C - Electrically Erasable Programmable Logic Elements - Google Patents

Abstract

The invention discloses an electric erasing type programmable logic element, which comprises a P-type substrate; a first N-type ion doped region in the P-type substrate; a first gate on the P-type substrate and adjacent to the first N-type ion doped region, and in floating state for storing data; a second N-type ion doped region located in the P-type substrate and adjacent to the first gate; a second gate as a control gate on the P-type substrate and adjacent to the second N-type ion doped region; and a third N-type ion doped region in the P-type substrate and adjacent to the second gate.

Description

Electrically Erasable Programmable Logic Elements

technical field

The invention relates to an electrically erasable programmable logic element, in particular to an electrically erasable programmable logic element which can be manufactured by using a standard CMOS process, and does not require additional floating gate area to reduce volume.

Background technique

In recent years, with the increasing demand for portable electronic products, the technology and market application of Electrically Erasable Programmable Read-Only Memory (EEPROM for short) are becoming increasingly mature and expanding. The fields of application of EEPROM include products such as digital camera negatives, mobile phones, video game consoles (Video Game Console), personal digital assistant (Personal Digital Assistant, PDA) memory cards, telephone answering devices, and programmable ICs. EEPROM is a kind of non-volatile memory (Non-Volatile Memory). Its operating principle is to control the opening or closing of the corresponding gate channel (channel) by changing the threshold voltage (Threshold Voltage) of the transistor or memory cell. In order to achieve the purpose of storing data, the data stored in the memory will not disappear due to power interruption.

Existing EEPROM technology mostly uses a stacked gate technology, in which a memory cell (Memory Cell) is formed on a substrate (Substrate), which includes a drain, a source, and a stacked gate, The stack gate usually includes a floating gate (Floating Gate) and a control gate (Control Gate), and between the floating gate and the substrate, and between the control gate and the floating gate Between them are separated by two oxide layers. The operating principle of this kind of EEPROM using stacked gate technology is to change the number of electrons stored in the floating gate by applying a high-level voltage to the control gate and using the electron tunneling effect or hot electron injection effect. , and then change the threshold voltage of the floating gate to achieve the purpose of storing data.

However, due to the complex structure of the above-mentioned EEPROM memory cells using the stacked gate technology, it cannot be manufactured using the general standard complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process technology, but must use a more complicated process. Thus, the manufacturing cost is increased. Therefore, the prior art additionally discloses a single-layer polysilicon (Single-Poly) memory cell structure (R.Kazerounian and B.Eitann, "A Single-polyEPROM for custom CMOS logic applications", IEEE Custom Integrated Circuits Conference, P. 59-62, 1986.), please refer to FIG. 1, which shows a side cross-sectional view of an existing single-layer polysilicon memory cell 10, the memory cell 10 is formed on a substrate 12, and it utilizes an N-type well ( N-Well) 14 is used as a coupling gate (Coupling Gate) of a floating gate 16, which is used to couple a high-level voltage (such as 9 to 12V) to the floating gate 16 through the coupling gate, and then Channel hot electrons are formed in the substrate 12 below the floating gate 16, and because the channel hot electrons are injected into the floating gate 16, the threshold voltage of the floating gate 16 is changed to achieve programming of the memory cell 10. the goal of. Since this single-layer polysilicon structure is simple in structure and can be manufactured by standard CMOS technology, it can improve the above-mentioned disadvantage of high cost of memory cells using the stacked gate technology.

However, the above-mentioned existing single-layer polysilicon memory cell 10 still has a major disadvantage, that is, it must utilize a relatively large N-type well 14 to couple the high-level voltage to the floating gate 16. , and the area of the N-type well 14 is usually several times or even tens of times the size of other parts of the memory cell 10. This feature makes it impossible to reduce the volume of the memory based on the single-layer polysilicon memory cell 10. For It is a disadvantage that cannot be ignored in the manufacture of memory.

Contents of the invention

Therefore, the main purpose of the present invention is to provide an electrically erasable programmable logic element, which uses single-layer polysilicon technology, includes a floating gate and a floating ion-doped region, and is used to store data to solve the problem of The above-mentioned problem that the area of the existing single-layer polysilicon storage unit is too large.

For realizing the purpose of the present invention, provide a kind of electrically erasable programmable logic element, it is as the storage cell of a memory, and this electrically erasable programmable logic element comprises a P-type substrate; A first N-type ion-doped region, located in the P-type substrate; a first gate, which is located above the P-type substrate and adjacent to the first N-type ion-doped region, and is in a floating state for storing the electrical The data of the erasable programmable logic element; a second N-type ion-doped region, located in the P-type substrate and adjacent to the first gate, and in a floating state; a second gate, It is the control gate of the electrically erasable programmable logic element, located above the P-type substrate and adjacent to the second N-type ion-doped region; and a third N-type ion-doped region, located The P-type substrate is adjacent to the second gate.

According to the present invention, an electrically erasable programmable logic element as a storage unit of a memory is provided, and the electrically erasable programmable logic element includes:

A P-type substrate;

a first N-type ion-doped region located in the P-type substrate;

A second N-type ion-doped region, a third N-type ion-doped region and a fourth N-type ion-doped region are sequentially formed in the P-type substrate on one side of the first N-type ion-doped region. a heterogeneous region, wherein the first, second, third and fourth N-type ion-doped regions are spaced apart from each other, and the second N-type ion-doped region is electrically connected to the third N-type ion-doped region;

A first gate, which is located above the P-type substrate and adjacent to the first and second N-type ion-doped regions, and is in a floating state, is used to store the electrically erasable programmable logic element data; and

A second gate, which is the control gate of the electrically erasable programmable logic element, is located above the P-type substrate and adjacent to the third and fourth N-type ion-doped regions.

According to the present invention, an electrically erasable programmable logic element as a storage unit of a memory is provided, and the electrically erasable programmable logic element includes:

A P-type substrate;

a first N-type ion-doped region located in the P-type substrate;

A second N-type ion-doped region and a third N-type ion-doped region are sequentially formed in the P-type substrate on one side of the first N-type ion-doped region, wherein the first and the first The second and third N-type ion-doped regions are spaced apart from each other;

A first gate, which is located above the P-type substrate and adjacent to the first and second N-type ion-doped regions, and is in a floating state, is used to store the electrically erasable programmable logic element data; and

A second gate, which is the control gate of the electrically erasable programmable logic element, is located above the P-type substrate and adjacent to the second and third N-type ion-doped regions.

The electrically erasable programmable logic element of the present invention uses a second grid to control the voltage level of a second N-type ion-doped region, and then can control the voltage level of a first grid for the first Channel hot holes or channel hot electrons are generated at the P-type substrate under the gate, and then the channel hot holes or channel hot electrons are used to change the threshold voltage value of the first gate to change the logic The data stored in the component.

Description of drawings

Fig. 1 is the side view sectional view of existing single-layer polysilicon storage unit;

Fig. 2 is the front sectional view of the electrically erasable programmable logic element of the present invention;

Fig. 3 is a front sectional view of an embodiment of the electrically erasable programmable logic element of Fig. 2;

FIG. 4 is a schematic diagram of electrically erasable programmable logic elements of FIG. 3 arranged in an array in a memory;

FIG. 5 is a schematic layout diagram of the memory of FIG. 4; and

6 is a schematic diagram of the distribution of the floating gate channel current versus the floating gate voltage of the electrically erasable programmable logic element of the present invention.

The reference signs in the accompanying drawings are explained as follows:

10 storage units 12, 22, 52 substrates

14N type well 16, 26, 56 floating gate

20, 50 logic elements

24, 28, 32, 54, 58a, 58b, 62N-type ion-doped regions

30, 60 control grid 34, 36, 64, 66 oxide layer

40 memory 68 metal wires

Detailed ways

Please refer to FIG. 2, which shows a front cross-sectional view of an Electrically Erasable Programmable Logic Device (Electrically Erasable Programmable Logic Device) 50 of the present invention. The electrically erasable programmable logic element 50 includes a P-type substrate (P-Type Substrate) 52; a first N-type ion-doped region 54, located in the P-type substrate 52; a first gate 56, which Located above the P-type substrate 52 and adjacent to the first N-type ion-doped region 54, and in a floating (Floating) state, used as a floating gate of the electrically erasable programmable logic element 50 to store The nonvolatile data of the electrically erasable programmable logic element 50; a second N-type ion-doped region 58a, located in the P-type substrate 52 and adjacent to the first grid 56; a third N-type The ion-doped region 58b is located in the P-type substrate 52 and is electrically connected to the second N-type ion-doped region 58b; a second gate 60, which is used as the control gate of the electrically erasable programmable logic element 50, Located above the P-type substrate 52 and adjacent to the third N-type ion-doped region 58b; and a third N-type ion-doped region 62, located in the P-type substrate 52 and adjacent to the second gate 60 catch. As is well known to those skilled in the art, the first gate (i.e. floating gate) 56 and the second gate (i.e. control gate) 60 generally include a first oxide layer 64 and a The second oxide layer 66, as shown in FIG. 2, is located on the bottom side of the floating gate 56 and the control gate 60, and is used to isolate the two gates from the P-type substrate 52, so as to prevent the two gates from contacting the P-type substrate. The substrate 52 is directly contacted to conduct conduction. The electrical connection between the second and third N-type ion-doped regions 58a, 58b can achieve this purpose through various applications. In FIG. 2, a metal wire 68 is used to achieve the connection. Next, an embodiment of the present invention will be listed for detailed description.

Please refer to FIG. 3 , which shows a front cross-sectional view of the electrically erasable programmable logic device 20 of the present invention. Please note that the electrically erasable programmable logic element 20 in FIG. 3 shares the second and third N-type ion-doped regions 58a and 58b of the electrically erasable programmable logic element 50 in FIG. 2 to form a single N-type ion-doped region. The electrically erasable programmable logic element 20 includes a P-type substrate 22; a first N-type ion-doped region 24 located in the P-type substrate 22; a first grid 26 located in the P-type substrate 22 Above and adjacent to the first N-type ion-doped region 24, and in a floating state, it is used as a floating gate of the electrically erasable programmable logic element 20 to store the electrically erasable programmable logic element 20 non-volatile data; a second N-type ion-doped region 28, located in the P-type substrate 22 and adjacent to the first grid 26; a second grid 30, which can be used as an electric erasable The control gate of the programming logic element 20 is located above the P-type substrate 22 and adjacent to the second N-type ion-doped region 28; and a third N-type ion-doped region 32 is located in the P-type substrate 22 and adjacent to the second grid 30 . As is widely known to those skilled in the art, the first gate (i.e. floating gate) 26 and the second gate (i.e. control gate) 30 generally include a first oxide layer 34 and a The second oxide layer 36, as shown in FIG. 3, is located at the bottom side of the floating gate 26 and the control gate 30, and is used to isolate the two gates from the P-type substrate 22, so as to prevent the two gates from being connected to the P-type substrate. The substrate 22 is in direct contact with each other for conduction. Next, a preferred embodiment of the electrically erasable programmable logic device 20 of the present invention as a storage unit of a memory will be described.

Please refer to FIG. 4 and FIG. 5. FIG. 4 shows a schematic diagram of electrically erasable programmable logic elements 20 of the present invention arranged in an array in a memory 40, and FIG. 5 shows the layout of the memory 40 of FIG. 4 ( Layout) schematic diagram. The memory 40 in Fig. 4 can be an electrically erasable programmable read-only memory (i.e. EEPROM) according to different applications, or a single-time programmable memory (One-Time Programmable Memory, OTP Memory), when the memory 40 is When an EEPROM, it can read (Read), program (Program), and clear (Erase) actions, and when the memory 40 is a one-time programmable memory, it only needs to have the functions of reading and programming . As shown in FIG. 4, the memory 40 includes a plurality of electrically erasable programmable logic elements 20 (a logic element 20 in the range of the dotted line in FIG. 4), and the plurality of logic elements 20 include a plurality of columns ( Column) and a plurality of rows (Row) are arranged in an array (Array). In this embodiment, any two adjacent logical elements 20 are configured in a mirrored symmetry (Mirrored Symmetry) manner. For example, if The logic element 20 of a row is that the first N-type ion-doped region 24 is on the left side, and the third N-type ion-doped region 32 is configured in a right-side manner (such as the logic element 20 in Fig. 3 ), then it is located at its The logic elements 20 in the left column and the right column are arranged in such a way that the third N-type ion-doped region 32 is on the left and the first N-type ion-doped region 24 is on the right.

In this embodiment, the connection mode of the memory 40 is as follows, the second gates (control gates) 30 of the logic elements 20 in the same row are all electrically connected to each other and connected to a word line (WordLine) WL The third N-type ion-doped regions 32 of the logic elements 20 in the same column are electrically connected to each other and connected to a power line (Source Line) SL; and the first N-type ion-doped regions of the logic elements in the same row Regions 24 are all electrically connected to each other and to a bit line (Bit Line) BL. According to the position of each logic element 20 as a memory unit in the memory 40 in the array, the word line WL can be sequentially numbered as WL ₀ , WL ₁ , WL ₂ , ..., WL _X , ..., number the power lines SL as SL ₀ , SL ₁ , SL ₂ , ..., SL _X , ..., and number the bit lines BL are BL ₀ , BL ₁ , BL ₂ , . . . , BL _Y , . . . , as shown in FIG. 4 . In addition, as shown in FIG. 5, since the above-mentioned logic elements 20 of any two adjacent columns are arranged in a mirror-symmetrical manner, any two logic elements 20 of any two adjacent columns in the same row can share their adjacent elements in the layout. The two first N-type ion-doped regions 24, while the two logic elements 20 in any adjacent two columns of the same row can also share their adjacent two third N-type ion-doped regions 32 in the layout, so as to save part space.

Next, for the convenience of description, one of the logic elements 20 in the memory 40 in FIG. 4 will be taken as an example to illustrate the operation principle of the logic element 20 as a storage unit. As mentioned above, the first gate 26 in the logic element 20 is in a floating state, that is, there is no external signal or power connected to the first gate 26, and it is used as a floating gate of the logic element 20 pole. The function of the floating gate 26 is very similar to the function of the floating gate in the existing memory cell using the stacked gate technology. It uses the amount of electrons stored in the floating gate 26 to change the floating gate 26. Threshold voltage to achieve the purpose of storing data, that is, when the floating gate 26 is in a high threshold voltage state (High V _TH State), and when the floating gate 26 is in a low threshold voltage state (Low V _TH State) , which respectively represent that the binary digital data stored in the logic element 20 are different values (which may be a logic value “0” or a logic value “1”). The so-called high threshold voltage state refers to that due to the large number of electrons stored in the floating gate 26, if enough electrons are to be attracted in the P-type substrate 22 below the floating gate 26, a trench will be formed. To electrically connect the first N-type ion-doped region 24 and the second N-type ion-doped region 28, the floating gate 26 will need a relatively high voltage value; similarly, the so-called low threshold voltage state refers to Since there are a large number of holes stored in the floating gate 26, if enough electrons are to be attracted in the P-type substrate 22 below the floating gate 26 to form a channel to electrically connect the first N-type The ion-doped region 24 , the second N-type ion-doped region 28 , and the floating gate 26 only need to have a relatively low voltage. In the following description of this embodiment, the floating gate 26 will be in a high threshold voltage state to represent the logical value "0" stored in the logic element 20, and the floating gate 26 will be in a low threshold voltage state to represent the logic element. 20 stores the logical value "1" as an example, however, the definition contrary to the above design also falls within the scope of the present invention.

Please refer to FIG. 6, which shows a schematic diagram of the distribution of the gate current of the floating gate 26 of the electrically erasable programmable logic element 20 of the present invention to the voltage of the floating gate 26, wherein the horizontal axis represents the floating gate The voltage of the pole 26, and the vertical axis represents the gate current of the floating gate 26. Please note that the gate current of the floating gate 26 shown in FIG. 6 only shows the absolute value of the channel current and does not show its flow direction, and the mark CHH in different intervals represents that it is channel heat. The gate current caused by holes (Channel Hot Hole), and the symbol CHE represents the gate current caused by channel hot electrons (Channel Hot Electron). It can be seen from the figure that when the voltage value of the floating gate 26 changes from small to large (for example, from -3V to 7V), there will first be a section (marked by CHH) showing channel hot holes. The effect is more significant, and then there will be another interval (marked by CHE) showing that the channel hot electron effect is more significant. This phenomenon that the gate current is formed by channel hot holes and channel hot electrons is because when the floating gate 26 and the control gate 30 are turned on at the same time, the electrons will pass through the two conducting gates 26 and 30. The channel below flows between the third N-type ion-doped region 32 and the first N-type ion-doped region 24, and some of these electrons will be in the first N-type ion-doped region 24 and the P-type substrate The PN junction (PN Junction) of 22 collides with electron-hole pairs, and the electron-hole pairs will respectively flow into the floating gate 26 and the P-type substrate 22 according to different voltage levels, thus generating the gate current.

Since the floating gate 26 of the logic element 20 of the present invention is in a floating state, the voltage level generated by it is controlled by the first N-type ion-doped region 24 (that is, the bit line BL), the P-type substrate 22, and The voltage level of the second N-type ion-doped region 28 is obtained by coupling according to a certain ratio. That is to say, if the voltage of the bit line BL is V _BL , the voltage of the P-type substrate 22 is V _PS , and the voltage of the second N-type ion-doped region 28 is V _X , then the voltage of the floating gate is The flat V _FG can be expressed as the following relationship:

V _FG = α ₁ V _BL + α ₂ V _PS + α ₃ V _X

Among them, α ₁ , α ₂ , and α ₃ are three coefficients representing different proportions. Since the second N-type ion-doped region 28 of the logic element 20 of the present invention is also in a floating state, its voltage level is controlled by the voltage level V _SG of the control gate 30 (that is, the word line WL). The resistance value of the channel below determines the coupling degree of the voltage level V _SL located in the third N-type ion-doped region 32 (that is, the power line SL) to the second N-type ion-doped region 28 . In this embodiment, the programming and clearing operations of the logic element 20 of the present invention are to fix the above-mentioned parameters such as V _BL , V _PS , V _SL and so on, and only change the voltage value of V _SG to change the floating gate The voltage level V _FG of the electrode 26 operates within the range of CHH or CHE to achieve the purpose of changing the amount of electrons stored in the floating gate 26 , that is, to change the critical voltage state of the floating gate 26 . Next, the operating principle of the reading, programming, and clearing actions of the logic element 20 of the present invention in this embodiment will be described in detail.

When the memory 40 intends to read a selected logic element 20 as its storage unit, it grounds the first N-type ion-doped region 24 (that is, the bit line BL), and makes the control gate 30 ( That is, the voltage level of the word line WL) exceeds the voltage level of the third N-type ion-doped region 32 (ie, the power line SL) by a predetermined value (usually the threshold voltage of the control gate 30), so that the voltage level under the control gate 30 A channel is formed in the P-type substrate 22 to conduct the second N-type ion-doped region 28 and the third N-type ion-doped region 32 . In this embodiment, the control gate 30 receives 1.8V through the word line WL, and the third N-type ion-doped region 32 receives 1V through the power line SL. Please note that the control gates 30 and the third N-type ion-doped region 32 of other unselected logic elements 20 are both input with 0V. At this time, if the floating gate 26 is in a high threshold voltage state, that is, when the data stored in the logic element 20 is a logic value "0", then the first N-type ion-doped region 24 and the floating gate 26, the second The potential difference between the two N-type ion-doped regions 28 will not be enough to conduct the channel below the floating gate, so a sense amplifier (Sense Amplifier, not shown in the figure) will read from the bit line BL Takes out the logical value "0". Conversely, if the floating gate 26 is in a low threshold voltage state, that is, when the data stored in the logic element 20 is a logic value “1”, the first N-type ion-doped region 24 and the floating gate 26, The potential difference between the second N-type ion-doped region 28 will be sufficient to conduct the channel below the floating gate, so a sense amplifier (Sense Amplifier, not shown in the figure) will read from the bit line BL Takes out the logical value "1". Please note that the sense amplifier mentioned above can be changed correspondingly according to different requirements and different voltage level designs.

When the memory 40 intends to program a selected logic element 20 as its memory cell, it electrically connects the first N-type ion-doped region 24 (that is, the bit line BL) to a high potential, and connects the third The N-type ion-doped region 32 (that is, the power line SL) is grounded, and the control gate 30 (that is, the word line WL) is electrically connected to a preset voltage value so that the P-type substrate 22 below the floating gate 26 Channel hot holes are formed, and the preset voltage is within the CHH interval in FIG. 6 to ensure the formation of channel hot holes. In this embodiment, the first N-type ion-doped region 24 receives 8V through the bit line BL, and the control gate 30 receives 4V through the word line WL. Please note that the first N-type ion-doped region 24 and the control gate 30 of other unselected logic elements 20 are both input with 0V. At this time, if the floating gate 26 is in a high threshold voltage state, that is, when the data stored in the logic element 20 is a logic value "0", since a large number of electrons are stored in the floating gate 26, the floating The gate 26 will continue to attract the channel hot holes formed in the P-type substrate 22 below it until there are a large number of holes stored in the floating gate 26, so the floating gate 26 will pass through This process transitions to a low threshold voltage state, that is, the data stored in the logic element 20 is programmed to a logic value "1". And if the floating gate 26 is in a low threshold voltage state, that is, when the data stored in the logic element 20 is a logic value "1", then since the floating gate 26 originally stores a large number of holes, the It will not be changed due to the existence of channel hot holes, that is, the data stored in the logic element 20 will continue to maintain the logic value “1”.

When the memory 40 is going to clear a selected logic element 20 as its memory cell, it will electrically connect the first N-type ion-doped region 24 (that is, the bit line BL) to a high potential, and connect the third The N-type ion-doped region 32 (that is, the power line SL) is grounded, and the control gate 30 (that is, the word line WL) is electrically connected to a preset voltage value so that the P-type substrate 22 below the floating gate 26 Channel hot electrons are formed, and the preset voltage is within the CHE interval in FIG. 6 to ensure the formation of channel hot electrons. In this embodiment, the first N-type ion-doped region 24 receives 8V through the bit line BL, and the control gate 30 receives 1V through the word line WL. Please note that the first N-type ion-doped region 24 and the control gate 30 of other unselected logic elements 20 are both input with 0V. At this time, if the floating gate 26 is in a low threshold voltage state, that is, when the data stored in the logic element 20 is a logic value "1", since there are a large number of holes stored in the floating gate 26, the floating The set gate 26 will continue to attract the channel hot electrons formed in the P-type substrate 22 below it until there are a large number of electrons stored in the floating gate 26, so the floating gate 26 passes through this A process transitions to a high threshold voltage state, that is, the data stored in the logic element 20 is cleared to a logic value “0”. And if the floating gate 26 is in a high threshold voltage state, that is, when the data stored in the logic element 20 is a logic value "0", then since the floating gate 26 originally stores a large number of electrons, its There will be no change due to the presence of channel hot electrons, that is, the data stored in the logic element 20 will continue to maintain a logic value of “0”.

Compared with the prior art, the electrically erasable programmable logic element of the present invention uses a second gate to control the voltage level of a second N-type ion-doped region, thereby being able to control the voltage of a first gate level to generate channel hot holes or channel hot electrons at the P-type substrate under the first gate, and then use the channel hot holes or channel hot electrons to change the threshold of the first gate voltage value to change the data stored in the logic element. Therefore, the electrically erasable programmable logic element of the present invention is different from the single-layer polysilicon storage unit using a large-area coupled N-type well in the prior art, and has the advantages of reducing cost and volume.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention are covered by the patent of the present invention.

Claims (28)

1. An electrically erasable programmable logic element as a storage unit of a memory, the electrically erasable programmable logic element comprising: A P-type substrate; a first N-type ion-doped region located in the P-type substrate; A second N-type ion-doped region, a third N-type ion-doped region and a fourth N-type ion-doped region are sequentially formed in the P-type substrate on one side of the first N-type ion-doped region. a heterogeneous region, wherein the first, second, third and fourth N-type ion-doped regions are spaced apart from each other, and the second N-type ion-doped region is electrically connected to the third N-type ion-doped region; A first gate, which is located above the P-type substrate and adjacent to the first and second N-type ion-doped regions, and is in a floating state, is used to store the electrically erasable programmable logic element data; and A second gate, which is the control gate of the electrically erasable programmable logic element, is located above the P-type substrate and adjacent to the third and fourth N-type ion-doped regions. 2. The electrically erasable programmable logic element as claimed in claim 1, wherein the first gate comprises a first oxide layer located on the bottom side of the first gate for isolating the P-type substrate and the first gate. 3. The electrically erasable programmable logic device as claimed in claim 1, wherein the second gate comprises a second oxide layer located on the bottom side of the second gate for isolating the P-type substrate and the second gate. 4. The EEPLD as claimed in claim 1, wherein the memory is an EEPROM. 5. The electrically erasable programmable logic device as claimed in claim 1, wherein the memory is a one-time programmable memory. 6. The electrically erasable programmable logic device as claimed in claim 1, wherein a plurality of the electrically erasable programmable logic devices serving as storage units of the memory are arranged in an array. 7. The electrically erasable programmable logic element as claimed in claim 6, wherein among the plurality of electrically erasable programmable logic elements arranged in an array, the electrically erasable programmable logic element located in the same column The second gates of the arrays are all electrically connected to each other and to a word line, and the fourth N-type ion-doped regions of the electrically erasable programmable logic elements in the same column are also electrically connected to each other and to a source Wire. 8. The electrically erasable programmable logic element as claimed in claim 6, wherein among the plurality of electrically erasable programmable logic elements arranged in an array, the electrically erasable programmable logic elements of two adjacent columns It is configured in a mirror-symmetric manner. 9. The electrically erasable programmable logic element as claimed in claim 8, wherein the electrically erasable programmable logic element located in two adjacent columns of the same row shares its adjacent two first N-type ion-doped region, and the shared two first N-type ion-doped regions are electrically connected to a bit line. 10. The electrically erasable programmable logic element as claimed in claim 8, wherein the electrically erasable programmable logic element located in two adjacent columns of the same row shares its adjacent two fourth N-type ion-doped region, and the shared two fourth N-type ion-doped regions are electrically connected to a source line. 11. The electrically erasable programmable logic element as claimed in claim 6, wherein among the plurality of electrically erasable programmable logic elements arranged in an array, the electrically erasable programmable logic element located in the same row The first N-type ion-doped regions are all electrically connected to each other and connected to a bit line. 12. The electrically erasable programmable logic element according to claim 1, when the memory cell is to be read, the first N-type ion-doped region is grounded, and the potential of the second gate exceeds The potential of the fourth N-type ion-doped region is a predetermined value, so that a channel is formed in the P-type substrate below the second grid so that the third N-type ion-doped region and the fourth N-type The ion-doped region conducts. 13. The electrically erasable programmable logic device according to claim 1, when the memory cell is to be programmed, the first N-type ion-doped region is electrically connected to a high potential, and the fourth The N-type ion-doped region is grounded, and the second gate is electrically connected to a voltage value to form channel hot holes in the P-type substrate under the first gate to program the first gate. 14. The electrically erasable programmable logic device according to claim 1, when the memory cell is to be cleared, the first N-type ion-doped region is electrically connected to a high potential, and the fourth The N-type ion-doped region is grounded, and the second gate is electrically connected to a voltage value to form channel hot electrons in the P-type substrate under the first gate to clear the first gate. 15. An electrically erasable programmable logic element as a storage unit of a memory, the electrically erasable programmable logic element comprising: A P-type substrate; a first N-type ion-doped region located in the P-type substrate; A second N-type ion-doped region and a third N-type ion-doped region are sequentially formed in the P-type substrate on one side of the first N-type ion-doped region, wherein the first and the first The second and third N-type ion-doped regions are spaced apart from each other; A first gate, which is located above the P-type substrate and adjacent to the first and second N-type ion-doped regions, and is in a floating state, is used to store the electrically erasable programmable logic element data; and A second gate, which is the control gate of the electrically erasable programmable logic element, is located above the P-type substrate and adjacent to the second and third N-type ion-doped regions. 16. The electrically erasable programmable logic element as claimed in claim 15, wherein the first gate comprises a first oxide layer located on the bottom side of the first gate for isolating the P-type substrate and the first gate. 17. The electrically erasable programmable logic device as claimed in claim 15, wherein the second gate comprises a second oxide layer located on the bottom side of the second gate for isolating the P-type substrate and the second gate. 18. The EEPLD of claim 15, wherein the memory is an EEPROM. 19. The electrically erasable programmable logic device of claim 15, wherein the memory is a one-time programmable memory. 20. The electrically erasable programmable logic device as claimed in claim 15, wherein a plurality of the electrically erasable programmable logic devices serving as storage units of the memory are arranged in an array. 21. The electrically erasable programmable logic element as claimed in claim 20, wherein among the plurality of electrically erasable programmable logic elements arranged in an array, the electrically erasable programmable logic element located in the same column The second gates of the arrays are all electrically connected to each other and to a word line, and the third N-type ion-doped regions of the electrically erasable programmable logic elements in the same column are also electrically connected to each other and to a source Wire. 22. The electrically erasable programmable logic element as claimed in claim 20, wherein among the plurality of electrically erasable programmable logic elements arranged in an array, the electrically erasable programmable logic elements of two adjacent columns Configured in mirror-symmetrical fashion. 23. The electrically erasable programmable logic element as claimed in claim 22, wherein the electrically erasable programmable logic element located in two adjacent columns of the same row shares its adjacent two first N-type ion-doped region, and the shared two first N-type ion-doped regions are electrically connected to a bit line. 24. The electrically erasable programmable logic element as claimed in claim 22, wherein the electrically erasable programmable logic element located in two adjacent columns of the same row shares its adjacent two third N-type ion-doped region, and the shared two third N-type ion-doped regions are electrically connected to a source line. 25. The electrically erasable programmable logic element as claimed in claim 20, wherein among the plurality of electrically erasable programmable logic elements arranged in an array, the electrically erasable programmable logic element located in the same row The first N-type ion-doped regions are all electrically connected to each other and connected to a bit line. 26. The electrically erasable programmable logic element according to claim 15, when the memory cell is to be read, the first N-type ion-doped region is grounded, and the potential of the second gate exceeds The potential of the third N-type ion-doped region is a predetermined value, so that a channel is formed in the P-type substrate under the second grid so that the second N-type ion-doped region and the third N-type ion The doped region conducts. 27. The electrically erasable programmable logic device according to claim 15, when the memory cell is to be programmed, the first N-type ion-doped region is electrically connected to a high potential, and the third The N-type ion-doped region is grounded, and the second gate is electrically connected to a voltage value to form channel hot holes in the P-type substrate under the first gate to program the first gate. 28. The electrically erasable programmable logic device according to claim 15, when the memory cell is to be cleared, the first N-type ion-doped region is electrically connected to a high potential, and the third The N-type ion-doped region is grounded, and the second gate is electrically connected to a voltage value to form channel hot electrons in the P-type substrate under the first gate to clear the first gate.

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