CN1260803C - A method for forming shallow grooves - Google Patents

Abstract

The invention provides a method for forming a groove structure, which at least comprises the following steps: forming a pad oxide layer on a substrate; forming a first polysilicon layer on the pad oxide layer; forming an oxide layer on the first polysilicon layer; forming a second polysilicon layer on the oxide layer; removing part of the second polysilicon layer, the oxide layer, the first polysilicon layer and the pad oxide layer to expose part of the substrate; and etching the second polysilicon layer and part of the substrate to form a trench structure in the substrate and expose the oxide layer. The etching depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

Description

A method for forming shallow grooves

technical field

The invention relates to a method for forming shallow trenches, in particular to a method for forming shallow trenches that can reduce micro-loading and corner recesses during formation of shallow trenches.

Background technique

The disadvantage of traditional area oxide isolation devices is that they are prone to defect formation due to the high stress generated in the narrow active region under the nitride layer during field oxidation; secondly, defects are also easily generated due to the Kooi effect. When the geometric size gradually shrinks, the bird's beak encroachment occupies most of the oxygen surface area of the field, which is more likely to lead to the formation of defects. Therefore, when isolating semiconductor elements below 0.35 microns, it is very important to overcome the shortcomings of traditional methods to form good isolation regions.

It is a practice to use shallow-trench isolation (shallow-trench isolation) technology to isolate components during the fabrication of integrated circuits. Generally, steep trenches are formed on a semiconductor substrate using silicon nitride as a mask and anisotropic etching process. Next, the trench is filled with oxide to form a shallow trench isolation device whose surface is at the same level as the surface of the substrate.

Unfortunately, for highly integrated circuits, when etching the shallow trench structure, there will be microloading; such time-mode etching makes it difficult to control the depth of the shallow trench structure. After the STI is formed, the problem of corner dishing can also lead to the degradation of the STI.

In any case, when forming shallow trench isolation devices, how to improve their characteristics and reduce the reliability degradation of semiconductor devices is a very important issue.

Contents of the invention

In view of the above-mentioned background of the invention, the present invention provides a method for forming shallow trench isolation devices; the depth of the trench is controlled by the thickness of the polysilicon, rather than the traditional time-mode (time-mode) control

Another object of the present invention is to provide a method for forming a trench isolation device. The use of the polysilicon layer can avoid the micro-loading phenomenon and the Kooi effect during the formation of the trench isolation device.

Another object of the present invention is to provide a method for forming a trench isolation device; when forming the liner layer of the trench, the oxidation of the polysilicon layer can avoid the occurrence of recessed corners of the trench.

According to the purpose described above, a method for forming a trench structure is disclosed, at least comprising: forming a pad oxide layer on the substrate; forming a first polysilicon layer on the pad oxide layer; forming an oxide layer on the first polysilicon layer on the silicon layer; forming a second polysilicon layer on the oxide layer; removing part of the second polysilicon layer, the oxide layer, the first polysilicon layer and the pad oxide layer to expose part of the substrate; and etching the second polysilicon layer The two polysilicon layers and part of the substrate form a trench structure in the substrate and expose the oxide layer. The etch depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer.

Description of drawings

The present invention can have a deeper understanding with the following figures:

FIG. 1A to FIG. 1F are a series of schematic cross-sectional views of shallow trench isolation devices formed by the method of the present invention.

Detailed ways

The semiconductor design of the present invention can be widely applied in many semiconductor designs, and can utilize many different semiconductor materials to make, when the present invention illustrates the method of the present invention with a preferred embodiment, those who are familiar with this field should recognize It is known that many steps can be changed, and materials and impurities can also be replaced, and these general replacements undoubtedly do not depart from the spirit and scope of the present invention.

Secondly, the present invention is described in detail as follows with schematic diagrams. When describing the embodiments of the present invention in detail, the cross-sectional view showing the semiconductor structure will not be partially enlarged according to the general scale in the semiconductor manufacturing process for the convenience of explanation, but it should not be used as a limiting cognition. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

In this embodiment, a method for forming a trench structure is disclosed, at least including: forming a pad oxide layer on the substrate; forming a first polysilicon layer on the pad oxide layer; forming an oxide layer on the first polysilicon layer On the silicon layer; forming a second polysilicon layer on the oxide layer; removing part of the second polysilicon layer, the oxide layer, the first polysilicon layer and the pad oxide layer to expose part of the substrate; and etching the second The polysilicon layer and part of the substrate form a trench structure in the substrate and expose the oxide layer. The etch depth of the trench structure is well controlled by the etched thickness of the second polysilicon layer. Next, while forming the liner layer on the sidewall of the trench structure, a sidewall oxide layer is formed on the sidewall of the first polysilicon layer, which can protect the trench structure and avoid corner depressions.

Referring to FIG. 1A , a pad oxide layer 20 is formed on a silicon substrate 10 , and a polysilicon layer 30 , an oxide layer 40 and another polysilicon layer 50 are sequentially formed thereon. A pattern-transferred photoresist layer 60 defining trench isolation is formed on the polysilicon layer 50 .

Etching the polysilicon layer 50 , the oxide layer 40 , the polysilicon layer 30 and the pad oxide layer 20 to expose part of the surface of the silicon substrate 10 ; and then removing the photoresist layer 60 , as shown in FIG. 1B .

One of the key steps of the present invention is etching the exposed surface of the silicon substrate 10 to form a trench in the silicon substrate 10; the etching of the silicon substrate 10 is controlled by the simultaneously etched polysilicon layer 50, and the etching stops at the oxide layer 40. Furthermore, simultaneous etching of the polysilicon layer 50 and the silicon substrate 10 can avoid micro-loading during trench formation. Thus, the depth of the trench is controlled by the thickness of the polysilicon layer 50, as shown in FIG. 1C.

Next, the lining layer 70 is formed by oxidation of the sidewall of the trench; while the lining layer 70 is formed, the sidewall oxide layer 90 (side-wall oxide layer) of the polysilicon layer 30 will also be formed, as shown in FIG. 1D; There is no silicon nitride thin layer, so there will be no Kooi effect during the high temperature oxidation process of the sidewall oxide layer 90 .

Then silicon oxide is deposited by high-density plasma chemical vapor phase, followed by chemical mechanical polishing to form the groove structure 80 . Afterwards, the oxide layer 40 and the polysilicon layer 30 are removed by appropriate methods, as shown in FIG. 1E .

After that, the pad oxide layer 20 is removed; one of the key steps of the present invention, when the pad oxide layer 20 is removed, the sidewall oxide layer 90 can protect the trench structure 80 to avoid corner recesses, as shown in FIG. 1F .

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed in the present invention should be included in the following within the scope of the claims.

Claims (9)

1. the formation method of a groove structure, this method comprises at least:

Form pad oxide on ground;

Form first polysilicon layer on this pad oxide;

Form oxide layer on this first polysilicon layer;

Form second polysilicon layer on this oxide layer;

Remove this second polysilicon layer of part, this oxide layer, this first polysilicon layer and this pad oxide to expose this ground of part; And

This second polysilicon layer of etching and this ground of part to be forming this groove structure in this ground, and expose this oxide layer.

2. method as claimed in claim 1 is characterized in that, also comprises forming backing layer on the first side wall of this groove structure.

3. method as claimed in claim 2 is characterized in that, also comprises forming sidewall oxide on second sidewall of this first polysilicon layer.

4. method as claimed in claim 1 also comprises:

Dielectric layer and is inserted in this groove structure on this oxide layer;

This dielectric layer of planarization and this oxide layer; And

Remove this first polysilicon layer and this pad oxide.

5. method as claimed in claim 4 is characterized in that, above-mentioned deposition step forms with the high density plasma CVD method.

6. the formation method of a groove structure, this method comprises at least:

Form pad oxide on ground;

Form first polysilicon layer on this pad oxide;

Form oxide layer on this first polysilicon layer;

Form second polysilicon layer on this oxide layer;

Remove this second polysilicon layer of part, this oxide layer, this first polysilicon layer and this pad oxide to expose this ground of part;

This second polysilicon layer of etching and this ground of part to be forming groove structure in this ground, and expose this oxide layer; And

Form simultaneously backing layer on the sidewall of this groove structure with sidewall oxide on the sidewall of this first polysilicon, this sidewall oxide is in order to protecting this groove structure, to avoid the corner depression.

7. method as claimed in claim 6 is characterized in that, also comprises:

Insert dielectric layer in this groove structure with this oxide layer on; And

This dielectric layer of planarization and this oxide layer.

8. method as claimed in claim 7 is characterized in that above-mentioned dielectric layer comprises silicon oxide layer at least.

9. method as claimed in claim 7 is characterized in that above-mentioned dielectric layer comprises polysilicon layer at least.

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