CN1253893C - Method of guiding ROM to realize write protection - Google Patents

Abstract

The invention relates to a write protection logic realization method of a read-only memory for guidance, and belongs to the application technical field of semiconductor memory chips. This method first sets the write-protection data register and the write-protection status register, each of which is set to an initial value when resetting, and the write-protection status register is in the state of "write-protection enable", continuously writes data to the data register, and the write-protection status register is In the "write protection prohibited" state, the chip select signal of the boot ROM is decoded, so that the chip select signal of the boot ROM is valid. At this time, the write operation is performed on the boot ROM. After the write operation is completed, Write a data to the write protection data register, so that the write protection status register is in the state of "write protection enable" again. The method of the present invention can realize the write protection function of the read-only memory for guidance by changing the logic, and reduce the probability of the read-only memory for guidance being erased or rewritten.

Description

A method for implementing write protection of a bootable read-only memory

technical field

The invention relates to a write protection logic realization method of a read-only memory for guidance, and belongs to the application technical field of semiconductor memory chips.

Background technique

In some electronic devices, a single-board boot read-only memory that plays a booting role is usually installed on the single board. Because there are unavoidable inconsistencies in the design of the board boot program, and there may be new requirements at any time, the boot ROM of the board generally supports the online upgrade function. At this time, the boot ROM must be in a specific Time to allow the new bootloader to be written. However, during the operation of the board, the program may run away. If the program runs away to the corresponding boot ROM erase function, or when the write operation after the program runs away coincides with the timing of the boot ROM write operation, the boot ROM will be erased or Overwrite, thereby damaging the boot program of the board, and thus causing the board to fail to start normally. The basic method to solve the rewriting of the boot ROM is to write-protect the boot ROM chip. When the boot ROM needs to be written, the protection function is disabled, and the write protection function is activated after the write operation is completed.

In the existing methods for writing protection of the boot read-only memory, most of them are realized by hardware. Different boot read-only memory chips have different methods for implementing data protection. Some ROM chips for booting have their own programming voltage pin VPP. When programming this type of device, a specific programming voltage is required to be provided on the VPP pin, which is different from the normal working voltage of the chip. The programming voltage of the boot read-only memory is generally provided by the programmer when loading, but this programming voltage is not provided on the single board, so that when the single board is working normally, the boot read-only memory device can be guaranteed on the hardware will not be written. On the VPP side of some chips, when the input voltage is greater than a certain threshold, the device is allowed to be written, and if it is lower than a certain threshold, the device will be prohibited from being written. Using this feature, the VPP signal can be individually controlled on the board and only set above a voltage threshold when programming the boot ROM chip, which is typically provided in the device manual.

In addition, data protection can also be implemented through some control lines of the device. The write protection implemented by the control pin is actually to prevent software from accidentally writing to the ROM chip for booting. The write-related control pins of the boot read-only memory chip include WP# (write protection) and WE# (write enable). Some devices also provide RP# (reset or power-down) pins. Different chips may provide control The pins are not exactly the same. For example, the SST39VF040 chip has a small capacity and is generally used as a read-only memory for single-board booting. The chip only provides WE# without WP# and RP# pins. If the device has an RP# pin, it is necessary to confirm that the RP# pin of the boot ROM chip is set from low level to high level before the CPU reset is completed. If the boot ROM chip supports data protection through RP#, it is recommended to set WP# to the writable state of the boot ROM, and realize the data protection of the boot ROM by controlling RP#; If there is only WP# control line in the read-only memory, you can control WP# to realize data protection; if there is no control line similar to WP#, and there is no control line similar to RP#, you can also realize data protection by controlling the WE# signal line . Usually it is not necessary to implement multiple protection methods for the same chip. If you want to realize data protection by controlling the WE# signal line, generally pull WE# to a high level in the design, but in this case, the boot ROM cannot support the online upgrade function. In addition, some larger-capacity flash memory (Flash) has a sector protection function, which is also a software protection method.

The write protection method of the above-mentioned boot ROM mainly adopts pins such as VPP, WP#, and RP# of the chip itself. The prerequisite for using these pins to implement write protection must be that the chip itself provides these pins. However, the commonly used ROM chip for booting does not necessarily provide these pins. In addition, if WE# is pulled to a fixed high level, the boot ROM cannot support the online upgrade function.

If WE# is not pulled to a fixed high level, and WE# is used to realize the write protection of the boot ROM, the WE# pin of the boot ROM chip must be drawn from the logic, but the WE# signal It is not a pin that must be brought out from the logic. In comparison, the chip select signal CE# of the boot ROM chip is generally obtained through logic decoding. In particular, some single boards are not designed to support the write protection function, but their CE# is drawn out through the logic device.

Contents of the invention

The present invention aims at the shortcomings of the limited protection function and inflexible application of the existing write protection method of the read-only memory for guidance, and proposes a write protection logic implementation method for the read-only memory for guidance, so as to strengthen the write protection of the read-only memory for guidance. Protection function to reduce the probability of it being erased or rewritten.

The method for implementing the write protection logic of the read-only memory for guidance provided by the present invention comprises the following steps:

(1) Write-protection data register and write-protection status register are set, and address is allocated for above-mentioned two registers respectively;

The write protection state register includes a "write protection enabled" state and a "write protection prohibited" state;

(2) An initial value is respectively set for the above two registers, and the read-only memory for guiding is set to the "write protection enabling" state;

(3) Write data to the write-protected data register continuously. Every time a data is written, the value of the write-protected status register changes once until the value is a specific value. At this time, the boot read-only memory is set to "write-protected Forbidden" status;

(4) Decoding the chip select signal of the ROM for guidance, so that the chip select signal of the ROM for guidance is valid, and at this time, the write operation is performed for the ROM for guidance;

(5) After the write operation is finished, write data into the write protection data register, so that the boot read-only memory is in the "write protection enable" state again.

In the above step (4), the highest bit of the write protection status register and other control signals of the chip are used to decode the chip select signal of the boot ROM.

The write protection state register in the above-mentioned method also comprises " intermediate state " state, wherein said (3) step, its process is as follows:

(1) At the beginning, the write protection status register is in the state of "write protection enable";

(2) In the "write protection enable" state, write the first setting data to the write protection data register, so that the write protection state register enters the "intermediate state" state, if it is other operations, return to the "write protection enable" can" state;

(3) In the "intermediate state", if the first set data is written to the write-protected data register, the write-protected state register maintains the current state, and if the second set data is written to the write-protected data register, the write The protection status register enters the "write protection disabled" state, and returns to the "write protection enabled" state for other operations.

The write protection logic implementation method of the boot ROM proposed by the present invention, for a single board that does not implement the write protection function of the boot ROM at the initial stage of design, it does not need to consider whether the chip provides hardware pins related to write protection. As long as the CE# signal of the boot ROM chip is decoded by logic, the write protection function of the boot ROM can be realized by changing the logic. If the write protection method is used together with other write protection methods, the write protection function of the boot ROM can be greatly enhanced, and the probability of the boot ROM being erased or rewritten can be reduced. The method of the present invention can be applied to all flash memory chips (Flash) including the boot read-only memory, and realizes the write protection function for the boot read-only memory chip.

Description of drawings

FIG. 1 is a flowchart of an embodiment of the present invention implementing write protection logic.

Detailed ways

The method for implementing the write protection logic of the boot ROM proposed by the present invention will be described in detail below in conjunction with the accompanying drawings.

(1) Setting register

Set up an 8-bit write protection data register and a 3-bit write protection status register in the logic. Assign the two registers their respective addresses. After having the address, by establishing the write process in the logic, the register pair can be read or written.

The above-mentioned write protection state register is used to indicate the write protection state of the boot ROM, and it has three states in total: "write protection enabled", "intermediate state", and "write protection disabled". The "intermediate state" is the intermediate state that the write protection logic must pass through from the "write protection enable" state to the "write protection prohibition" state. In this state, it is still impossible to write data to the boot read-only memory. .

The write-protected data register is used to write data into it. When certain data is written into the write-protected data register, the state of the write-protected status register will change accordingly.

The number of bits of the above-mentioned write protection status register can be changed, and can be designed as 2 bits or others according to needs. The number of data continuously written into the write protection data register can be flexibly designed. If the number of data is increased, the intermediate state will be correspondingly increased to enhance the write protection function. The value written continuously to the write-protected data register can also be flexibly designed.

(2) Set the initial value for the two registers

When the board is powered on or reset, the write protection logic enters the "write protection enable" state, at this time, the write protection data register is set to all "1", and the write protection status register is also set to all "1";

(3) Write protection prohibited

If you want to implement the write operation to the boot read-only memory, you must first make the write protection logic in the "write protection disabled" state. At this time, the write protection logic needs to go through three states: "write protection enabled", "intermediate state", and "write protection disabled".

An embodiment of the present invention takes two "intermediate states" as examples, as shown in Figure 1, at this time, the write protection logic needs to go through "write protection enabling", "the first intermediate state", and "the second intermediate state" , "write protection prohibited" four states. If you want to realize the function of prohibiting write protection, write 3 data to the data register continuously: 0xAA, 0x99, 0x66 (3 write operations must be continuous). Every time a data is written, the value of the write protection status register changes once until its value is "011". When the value of the write protection status register is "011", the boot read-only memory is in the "write protection prohibited" state.

As shown in Figure 1, the conversion relationship between the four states of the write protection status register is as follows:

When the board is powered on or reset, the write protection status register is in the "write protection enabled" state;

In the "write protection enable" state, if the first setting data (such as 0xAA) is written to the write protection data register, the write protection state register will enter the "first intermediate state" state, and if it is other operations, it will remain current status;

In the "first intermediate state" state, if the first setting data (such as 0xAA) is written to the write protection data register, the write protection status register maintains the current state, and if the second setting data is written to the write protection data register data (such as 0x99), the write protection status register enters the "second intermediate state" state, and if it is other operations, it returns to the "write protection enable" state;

In the "second intermediate state" state, if the third setting data (such as 0x66) is written to the write protection data register, the write protection state register enters the "write protection prohibited" state, and if it is other operations, it returns to the " Write Protect Enable";

In the "write protection disabled" state, if the fourth setting data (such as 0x55) is written to the write protection data register, the write protection status register returns to the "write protection enable" state, and if it is other operations, it can be Write operations to boot ROM and any other operations.

In the state of "write protection prohibited", the write operation and any other operation to the boot read-only memory can be carried out. If the fourth setting data (0x55) is written to the write protection data register, the write protection status register returns to " Write protection enabled" state,.

The corresponding relationship between the four states of the write protection status register and the register value of the write protection status register is as follows:

"Write protection enable" status -- the value of the write protection status register is "111";

"The first intermediate state" state--the value of the write protection state register is "110";

"The second intermediate state" state--the value of the write protection state register is "101";

"Write protection disabled" status - the value of the write protection status register is "011".

(4) Implement a write operation to the boot ROM

When the write-protected state memory is in the state of "write-protection prohibited", write operations such as online upgrade can be performed on the boot read-only memory. When implementing the write operation to the boot read-only memory, the chip select signal of the boot read-only memory should be decoded from the second bit data of the write protection status register and other control signals. The state of the CE# signal is not only obtained by decoding the general control signals (including the CPU's read signal, write signal, high address signal, chip select signal, etc.), but also controlled by the second bit of the write protection status register. In addition, when performing a read operation, the CE# signal should not be controlled by the second bit of the write protection status register.

(5) After the write operation is finished, reset the write protection state register to the write protection state. Write the fourth data 0x55 into the write protection data register, then the boot read-only memory is in the write protection state again.

Claims (3)

1, a kind of write-protection logic implementation method with read-only memory for guiding, it is characterized in that the method comprises the following steps: (1) Write-protected data register and write-protected status register are set, and addresses are assigned to the two registers respectively; The write protection state register includes a "write protection enabled" state and a "write protection prohibited" state; (2) An initial value is respectively set for the above two registers, and the read-only memory for guiding is set to the "write protection enabling" state; (3) Continuously write data to the write protection data register. Every time a data is written, the value of the write protection status register changes once until the value is a set value. At this time, the boot read-only memory is set to "write protection prohibited" status; (4) Decoding the chip select signal of the ROM for guidance, so that the chip select signal of the ROM for guidance is valid, and at this time, the write operation is performed for the ROM for guidance; (5) After the write operation is finished, write data into the write protection data register, so that the boot read-only memory is in the "write protection enable" state again. 2. The method according to claim 1, wherein the (4) step is used to decode the chip select signal of the ROM for guidance and is the highest bit of the write protection status register and other control signals of the chip . 3. The method according to claim 1, wherein the write protection state register also includes an "intermediate state" state, wherein said (3) step, its process is as follows: (1) At the beginning, the write protection status register is in the state of "write protection enable"; (2) In the "write protection enable" state, write the first setting data to the write protection data register, so that the write protection state register enters the "intermediate state" state, if it is other operations, return to the "write protection enable" can" state; (3) In the "intermediate state", if the first set data is written to the write-protected data register, the write-protected state register will maintain the current state; if the second set data is written to the write-protected data register, the write The protection status register enters the "write protection disabled" state, and returns to the "write protection enabled" state for other operations.