CN1252583C - Display control circuit and method correcting drivce voltage based on the input impedance of screen - Google Patents

Abstract

The present invention relates to a display control circuit which comprises a conversion circuit, wherein the conversion circuit is used for converting display data into display driving voltage. The conversion circuit comprises a current mirror circuit and a voltage calibration circuit, wherein the current mirror circuit is used for converting the display data into output current having a current ratio with reference current according to the reference current; the output current is transmitted to a screen to generate the corresponding display driving voltage; the voltage calibration circuit is used for calibrating the current ratio according to the display driving voltage and scheduled display driving voltage so as to adjust the output current, and thereby, the display driving voltage approaches to the scheduled display driving voltage.

Description

Proofread and correct the display control circuit and the method for driving voltage according to the input impedance of screen

Technical field

The present invention relates to a kind of display control circuit, particularly relate to a kind of display control circuit that can proofread and correct display driver voltage according to the input impedance of screen.

Background technology

See also Fig. 1, Fig. 1 is the function block schematic diagram of known computer systems 10.It includes a central processing unit (CPU) 12, one north bridge circuits 14, one system storages 16, one display control circuits 18, and a screen 20.Central processing unit 12 is used for the running of control computer system 10, the signal that north bridge circuit 14 is used between coherent system storer 16, display control circuit 18 and the central processing unit 12 transmits, system storage 16 is used for storing the operational data of central processing unit 12, and display control circuit 18 then is used for the output image signal to drive screen 20 display frames.Display control circuit 18 includes a display chip 22, one display-memories 24, and a D/A conversion circuit 26, in addition, comprises also in the display-memory 24 that an operational data is deposited block 28 and a view data is deposited block 30.Display chip 22 can be carried out 2D and 3D graphic operation, and be stored in data and deposit block 28, and the video data (the GTG value of respective pixel (gray level)) of each pixel (pixel) on the corresponding screen 20 is recorded in view data deposits block 30, then, D/A conversion circuit 26 is just deposited view data that video datas (digital signal) are converted to corresponding display driver voltage (analog signal) in the block 30, and exports screen 20 to and show.

With cathode-ray tube (CRT) (cathode ray tube, CRT) screen, the manufacturing of display control circuit 18, be according to 75 ohm of the standard input impedance of screen, set the transformational relation between video data (digital signal) and the display driver voltage (analog signal), therefore when same display control circuit 18 is used for driving different screens 20, because the input impedance that different screens 20 may have is (75 ± Δ R) ohm, therefore cause same video data on different screen 20, to export the image frame of different brightness, therefore cause display quality not good.

Summary of the invention

Therefore fundamental purpose of the present invention is to provide a kind of display control circuit that can proofread and correct display driver voltage according to the input impedance of screen, makes the shown image frame of screen have consistent display quality.

To achieve these goals, the invention provides a kind of display control circuit, be useful on the screen, comprise: a display chip, transmit a video data; Display-memory is stored required operational data and view data; An and change-over circuit, this video data is converted to a display driver voltage, this change-over circuit includes: a current mirroring circuit, according to a reference current and this video data, produce an output current that has a current ratio with this reference current, this output current is sent to this screen, produces should display driver voltage; And a voltage correction circuit, according to this display driver voltage and a predetermined display driver voltage, revise this current ratio, to adjust this output current, make this display driver voltage convergence should predetermined display driver voltage.

The present invention also provides a kind of correction one display driver voltage method, and it includes: according to a reference current, make a video data convert an output current that has a current ratio with this reference current to, this output current also produces should display driver voltage; And after relatively this display driver voltage and one is scheduled to display driver voltage, revise this current ratio, to adjust this output current, make this display driver voltage convergence should be scheduled to display driver voltage.

Description of drawings

Fig. 1 is the function block schematic diagram of known computer systems;

Fig. 2 is the function block schematic diagram of computer system of the present invention;

Fig. 3 is the circuit diagram of D/A conversion circuit shown in Figure 2;

Fig. 4 is the circuit diagram of current ratio control circuit shown in Figure 3; With

Fig. 5 is the running synoptic diagram of state machine shown in Figure 3.

The drawing reference numeral explanation

10,50 computer systems, 12,52 central processing units

14,54 north bridge circuits, 16,56 system storages

18,58 display control circuits, 20,60 screens

22,62 display chips, 24,64 display-memories

26,66 D/A conversion circuits, 28,70 operational datas are deposited block

30,72 view data are deposited block 68 voltage correction circuits

74,90 operational amplifiers, 75,86 resistance

76 current ratio control circuits, 78 state machines

82,83a, transistor 88a, 88b, 88c current ratio setup unit

83b、83c、84、

85、90a、90b、

91a、91b、92a、

92b、93a、93b、

93c

Embodiment

See also Fig. 2, Fig. 2 is the function block schematic diagram of computer system 50 of the present invention.Itself and Fig. 1 something in common are in this no longer repeat specification, and wherein the difference with Fig. 1 maximum is to be provided with in the D/A conversion circuit 66 voltage correction circuit (voltage calibration circuit) 68.And voltage correction circuit 68 is to proofread and correct this display driver voltage according to the input impedance of screen 60, and the display driver voltage behind the output calibration is to screen 60, to drive the picture of the pixel output on the screen 60.

See also Fig. 3, Fig. 3 is the circuit diagram of D/A conversion circuit 66 shown in Figure 2.D/A conversion circuit 66 is to use current mirror (current mirror) framework to produce output current Iout.Operational amplifier (operational amplifier, OP) 74 be used as an impact damper (buffer), the voltage level of terminal A is a reference voltage Vref, flow through the reference current Iref of resistance 75 for (Vref/R1), because reference voltage Vref and resistance value R1 are definite value, so reference current Iref can be considered a current source.When current ratio control circuit 76 does not start, terminal A can be considered and is directly connected in terminal B.Form the framework of a current mirror between transistor 82 and the transistor 83a, i.e. a corresponding proportionate relationship between the electric current that conducted of two current paths that constitute of transistor 82,83a; Similarly, transistor 82 forms a current mirror framework with transistor 83b, and transistor 82 forms a current mirror framework with transistor 83c, in fact can have n transistor AND gate transistor 82 to produce a plurality of mirror electric current I in the current mirror mode _N-1, I _N-2, I ₀The channel width/length of supposing transistor 83a is 2 of the channel width/length ratio of transistor 82 than (W/L ratio) ^N-1* L times, the mirror electric current I _N-1Promptly equal 2 ^N-1* L*Iref, the channel width/length of transistor 83b is than being 2 of the channel width/length ratio of transistor 82 ^N-2* L times, the mirror electric current I _N-2Promptly equal 2 ^N-2* L*Iref, the channel width/length of transistor 83c is than 2 of the channel width/length ratio that is transistor 82 ⁰* L times, the mirror electric current I ₀Promptly equal 2 ⁰* L*Iref.

In addition, switch element SW _N-1, SW _N-2..., SW ₀Be used for controlling the size of output current Iout, with switch element SW _N-1Be example, its grid (gate) that includes two transistor 84,85 is connected to anti-phase each other voltage level, as switch element SW _N-1Transistor 85 conductings the time, the mirror electric current I _N-1Just can transfer to the output terminal (that is end points C) of D/A conversion circuit 66.The bit length of video data is n, and by data bit D _N-1, D _N-2..., D ₀Constitute data bit D wherein _N-1, D _N-2..., D ₀In order to control mirror electric current I _N-1, I _N-2, I ₀Whether may be output to end points C (output terminal), so output current Iout represents with following equation (1): Iout=I _N-1+ I _N-2+ ... + I ₀=2 ^N-1* L*Iref*D _N-1+ 2 ^N-2* L*Iref*D _N-2+ ... + 2 ⁰* L*Iref*D ₀

Equation (1)

If video data represents 256 kinds of different GTG values 0～255 with 8, " 0000000 " corresponding GTG value 0 wherein, and " 11111111 " corresponding GTG value 255, when corresponding GTG value 255, data bit D _N-1, D _N-2..., D ₀Equal counterlogic value " 1 ", each switch element SW _N-1, SW _N-2..., SW ₀All can transmit the mirror electric current I _N-1, I _N-2..., I ₀To end points C, that is output current Iout is all mirror electric current I _N-1, I _N-2..., I ₀Summation, so Iout=(2 ⁷+ 2 ⁶+ 2 ⁵+ 2 ⁴+ 2 ³+ 2 ²+ 2 ¹+ 2 ⁰) * L*Iref=255*L*Iref.When GTG value 0, data bit D _N-1, D _N-2..., D ₀Equal counterlogic value " 0 ", each switch element SW _N-1, SW _N-2..., SW ₀All with the mirror electric current I _N-1, I _N-2..., I ₀Import earth terminal Gnd, can not transmit the mirror electric current I _N-1, I _N-2..., I ₀To end points C, so the current value of output current Iout is 0, and according to equation (1) Iout=0*Iref=0 as can be known.As shown in Figure 3, end points C is connected to earth terminal Gnd via resistance 86, therefore resistance 86 is the equivalent input impedance of screen 60, the voltage level of end points C is the D/A conversion circuit 66 conversion display driver voltages that video data produced, so if the resistance value of resistance 86 is R2, then this display driver voltage is the product of output current Iout and resistance value R2.

See also Fig. 4, Fig. 4 is the circuit diagram of the current ratio control circuit 76 of Fig. 3.It includes a plurality of current ratio setup unit 88a, 88b, 88c (only showing three at this).After current ratio control circuit 76 starts, current ratio setup unit 88a, 88b, 88c cross the electric current I ref ' of transistor 82 with the adjusting actual flow as divided circuit, because reference current Iref can be considered a current source, so when many more divided circuits started, the current value of electric current I ref ' was relatively more little.With current ratio setup unit 88a is example, and it includes transistor 90a, 91a, 92a, 93a, and wherein transistor 90a, 91a are respectively a PMOS transistor and a nmos pass transistor, if control bit C ₀Logical value " 1 ", the transistor switch that transistor 90a, 91a are constituted can be opened, and the grid of transistor 82,93a is connected, and transistor 92a is a nonconducting state.The suitable setting of reference voltage Vref can make transistor 82 enter state of saturation (saturation), and the drain electrode of transistor 93a, source electrode and grid are electrically connected on drain electrode, source electrode and the grid of transistor 82 respectively, so transistor 93a also similarly enters state of saturation, if the channel width/length of transistor 93a ratio is K times of the channel width/length ratio of transistor 82, the reference current Iref ' of the transistor 82 of then flowing through is [1/ (1+K)] * Iref; On the contrary, if control bit C ₀Logical value " 0 ", the transistor switch that transistor 90a, 91a are constituted can't be unlocked, and transistor 92a conducting simultaneously causes the grid convergence high-voltage level Vdd of transistor 93a, transistor 93a can't conducting, so reference current Iref ' promptly can equal reference current Iref.

In like manner, for current ratio setup unit 88b, if control bit C ₁Counterlogic value " 1 ", and the channel width/length of transistor 93b is than the 2*K of the channel width/length ratio that is set at transistor 82 doubly, and the reference current Iref ' of the transistor 82 of flowing through is [1/ (1+2*K)] * Iref; On the contrary, if control bit C ₁Logical value " 0 ", reference current Iref ' can equal reference current Iref.Therefore, if current ratio control circuit 76 comprises m current ratio setup unit, and control bit C ₀, C ₁..., C _M-1Be used for controlling whether adjust reference current Iref ', and the channel width/length of transistor (for example transistor 93a, 93b) is K*2 than the channel width/length proportionate relationship with transistor 82 in regular turn ^T(0≤T≤m-1), that is transistor 93a (corresponding control bit C ₀) channel width/length than K*2 for the channel width/length ratio of transistor 82 ⁰Doubly, transistor 93b (corresponding control bit C ₁) channel width/length than K*2 for the channel width/length ratio of transistor 82 ¹Times, and transistor 93c (corresponding control bit C _M-1) channel width/length than K*2 for the channel width/length ratio of transistor 82 ^(m-1)Times, the known principle of superposition of foundation (superposition principle) reference current Iref ' as can be known is expressed as follows.

${\mathrm{Iref}}^{\text{'}}=\frac{\mathrm{Iref}}{1+K*{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="C0315520000171.png"\; state="\{\{state\}\}">C</figure-callout>}}_0{+2}^{1*}K*{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="C0315520000161.png,C0315520000171.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^{(m-1)}*K*C_{(m-1)}}$ Equation (2)

Under the running of considering voltage correction circuit 68, behind the reference current Iref in electric current I ref ' the substitution equation (1) of equation (2), the output current Iout in the time of can learning D/A conversion circuit 66 practical operations of the present invention is expressed as:

$\mathrm{Iout}=(2^{n-1*}L*D_{n-1}+2^{n-2}*L*D_{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^0*L*D_0)*$

$\frac{1}{1+K*{\mathrm{<figure-callout\; id="0"\; label="C"\; filenames="C0315520000171.png"\; state="\{\{state\}\}">C</figure-callout>}}_0+2^1*K*C_1+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^{(m-1)}*K*C_{(m-1)}}*\mathrm{Iref}$ Equation (3)

When D/A conversion circuit 66 reads identical data bit D _N-1, D _N-2..., D ₀Drive different input resistance R _In(A), R _InDuring (B) screen 60, via control bit C ₀, C ₁..., C _M-1Suitable setting can produce different output current Iout (A) and Iout (B) so that input impedance R _In(A) product with output current Iout (A) equals input impedance R _In(B) with the product of output current Iout (B), when promptly same video data drove different screens 60, D/A conversion circuit 66 can the identical display driver voltage of output.

See also Fig. 5, Fig. 5 is the running figure of state machine 78 shown in Figure 3.One setting value SET is to current ratio control circuit 76 in state machine 78 outputs, and setting value SET bit length is m, promptly by control bit C ₀, C ₁..., C _M-1Constitute.The corresponding three kinds of states 95,96,97 of the running of state machine 78, the transformation between each state 95,96,97 is then relevant with the comparative result Comp that operational amplifier 76 is exported.Operational amplifier 80 is the display driver voltage and a comparative voltage Vcomp of end points C output relatively, if display driver voltage is higher than Vcomp, then comparative result Comp is a high-voltage level; On the contrary, if display driver voltage is lower than Vcomp, then comparative result Comp is a low voltage level.In the present embodiment, comparative voltage Vcomp is input impedance pairing display driver voltage when being the screen of 75 ohm of standard values, simultaneously in the process of proofreading and correct, D/A conversion circuit 66 can produce display driver voltage Vtest output according to a test video data constantly, and wherein display driver voltage Vtest equals the product of the resistance value R2 of output current Iout and resistance 86.If the display driver voltage Vtest of end points C output is during greater than comparative voltage Vcomp, the input impedance (that is resistance value R2 of resistance 86) of then representing screen 60 is greater than 75 ohm of ideal values, so voltage correction circuit 68 must reduce output current Iout to downgrade display driver voltage Vtest; On the contrary, if the display driver voltage Vtest of end points C output is during less than comparative voltage Vcomp, the input impedance (that is resistance value R2 of resistance 86) of then representing screen 60 is less than 75 ohm of ideal values, so voltage correction circuit 68 must increase output current Iout to increase display driver voltage Vtest.

When above-mentioned correct operation starts, enable signal EN starting state machine 78, simultaneously initial each control bit C ₀, C ₁..., C _M-1Logical value.In the present embodiment, the most significant bit of setting value SET (control bit C _M-1) can be set with logical value " 1 ", and all the other control bit C ₀, C ₁..., C _M-2All set with logical value " 0 ", the initial value of setting value SET is between its maximal value (each control bit C ₀, C ₁..., C _M-1Logical value be " 1 ") with its minimum value (each control bit C ₀, C ₁..., C _M-1Logical value be " 0 ") between, setting value SET increases progressively or successively decreases so that reach the purpose that increases and downgrade display driver voltage Vtest so can be risen towards this maximal value by this initial value towards this minimum value, in addition, the initial value of output current Iout is as follows at this moment as can be known according to equation (3):

$\mathrm{Iout}=(2^{n-1}+2^{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^0)*L*\frac{1}{1+2^{(m-1)*K}}*\mathrm{Iref}$

If the resistance value R2 of resistance 86 is less than 75 ohm of ideal values, the initial value of the output current Iout resistance 86 of flowing through causes the display driver voltage Vtest of end points C less than comparative voltage Vcomp, comparative result Comp is output as logical value " 0 ", state machine 78 gets the hang of 95, setting value SET can successively decrease 1, makes control bit C _M-1Be logical value " 0 " all the other control bit C ₀, C ₁..., C _M-2Logical value " 1 ", according to equation (3) as can be known output current Iout can increase.The current value of output current Iout is as follows.

$\mathrm{Iout}=(2^{n-1}+2^{n-2}+{\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2}^0)*L*\frac{1}{1+K+2^1*K+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^{(m-2)}*K}*\mathrm{Iref}$

$=(2^{n-1}+2^{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^0)*L*\frac{1}{1+(2^{(m-1)}-1)*K}*\mathrm{Iref}$

$>(2^{n-1}+2^{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^0)*L*\frac{1}{1+2^{(m-1)}*K}*\mathrm{Iref}$

Output current Iout increases, cause display driver voltage Vtest to rise, if display driver voltage Vtest is still less than comparative voltage Vcomp, then setting value SET can successively decrease 1 again to promote the output current Iout that end points C is exported, aforesaid operations can constantly repeat, surpass comparative voltage Vcomp up to display driver voltage Vtest, comparative result Comp transfers logical value " 1 " to, state machine 78 is converted to another state 96 by state 95, and keep (hold) setting value SET, that is state machine 78 no longer is subjected to the triggering of comparative result Comp to change setting value SET.

On the other hand, if the resistance value R2 of resistance 86 is greater than in 75 ohm of ideal values, the initial value of the output current Iout resistance 86 of flowing through causes the display driver voltage Vtest of end points C2 greater than comparative voltage Vcomp, comparative result Comp counterlogic value one state machine 78 gets the hang of 97, setting value SET can increase progressively 1, makes control bit C _M-1Logical value " 1 ", control bit C ₀Also can logical value " 1 ", and all the other control bit C ₁..., C _M-2Logical value " 0 " still, according to equation (3) as can be known output current Iout can reduce.The current value of output current Iout is as follows.

$\mathrm{Iout}=(2^{n-1}+2^{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^0)*L*\frac{1}{1+K+2^{(m-1)}*K}*\mathrm{Iref}$

$=(2^{n-1}+2^{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^0)*L*\frac{1}{1+(1+2^{(m-1)})*K}*\mathrm{Iref}$

$<(2^{n-1}+2^{n-2}+\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;+2^0)*L*\frac{1}{1+2^{(m-1)}*K}*\mathrm{Iref}$

Output current Iout reduction causes display driver voltage Vtest to descend, if display driver voltage Vtest is still greater than comparative voltage Vcomp, then setting value SET can increase progressively 1 again to reduce the output current Iout that end points C is exported, aforesaid operations can constantly repeat, up to showing that comparative voltage Vcomp surpasses driving voltage Vtest, be that comparative result Comp transfers logical value " 0 " to, state machine 78 is converted to another state 96 by state 97, and keep (hold) setting value SET, that is state machine 78 no longer is subjected to the triggering of comparative result Comp to change setting value SET.Generally speaking, state machine 78 is to be made of a plurality of triggers (flip-flop), so get the hang of 96 the time when state machine 78, can stop to trigger trigger and reaches the order ground of lasting setting value SET.When D/A conversion circuit 66 carried out digital displaying data and simulates the conversion operations of display driver voltage, setting value SET meeting Control current was adjusted the display driver voltage of different GTG values than rate control circuit 76.In the present embodiment, current ratio setup unit 88a, 88b, 88c have different channel width/length ratios in the current ratio control circuit 76, therefore reference current Iref ' had different correcting values, but also can use identical channel width/length ratio, make starting current ratio setup unit number into and adjust reference current Iref ', when setting value SET increased progressively, the number that increases the startup of current ratio setup unit was to reduce reference current Iref '; When setting value SET successively decreased, the number that reduces the startup of current ratio setup unit also belonged to category of the present invention to promote reference current Iref '.

Compared to known technology, the D/A conversion circuit of display control circuit of the present invention includes a voltage correction circuit, when voltage correction starts, D/A conversion circuit is tested driving voltage to drive a screen according to a test video data output one, voltage correction circuit is proofreaied and correct according to this test driving voltage and target drives voltage then, till this test driving voltage convergence target drives voltage, after voltage correction circuit of the present invention decided the gain (gain) of display driver voltage via the operation of voltage correction, D/A conversion circuit just gained according to this and proofreaies and correct display driver voltage.In other words, for the screen of different input resistance, display control circuit of the present invention all can be according to the identical display driver voltage of same video data output, so the image frame that shows of different screen is all identical and have a consistent display quality.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Claims (16)

1. a display control circuit is useful on the screen, comprises:

One display chip transmits a video data;

Display-memory is stored required operational data and view data; And

One change-over circuit is converted to a display driver voltage with this video data, and this change-over circuit includes:

One current mirroring circuit according to a reference current and this video data, produces an output current that has a current ratio with this reference current, and this output current is sent to this screen, produces should display driver voltage; And

One voltage correction circuit according to this display driver voltage and a predetermined display driver voltage, is revised this current ratio, to adjust this output current, makes this display driver voltage convergence should be scheduled to display driver voltage.

2. display control circuit as claimed in claim 1, wherein this current mirroring circuit comprises:

One first current path transmits this reference current; And

A plurality of second current paths connect this first current path, are used for transmitting the output terminal of a plurality of mirror electric currents to this change-over circuit, to form this output current.

3. display control circuit as claimed in claim 2, wherein this voltage correction circuit comprises:

One current ratio control circuit is controlled this current ratio;

One comparer, relatively this display driver voltage is scheduled to display driver voltage with this, to produce a comparative result; And

One state machine produces a setting value to this current ratio control circuit according to this comparative result, to revise this current ratio.

4. display control circuit as claimed in claim 3, if this display driver voltage is greater than this predetermined display driver voltage, the setting value of this state machine output can reduce this current ratio, if this display driver voltage is less than this predetermined display driver voltage, the setting value of this state machine output can increase this current ratio.

5. display control circuit as claimed in claim 3, this current ratio control circuit comprises a plurality of current ratio setup units, and this current ratio control circuit is adjusted this current ratio according to the current ratio setup unit that this setting value starts a corresponding predetermined number.

6. display control circuit as claimed in claim 5, wherein all corresponding same correcting value of each current ratio setup unit is adjusted this current ratio.

7. display control circuit as claimed in claim 5, wherein the corresponding a plurality of different correcting values of these a plurality of current ratio setup units are adjusted this current ratio.

8. display control circuit as claimed in claim 5, wherein each current ratio setup unit is to be connected in the current mirror mode with this first current path.

9. display control circuit as claimed in claim 3, wherein if corresponding one first logic level of this comparative result, then this state machine can enter and revise this setting value to order about one first mode of operation that this current ratio control circuit reduces this current ratio, and if corresponding one second logic level of this comparative result, then this state machine can enter this setting value of correction increases by one second mode of operation of this current ratio to order about this current ratio control circuit.

10. display control circuit as claimed in claim 9, wherein if this state machine is in this first mode of operation, and this comparative result is to should second logic level, then this state machine can enter one the 3rd mode of operation to keep this setting value by this first mode of operation, and if this state machine is in this second mode of operation, and this comparative result is to should first logic level, and then this state machine can enter the 3rd mode of operation to keep this setting value by this second mode of operation.

11. proofread and correct a display driver voltage method for one kind, it includes:

According to a reference current, make a video data convert an output current that has a current ratio with this reference current to, this output current also produces should display driver voltage; And

Relatively behind this display driver voltage and the predetermined display driver voltage, revise this current ratio,, make this display driver voltage convergence should be scheduled to display driver voltage to adjust this output current.

12. as correction one display driver voltage method as described in the claim 11, wherein this video data converts an output current that has a current ratio with this reference current to, be to utilize a current mirror mode, make and use this reference current on one first current path of this current mirror, all electric currents constitute this output current on a plurality of second current paths.

13. as correction one display driver voltage method as described in the claim 12, wherein relatively this display driver voltage and a predetermined display driver voltage also comprise the following steps:

Produce a comparative result; And

Produce a setting value to revise this current ratio according to this comparative result.

14. as correction one display driver voltage method as described in the claim 13, wherein when this display driver voltage during greater than this predetermined display driver voltage, use this setting value to reduce this current ratio, and, use this setting value to increase this current ratio when this display driver voltage during less than this predetermined display driver voltage.

15. as correction one display driver voltage method as described in the claim 13, when wherein this display driver voltage is greater than this predetermined display driver voltage, when this comparative result is one first logic level, enter one first mode of operation that reduces this current ratio, and when this display driver voltage during less than this predetermined display driver voltage, when comparative result is one second logic level, enter one second mode of operation that increases this current ratio.

16. correction one display driver voltage method as claimed in claim 15, wherein ought be in this first mode of operation, and this comparative result is when being this second logic level, then enter one the 3rd mode of operation to keep this setting value by this first mode of operation, and when being in this second mode of operation, and this comparative result enters the 3rd mode of operation to keep this setting value by this second mode of operation when being this first logic level.

Images