CN1246770C - Digital signal processor with modulus address arithmetic - Google Patents

Abstract

A digital signal processor with modulo address operation. In the address generator unit, a programmable register group consisting of 8 base address registers, index registers and mode registers is used, and an adder and an accumulator for modulus are used. A device and a result selection judgment logic module including a constant generator, a linear addition operation and a modulo operation selector, an out-of-bounds discriminator, a two-input AND gate, a three-input AND gate and two multiplexers. The present invention adopts the address generator unit with specific discrimination logic, not only can complete ordinary linear address operation and modulus operation, but also when the index offset value is a positive integer multiple of the lower limit value of modulo operation, it is not necessary to set the mode The linear address operation can be performed by changing from the modulo operation to the linear operation, and once the next index offset value is not a positive integer multiple of the lower limit value of the modulo operation, it will automatically switch to the modulo operation mode, achieving zero overhead mode switching function.

Description

Digital signal processor with modulo address operation

Technical field:

The invention relates to a digital signal processor, in particular to a digital signal processor with modulo address calculation, which innovates the generation method of the digital data memory access address in the digital signal processor (DSP), and belongs to computer digital signal Dealing with technical fields.

Background technique:

The technical background related to the present invention can refer to TMS320C600 digital signal processor reference manual (TMS32C6000 CPU and Instruction Set Reference Guide) of Texas Instruments Corporation.

With the wide application of digital signal processors and the continuous improvement of their efficiency requirements, it is becoming more and more important to complete the same numerical calculation tasks with fewer instructions. In existing digital signal processors, it has become a routine operation for the address generation unit to support multiple different addressing modes, but it is generally limited to direct linear addition operations and modulo operations. According to the routine implementation method, the direct linear addition operation is to add the contents of the base register to the contents of the index register as the calculated address; the modulo operation is to add the contents of the base register to the contents of the index register and then modulo the last k bits of the addition result according to the value in the mode register, so that the value of the last k bits is within the specified upper and lower bounds.

In the existing technology, the value in the mode register needs to be changed when the mode is changed, so frequently changing the value in the mode register in the program is a factor that leads to a decrease in efficiency.

For example, when dealing with parallel infinite impulse response filtering algorithms, it is necessary to perform the same operation in different address ranges of digital data memory, if at the same time because other parts of the overall program need to use modulo operations to calculate access numbers data storage. Then frequently changing the value in the mode register in this program is a factor that leads to a decrease in efficiency. Digital signal processors are usually designed and implemented with limited processing functions, but this function must be executed repeatedly and quickly. In order to ensure high efficiency of digital signal processors, it is usually necessary to reduce the number of instructions in the loop. Existing digital signal processors need more instructions, so the efficiency of the chip will drop.

Invention content:

The purpose of the present invention is to address the deficiencies in the prior art, to provide a digital signal processor with modulo address operations, to reduce the number of instructions required by the digital signal processor when switching between different addressing modes, thereby improving the digital signal processor operating efficiency.

In order to achieve such purpose, the present invention improves the modulus operation on the original basis, that is, when the modulus operation is performed, if the value in the index register is a positive integer multiple of the lower limit value of the modulo address range, then it is not Modulo operations are not performed but direct linear addition operations are used. This processing method can efficiently perform the same operation in different address ranges of the digital data memory. Under the condition of not needing to change the content of the mode register, the modulo operation and the linear operation of a specific value can be performed, and the operation speed is fast and the work efficiency is high. This is very useful for many digital signal processing algorithms.

The digital signal processor of the present invention is formed by connecting a digital signal processor core and a digital data memory, wherein the digital signal processor core is composed of a program control unit, an address generator unit, an instruction decoding unit and a digital data processing unit.

All connections below are one-way connections unless otherwise specified.

The instruction decoding unit is connected to the program control unit. The program control unit is connected to the address generator unit, the instruction decoding unit and the digital data processing unit. The digital data processing unit is bidirectionally connected to the digital data memory. The address generator unit is connected to the digital data memory through the address bus, while the digital data memory is connected to the address generator unit, the instruction decoding unit and the digital data processing unit through the data bus.

The instruction decoding unit translates the instruction code into the control signal representing the meaning of the instruction inside the core of the digital signal processor, and these control signals are transmitted to the program control unit, and the program control unit sends out the address generating unit, the instruction decoding unit and the digital data Control signals required for the processing unit to work. The digital data processing unit accepts the data from the digital data memory and performs operations on it. The address generator unit performs address calculation, and the result of the address calculation is sent to the digital data memory through the address bus. The digital data memory puts the corresponding digital data on the data bus according to the generated address, so as to send it to the address generator unit, instruction decoding unit and data processing unit, and provide them with instructions and operands.

The present invention adopts the address generator unit with specific discrimination logic, including programmable 8 groups of register groups composed of base address register, index register and mode register, adder, modulus accumulator and result selection judgment logic module . The set of base registers and the set of index registers are connected to the two inputs of the adder, while the set of base registers, the set of index registers and the set of mode registers are connected to the modulo accumulator. The base address register group, the index register group, the mode register group, the output of the adder and the output of the accumulator are connected to the selection result judging logic module.

The contents of the base register and the index register in the same group are transmitted to the input terminal of the adder as two input digital signals. The contents of the index register and the value in the mode register are connected to the modulo accumulator as input to obtain the second intermediate result. The input values of the result selection judgment logic module include not only the content of the base address register, the mode register, the two intermediate result values but also the content of the index register. The result selection judging logic module is used to decide whether to select the first intermediate result or the second intermediate result as the final address operation result.

Inside the result selection judgment logic module, it includes a constant generator A, a constant generator B, a linear addition operation and a modulo operation selector, an out-of-bounds discriminator, four two-input AND gates, one three-input AND gate and one two-input AND gate. multiplexer. The output bus of the mode register bank is connected to the input of the linear addition and modulo operation selector, the constant generator A and the constant generator B, and the sum bus and the constant generator A output bus are connected to the input of a two-input AND gate terminal, the base address register bus and the constant generator A output bus are connected to the input of a two-input AND gate, and the sum bus and the constant generator A output bus are connected to the input of a two-input AND gate. The outputs of the above three AND gates are connected to the out-of-bounds discriminator. The index register output bus and constant generator B are connected to the input of a two-input AND gate. The output end of the above-mentioned AND gate, the output end of the out-of-bounds discriminator, and the output end of the linear addition operation and the modulo operation selector are connected to the input end of a three-input AND gate, and the output end of the three-input AND gate is connected to the multiplexer The control signal end of the accumulative sum bus and the summative sum bus are connected to the input of the multiplexer, and the output of the multiplexer is the generated address.

The described result selection judgment logic module compares the value in the index register with the positive integer multiple of the lower limit of the address range determined by the value of the mode register, and if the result of the comparison is consistent, the result of the linear addition operation is automatically used as this The result of the secondary address operation without considering other selection factors. The program control unit directly controls the output of the base address register group, the index register group and the mode register group in the address generator unit, and the output of the result selection and judgment logic module is connected with the digital data memory.

The address generator unit of the digital signal processor involved in the present invention can not only complete the ordinary linear address operation and the modulus operation, but also when the index offset value is a positive integer multiple of the lower limit value of the modulo operation, it is not necessary to The linear address operation can be performed by changing the mode from modulo operation to linear operation. On the contrary, once the next index offset value is not a positive integer multiple of the lower limit value of modulo operation, it will automatically switch to modulo operation mode. In this way, a zero-overhead mode conversion function is achieved.

Description of drawings:

Fig. 1 is a structural block diagram of a digital signal processor of the present invention.

FIG. 1 describes the connection relationship of each component module in the digital signal processor of the present invention. As shown in Figure 1, the digital signal processor of the present invention is formed by connecting a digital signal processor core 5 and a digital data memory 6, wherein the digital signal processor core 5 is composed of a program control unit 1, an address generator unit 2, an instruction translator The code unit 3 and the digital data processing unit 4 are composed.

Fig. 2 is a structural block diagram of the address generator unit in the digital signal processor of the present invention.

As shown in Figure 2, the address generator unit 2 includes 8 groups of register groups, an adder 11, an accumulator 10 and a result selection judgment logic module 12 made up of a base address register group 7, an index register group 8 and a mode register group 9 . Each unit in the figure is connected through an index bus 13 , a mode bus 14 , an addition sum bus 15 , an accumulation sum bus 16 and a base address bus 17 .

Fig. 3 is a structural block diagram of the result selection judgment logic module in the address generator unit of the present invention.

As shown in Figure 3, the result selection judgment logic module 12 includes a constant generator A18, a constant generator B23, a linear addition operation and a modulo operation selector 26, an out-of-bounds discriminator 25, and four two-input AND gates 20, 21, 24 , 22, a three-input AND gate 27 and a two-way multiplexer 28.

Detailed ways:

The specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings.

All connections below are one-way connections unless otherwise specified.

As shown in FIG. 1 , the instruction decoding unit 3 is connected to the program control unit 1 . Program control unit 1 is connected with address generation unit 2 , instruction decoding unit 3 and digital data processing unit 4 . The digital data processing unit 4 is bidirectionally connected to a digital data memory 6 . The address generator unit 2 is connected to the digital data memory 6 through the address bus, while the digital data memory 6 is connected to the address generator unit 2, the instruction decoding unit 3 and the digital data processing unit 4 through the data bus.

The instruction decoding unit 3 translates the instruction code into the control signal representing the meaning of the instruction inside the digital signal processor core 5, and the program control unit 1 sends out the control address generating unit 2, the instruction decoding unit 3 and the digital data processing unit 4. control signal. The digital data processing unit 4 receives data from the digital data memory 6 and performs operations on it. The address generator unit 2 performs address calculation, and the result of the address calculation is sent to the digital data memory 6 through the address bus. Digital data memory 6 is connected to address generator unit 2, puts corresponding digital data on the data bus according to the address produced, and described data bus is connected to instruction decoding unit 3 and data processing unit 4, provides instruction and operand.

Referring to FIG. 2 , in the address generator unit 2 , the output signal of the base address register group 7 and the signal of the index register group 8 are connected to two input terminals of the adder 11 . The output signal of the base address register group 7, the output signal of the index register group 8 and the output signal of the mode register group 9 are connected to three input terminals of the accumulator 10, and at the same time, the above-mentioned base address registers, The index register and the mode register are respectively connected to the result selection judgment logic module 12 through the base address bus 17 , the index bus 13 and the mode bus 14 .

In the address generator unit 2, a data in the base address register group 7 and a data in the index register group 8 are sent to the two input ends of the adder 11, and the adder 11 performs a full operation on these two numbers. Add operation, and put the result on the sum bus 15. The above-mentioned data in the base address register group 7, the above-mentioned data in the index register group 8 and a data in the mode register group 9 are transmitted to three input terminals of the accumulator 10, and the accumulator 10 is based on the data in the index register group 8. Whether the numeric data in the array is a positive integer or a negative integer determines its own operation. If the digital data in the index register group 8 is a positive integer, the accumulator 10 needs to carry out the operation of changing the negative number with the absolute value unchanged to the data transmitted from the mode register group 9, and then the accumulation operation can be performed. If the digital data in the index register group 8 is a negative integer, then the data transmitted from the mode register group 9 can be directly used for accumulation operation. The accumulated result is sent to the accumulated sum bus 16 . At the same time, the base address value, index value and mode value involved in the addition and accumulation operations are sent to the result selection and judgment logic module 12 through the base address bus 17, the index bus 13 and the mode bus 14 respectively. The result selection judging logic module 12 is used to select whether to use the data on the sum bus 15 or the data on the sum bus 16 as the final address value.

With reference to Fig. 3, the output bus 14 of mode register group is connected to the input end of linear addition operation and modulus operation selector 26, constant generator A18 and constant generator B23, and the cumulative sum bus 16 and constant generator A18 output bus are connected to The input end of two-input AND gate 20, base address register bus 17 and constant generator A18 output bus are connected to the input end of two-input AND gate 21, addition and bus 15 and constant generator A18 output bus are connected to two-input AND gate 24 input terminal. The outputs of the above three AND gates are connected to the boundary-crossing discriminator 25 . The index register output bus 13 and the constant generator B23 are connected to the input terminals of the two-input AND gate 22 . The output end of the above-mentioned AND gate 22, the output end of the cross-border discriminator 25, and the output end of the linear addition operation and the modulus operation selector 26 are connected to the input end of the three-input AND gate 27, and the output end of the three-input AND gate 27 is connected To the control signal terminal of the multiplexer 28, the sum bus 16 and the sum bus 15 are connected to the input of the multiplexer, and the output of the multiplexer is the generated address.

In the result selection judgment logic module 12 , the constants of the constant generator A18 and the constant generator B23 both generate a constant according to the value in the mode bus 14 . In the constant generator A23, if the data significant figure in the mode bus 14 is k bits, the lowest k-bit signal of the constant generated by the constant generator A23 is 1, and the remaining signal bits are 0, such as the data in the mode bus 14 is 0001000101, then the constant (assumed to be 16 bits) generated by the constant generator A23 is 0000000001111111. In the constant generator A18, if the significant number of data in the mode bus 14 is k bits, the k+1th bit of the constant generated by the constant generator A18 is 1, and the remaining signal bits are 0, such as the data in the mode bus 14 is 0001000101, then the constant (assumed to be 16 bits) generated by the constant generator A18 is 0000000010000000. The constant generated by the constant generator A18 and the data on the cumulative sum bus 16 are logically ANDed to obtain the k+1th bit of the cumulative sum bus 16 . The constant generated by the constant generator A18 is logically ANDed with the data on the sum bus 15 to obtain the k+1th bit of the sum bus 15 . The constant generated by the constant generator A18 is logically ANDed with the data on the base address bus 17 to obtain the k+1th bit of the base address bus 17 .

In the cross-border discriminator 25, if the digital data in the index register group 8 is a negative integer, then the above-mentioned k+1th bit of the addition and bus 15 and the above-mentioned k+1th bit of the base address bus 17 carry out a logical XOR operation , when the result is 1, it means out of bounds; if the digital data in the index register group 8 is a positive integer, then the above-mentioned k+1th bit of the cumulative sum bus 16 and the above-mentioned k+1th bit of the base address bus 17 perform a logical XOR operation , when the result is 1, it means out of bounds. When out of bounds, the output result of the out of bounds discriminator 25 is 1.

The linear addition operation and modulo operation selector 26 determines whether to perform modulo operation according to the data on the mode bus 14. When the signal on the mode bus 14 is non-zero, the selected mode is modulo operation. Otherwise, it is a linear addition operation. Output 1 means modulo operation.

The constant generated by the constant generator B23 is logically ANDed with the data on the index bus 13 to obtain the lowest k bits of the index bus 13 . If the lowest k bits are zero, it means that the value on the index bus 13 is a positive integer multiple of the k power of 2, then the address operation enters a special mode, and the result of the modulo operation is no longer used. Special modes are indicated by output 1.

In the AND logic gate 27, if the input represents a modulo operation, has crossed the boundary and is not a special mode, then the output of the AND logic gate 27 is 1.

In the two-way multiplexer 28, when the input selection signal is 1, the data on the sum bus 16 is selected as the final address calculation result; otherwise, the data on the sum bus 15 is selected as the final address calculation result.

Claims (2)

1, a kind of digital signal processor with modulus address computing, comprise digital signal processor cores get (5) and the digital data memory (6) formed by procedure control unit (1), address generator unit (2), instruction decoding unit (3) and digital data processing unit (4), it is characterized in that procedure control unit (1) is connected with address generator unit (2), instruction decoding unit (3) and digital data processing unit (4), the two-way digital data memory (6) that is connected to of digital data processing unit (4); In the address generator unit (2), by base register group (7), modifier register group (8) and mode register set (9) are formed 8 groups of registers group, the output of base register group (7) and modifier register group (8) is connected two input ends of totalizer (11), base register group (7), the output signal of modifier register group (8) and mode register set (9) connects three input ends of totalizer (10), base register, modifier register and mode register are respectively by plot bus (17), index bus (13) is connected the result with pattern bus (14) and selects decision logic module (12), by the result select the data on decision logic module (12) selection use addition and the bus (15) or add up and bus (16) on data as last address value; The output of base register group (7), modifier register group (8) and mode register set (9) in the direct control address generator unit (2) of procedure control unit (1), the result selects the output of decision logic module (12) to link to each other with digital data memory (6).

2, as the said digital signal processor of claim 1 with modulus address computing, it is characterized in that the result selects in the decision logic module (12), pattern bus (14) is connected to linear adder computing and modulo operation selector switch (26), the input end of constant maker A (18) and constant maker B (23), add up and be connected the input end of two inputs and door (20) with bus (16) with constant maker A (18), plot bus (17) is connected the input end of two inputs and door (21) with constant maker A (18), addition and bus (15) are connected the input end of two inputs and door (24) with constant maker A (18), above-mentioned three and door (20,21,24) output is connected on the arbiter that crosses the border (25), index bus 13 is connected the input end of two inputs and door (22) with constant maker B (23), with door (22), the output terminal of arbiter (25) and linear adder computing and modulo operation selector switch (26) of crossing the border is connected the input end of three inputs and door (27), the output terminal of three inputs and door (27) is connected to the control signal end of multiplexer (28), add up and bus (16) and addition and bus (15) are connected to the input end of multiplexer (28), the address that multiplexer (28) output generates.

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