CN1240117C - Manufacturing method of thin film transistor flat panel display - Google Patents

Abstract

A manufacturing method of a thin film transistor flat panel display mainly comprises the following manufacturing processes: (1) defining the pattern of the first metal layer/the gate insulating layer/the amorphous silicon layer with a first photomask; (2) defining and forming a protective layer (passivation) and an etching stop layer (etching stopper) by using a second photomask; (3) defining and forming a Source/Drain (Source/Drain) by using a third photo mask; (4) and defining and forming a pixel electrode by using a fourth photomask. The manufacturing process of the invention only needs to apply four photomasks, thus simplifying the manufacturing process of the thin film transistor flat panel display.

Description

Manufacturing method of thin film transistor flat panel display

Technical field

The invention relates to a method for manufacturing a flat panel display, in particular to a method for manufacturing a thin film transistor liquid crystal display.

Background technique

FIG. 1A to FIG. 1D show a conventional manufacturing method of a thin film transistor used in a liquid crystal display. Referring to FIG. 1A , firstly, a gate electrode 2 is defined and formed on a transparent substrate 1 , and then an insulating layer 3 is formed to cover the gate electrode 2 . Next, an amorphous silicon (amorphous silicon) layer 40 and a silicon nitride layer 50 are sequentially formed on the insulating layer 3 . Referring to FIG. 1B , the silicon nitride layer 50 is limitedly etched to form an etching stopper layer (etching stopper) 5 . Referring to FIG. 1C , a doped silicon layer 6 (for example, an amorphous silicon layer doped with n-type impurities) is formed on the etch stop layer 5 and the amorphous silicon layer 40 . Referring to FIG. 1D , a metal layer is then formed, and then the metal layer is etched to form source/drain electrodes 7 and 8 , and finally a protective layer 9 is formed. During the etching process, part of the metal layer and the doped silicon layer 6 will be etched away, and the etch stop layer 5 is used to protect the amorphous silicon layer 40 from being damaged by etching.

Although the above-mentioned conventional methods are used to manufacture thin film transistors, there is still room for improvement in the manufacturing process of thin film transistors.

Contents of Invention

The purpose of the present invention is to provide a method for manufacturing a thin film transistor, which only requires four photomask manufacturing processes, thereby simplifying the method for manufacturing a thin film transistor.

The purpose of the present invention is achieved by providing a method for manufacturing a thin film transistor flat-panel display, comprising: (a) providing a substrate on which a first conductive layer, a first insulating layer and a first insulating layer are sequentially formed. a semiconductor layer; (b) defining the patterns of the semiconductor layer, the first insulating layer and the first conductive layer to form a scanning line, a gate pad and a gate, and the gate pad is formed at one end of the scanning line; (c) forming a protective layer covering the above-mentioned scanning lines, gate pads, gates and the substrate; (d) defining the pattern of the above-mentioned protective layer, forming a first opening and a second opening on the above-mentioned gate, And a third opening is formed on the above-mentioned gate pad, so that the above-mentioned semiconductor layer is exposed in the above-mentioned first, second and third openings; (e) sequentially forming a doped silicon layer and a second conductive layer on the above-mentioned substrate layer; (f) defining the pattern of the above-mentioned second conductive layer and the above-mentioned doped silicon layer to form a signal line, and forming a source electrode and a drain electrode above the above-mentioned gate electrode, and defining between the above-mentioned source electrode and the drain electrode is a channel, the doped silicon layer of the source and the drain is in contact with the semiconductor layer of the gate through the first and second openings respectively, and the signal line is perpendicular to the scanning line; (g) defining the gate The pattern of the semiconductor layer and the insulating layer in the electrode pad, remove the above-mentioned semiconductor layer and the insulating layer in the above-mentioned third opening, so that the above-mentioned first conductive layer is exposed in the above-mentioned third opening; (h) form a transparent electrode layer in the above-mentioned and (i) defining the transparent electrode layer to form a pixel electrode.

The present invention also provides a method for manufacturing a thin film transistor flat panel display, including: (a) providing a substrate, on which a first conductive layer, a first insulating layer and a semiconductor layer are sequentially formed; (b) defining The patterns of the above-mentioned semiconductor layer, the above-mentioned first insulating layer and the above-mentioned first conductive layer are used to form a scanning line, a gate pad and a gate, and the above-mentioned gate pad is formed at one end of the above-mentioned scanning line; (c) forming a A protective layer covering the above-mentioned scanning lines, gate pads, gates and the substrate; (d) defining the pattern of the above-mentioned protective layer, forming a first opening and a second opening on the above-mentioned gate, and forming a first opening and a second opening on the above-mentioned gate forming a third opening above the pad; (e) sequentially forming a doped silicon layer and a second conductive layer on the above-mentioned substrate; (f) defining the pattern of the second conductive layer and the above-mentioned doped silicon layer, in the above-mentioned An island structure is formed above the gate, and the above-mentioned doped silicon layer is respectively in contact with the semiconductor layer of the above-mentioned gate through the above-mentioned first and second openings; (g) defining the semiconductor layer and the first insulating layer in the above-mentioned gate pad pattern, so that the first conductive layer is exposed in the third opening; (i) forming a transparent electrode layer on the substrate, and covering the second conductive layer; and (j) defining the transparent electrode layer, the first Two conductive layers and the above-mentioned doped silicon layer form a source electrode and a drain electrode in the above-mentioned island structure, and a channel is defined between the above-mentioned source electrode and the drain electrode, and the above-mentioned channel is located above the above-mentioned gate, and the above-mentioned transparent electrode layer A pixel electrode is also formed and coupled to the drain.

The present invention also provides a method for manufacturing a thin film transistor liquid crystal display, comprising: (a) providing a substrate, on which a first conductive layer, a first insulating layer and a semiconductor layer are sequentially formed; (b) defining The patterns of the above-mentioned semiconductor layer, the above-mentioned first insulating layer and the above-mentioned first conductive layer are used to form a scanning line, a gate pad and a gate, and the above-mentioned gate pad is formed at one end of the above-mentioned scanning line; (c) forming a A protective layer covering the above-mentioned scanning lines, gate pads, gates and the substrate; (d) defining the pattern of the above-mentioned protective layer, forming a first opening and a second opening on the above-mentioned gate, and Forming a third opening on the pad; (e) forming a second conductive layer to define the pattern of the second conductive layer, forming a signal line on the protective layer, and the signal line is perpendicular to the scanning line; (f) A doped silicon layer and a transparent electrode layer are sequentially formed on the line and the above-mentioned protection layer, and the above-mentioned doped silicon layer is connected to the semiconductor layer of the above-mentioned gate through the above-mentioned first and second openings; (g) defining the above-mentioned transparent electrode Layer and the above-mentioned doped silicon layer, a source and a drain are defined above the gate, and a channel is defined between the source and the drain. The transparent electrode layer also forms a pixel electrode, and the pixel electrode and The drain is connected, and the source is electrically connected to the signal line; and (h) limiting etching of the semiconductor layer and the first insulating layer in the gate pad, so that the first conductive layer is exposed in the third opening .

The present invention also provides a method for manufacturing a thin film transistor flat panel display, including: (a) providing a substrate, on which a first conductive layer, a first insulating layer and a semiconductor layer are sequentially formed; (b) defining The pattern of the above-mentioned semiconductor layer, the above-mentioned first insulating layer and the above-mentioned first conductive layer is to form a scanning line, a gate pad and a gate, and the above-mentioned gate pad is formed at one end of the above-mentioned scanning line; (c) in the above-mentioned A protective layer and a second conductive layer are sequentially formed on the substrate, covering the gate pad and the gate; (d) defining the pattern of the second conductive layer and the protective layer, forming a signal line on the substrate, and A first opening and a second opening are formed on the gate, and a third opening is formed on the gate pad; (e) sequentially forming a doped silicon layer and a transparent electrode layer on the signal line, the gate and the above-mentioned substrate, and the above-mentioned doped silicon layer is in contact with the above-mentioned semiconductor layer through the above-mentioned first opening and the above-mentioned second opening; and (f) defining the pattern of the above-mentioned transparent electrode layer, the above-mentioned doped layer, and the above-mentioned second conductive layer, A drain and a source are formed above the gate, a channel is defined between the drain and the source so that the protective layer is exposed to the channel, the transparent electrode layer also forms a pixel electrode, and the pixel The electrode is connected to the above-mentioned drain.

Furthermore, its main features are: use the first photomask to define the pattern of the amorphous silicon layer/gate insulating layer/first metal layer; use the second photomask to form a passivation layer and island-shaped etching stop layer (etching stopper); use the third photomask to define the source/drain (Source/Drain); and then use the last photomask to define the formation of pixel electrodes.

The advantage of the method of the invention is that the manufacturing process only needs to use four photomasks, so as to simplify the manufacturing process of the thin film transistor flat panel display.

Description of drawings

1A-1D are cross-sectional views of the existing manufacturing process of thin film transistors in flat panel displays;

2A-2D are top views of the manufacturing process of the first embodiment of the present invention;

3A-3D are cross-sectional views of the manufacturing process of the first embodiment of the present invention;

4A-4D are cross-sectional views of the manufacturing process of the second embodiment of the present invention;

5A to 5D are top views of the manufacturing process of the third embodiment of the present invention;

6A-6D are cross-sectional views of the manufacturing process of the third embodiment of the present invention;

7A to 7D are top views of the manufacturing process of the fourth embodiment of the present invention;

8A-8D are cross-sectional views of the manufacturing process of the fourth embodiment of the present invention;

9A to 9C are top views of the manufacturing process of the fifth embodiment of the present invention;

10A-10C are cross-sectional views of the manufacturing process of the fifth embodiment of the present invention.

Detailed ways

Various preferred manufacturing processes will be described in detail in the following first to fifth embodiments.

Embodiment one:

2A-2D are top views of the manufacturing process of the first embodiment of the present invention. 3A-3D are cross-sectional views of the manufacturing process of the first embodiment of the present invention. In Figures 3A to 3D, Region I is the region where the thin film transistor is located, corresponding to the section along the A-A' direction in Figures 2A to 2D; Region II is the region where the gate pad (gate pad) structure is located, corresponding to Figure 2A ~A section along the B-B' direction in 2D. The manufacturing method of the present invention will be described below with reference to FIGS. 2A to 2D and FIGS. 3A to 3D .

Referring to FIG. 2A and FIG. 3A , firstly, a first conductive layer 101 , an insulating layer 102 , and a semiconductor layer 103 are sequentially formed on a transparent substrate 100 . The patterns of the semiconductor layer 103 , the insulating layer 102 and the first conductive layer 101 are further defined to form a scan line DL, a gate pad DLp and a gate DLg. The gate pad DLp is formed at one end of the scan line DL, and the gate DLg extends from one side of the scan line DL, and the semiconductor layer 103 of the gate DLg serves as a channel layer of the thin film transistor. Generally speaking, the substrate 100 can be a glass substrate or a quartz substrate, the semiconductor layer 103 can be an amorphous silicon layer, the insulating layer 102 can be a silicon oxide layer, and the first conductive layer 101 is a metal layer, forming a gate electrode.

Referring to FIG. 2B and FIG. 3B , next, a protection layer 104 is formed to cover the scan line DL, the gate DLg, the gate pad DLp and the substrate 100 . Then define the pattern of the protective layer 104, form the first opening op1 and the second opening op2 on the gate DLg, and form the third opening op3 on the gate pad DLp, so that the semiconductor layer 103 is formed by the first opening op1, the second opening op2 and the second opening op2. Three openings are exposed in op3. In this embodiment, the passivation layer 104 is made of silicon nitride (SiNx) or organic polymer material.

Referring to FIG. 2C and FIG. 3C , a doped silicon layer 105 and a second conductive layer 106 are sequentially formed on the substrate 100 . The pattern of the second conductive layer 106 and the doped silicon layer 105 is defined to form a signal line SL, and a source S and a drain D are formed on the gate DLg, and the distance between the source S and the drain D is defined as A channel 110, exposing the semiconductor layer 103 therein.

The doped silicon layer 105 of the source/drain (S, D) is in electrical contact with the semiconductor layer 103 of the gate DLg through the first and second openings (op1, op2) respectively. The signal lines SL are perpendicular to the scan lines DL.

The protective layer 104 interposed between the first opening op1 and the second opening op2 serves as an etching stop layer (etching stop; or island-shaped etching stop layer IS), which limits the etching of the second conductive layer 106 and the doped layer 105. When , it is used to protect the semiconductor layer 103 (ie, the channel layer) in the gate DLg from being damaged by etching. In this embodiment, the doped silicon layer 105 is an n-type doped silicon layer, and the second conductive layer is a metal layer.

Referring to FIG. 2D and FIG. 3D , the semiconductor layer 103 and the insulating layer 102 in the gate pad DLp are etched, so that the first conductive layer 101 of the gate pad DLp is exposed in the third opening op3. Next, a transparent electrode layer 107 is formed on the substrate 100 and covers the source S, the drain D and the gate pad DLp. Finally, define the pattern of the transparent electrode layer 107 to form a pixel electrode layer PL coupled to the drain D, and a dummy signal line layer FS covering the source S and the signal line SL, and the transparent electrode layer 107 and the gate The first conductive layer 101 in the pad DLp constitutes an electrical contact.

In this embodiment, the transparent electrode layer 107 is an ITO layer. It should be noted that the second conductive layer 106 of the source/drain electrodes (S, D) each has a sidewall in the channel 110 , and the transparent electrode layer 107 covers the sidewall of the second conductive layer 106 in the channel 110 .

Embodiment two:

The top view of the manufacturing process of the second embodiment of the present invention is the same as that indicated in FIGS. 2A-2D . 4A-4D show cross-sectional views of the manufacturing process of the second embodiment of the present invention. The biggest difference between the first embodiment and the second embodiment is that an insulating layer 202 is formed on the semiconductor layer 103 to protect the semiconductor layer 103 . In the second embodiment, the same names as those of the first embodiment use the same reference numerals.

Referring to FIG. 2A and FIG. 4A, a first conductive layer 101, a first insulating layer 102, a semiconductor layer 103 and a second insulating layer 202 are sequentially formed on the substrate 100, and their patterns are defined to form a scanning line. DL, a gate pad DLp and a gate DLg. In this embodiment, the second insulating layer 202 may be a silicon nitride layer.

Referring to FIG. 2B and FIG. 4B , a protection layer 104 is formed to cover the scan line DL, the gate DLg, the gate pad DLp and the substrate 100 . Then define the patterns of the protection layer 104 and the second insulating layer 202, form the first opening op1 and the second opening op2 on the gate DLg, and form the third opening op3 on the gate pad DLp, so that the semiconductor layer 103 is formed by the first opening op1, The second opening op2 and the third opening op3 are exposed.

Referring to FIG. 2C and FIG. 4C , a doped silicon layer 105 and a second conductive layer 106 are sequentially formed on the substrate 100 . The pattern of the second conductive layer 106 and the doped silicon layer 105 is defined to form a signal line SL, and a source S and a drain D are formed on the gate DLg, and the distance between the source S and the drain D is defined as A channel 110 is provided, and the second insulating layer 202 is exposed therein.

When etching the second conductive layer 106 and the doped silicon layer 105, the protective layer 104 and the second insulating layer 202 between the first opening op1 and the second opening op2 serve as an etching stop layer (etch stop; or island The etch stop layer IS) is used to protect the semiconductor layer 103 (ie, the channel layer) of the gate DLg from being damaged by etching.

Referring to FIG. 2D and FIG. 4D, first define the pattern of the semiconductor layer 103 and the first insulating layer 102 of the gate pad DLp, and remove the semiconductor layer 103 and the first insulating layer 102 in the third opening op3 to expose the gate pad DLp The first conductive layer 101 in. Next, a transparent electrode layer 107 is formed on the substrate 100 to cover the source S, the drain D and the gate pad DLp. Finally, define the pattern of the transparent electrode layer 107, form a pixel electrode layer PL coupled to the drain D, and a dummy signal line layer FS covering the source S and the signal line SL, and the transparent electrode layer 107 and the gate pad The first conductive layer 101 of the DLp constitutes an electrical contact.

In this embodiment, a thin layer of silicon nitride (ie, the second insulating layer 202 ) is further formed on the semiconductor layer 103 , thereby preventing the semiconductor layer 103 from being oxidized due to long-term exposure to air.

Embodiment three:

5A-5D show the top view of the manufacturing process of the third embodiment of the present invention. 6A-6D show cross-sectional views of the manufacturing process of the third embodiment of the present invention. In Figures 6A to 6D, Region I is the region where the thin film transistor is located, corresponding to the section along the A-A' direction in Figures 5A to 5D; Region II is the region where the gate pad structure is located, corresponding to Figures 5A to 5D Section along the B-B' direction in 5D. A method for manufacturing a thin film transistor applied to a flat panel display according to the present invention will be described below with reference to FIGS. 5A-5D and FIGS. 6A-6D .

Referring to FIG. 5A and FIG. 6A, and FIG. 5B and FIG. 6B, the first conductive layer 101, the first insulating layer 102, the semiconductor layer 103 and the protective layer 104 are used on the substrate 100 to define the scanning line DL and the gate pad DLp to be connected with Gate DLg. First, second and third openings op1 , op2 and op3 are respectively formed on the gate DLg and the gate pad DLp to expose the semiconductor layer 103 . The manufacturing process is the same as that described in the first embodiment, so it will not be repeated here.

Referring again to FIG. 5C and FIG. 6C , a doped silicon layer 105 and a second conductive layer 106 are formed on the substrate 100 . Next, the patterns of the second conductive layer 106 and the doped silicon layer 105 are defined, an island structure is formed above the gate, and a signal line SL is additionally formed. The signal line SL is perpendicular to the scan line DL, and the doped silicon layer 105 is in electrical contact with the semiconductor layer 103 of the gate DLg through the first and second openings (op1, op2).

Referring to FIG. 5D and FIG. 6D , first define the patterns of the semiconductor layer 103 and the first insulating layer 102 in the gate pad DLp, so that the first conductive layer 101 is exposed in the third opening op3 of the gate pad DLp. A transparent electrode layer 107 is formed on the substrate 100 to cover the second conductive layer 106 . Afterwards, patterns of the transparent electrode layer 107 , the second conductive layer 106 , and the doped silicon layer 105 are defined to form a source S and a drain D in the island structure. A channel 110 is defined between the source and the drain, and the channel 110 is directly above the gate DLg. In addition, the transparent electrode layer 107 forms a pixel electrode PL, which is connected to the drain D. The transparent electrode layer 107 also covers the source S of the signal line SL and the gate DLg. In addition, the transparent electrode layer 107 also covers the gate pad DLp, and is in contact with the first conductive layer 101 in the gate pad DLp through the third opening op3.

In this embodiment, the transparent electrode layer 107 is an ITO layer, and the transparent electrode layer 107 does not cover the sidewall of the second metal layer 106 in the channel 110 , so the size of the channel in the TFT can be reduced.

Embodiment four:

7A-7D show the top view of the manufacturing process of the fourth embodiment of the present invention. 8A-8D show cross-sectional views of the manufacturing process of the fourth embodiment of the present invention. In FIGS. 8A to 8D, the region I is where the thin film transistors are located, corresponding to the section along the A-A' direction in FIGS. 7A to 7D; Section along B-B' direction in 7D. The present embodiment will be described below with reference to FIGS. 7A to 7D and FIGS. 8A to 8D.

Referring to FIG. 7A and FIG. 8A, and FIG. 7B and FIG. 8B, on the substrate 100, the first conductive layer 101, the first insulating layer 102, the semiconductor layer 103 and the protective layer 104 are used to define the scanning line DL and the gate pad DLp to be compatible with Gate DLg. Then, the first, second, and third openings op1, op2, and op3 are respectively formed on the gate DLg and the gate pad DLp to expose the semiconductor layer 103. The manufacturing process is the same as that described in the first embodiment, so here Not to be repeated. In addition, a second insulating layer (not shown) can be formed on the semiconductor layer 103 to protect the semiconductor layer 103 .

Referring to FIG. 7C and FIG. 8C, a second metal layer 106 is formed on the protection layer 104, and defines the pattern of the signal line SL, and the signal line SL is perpendicular to the scanning line DL.

Referring to FIG. 7D and FIG. 8D , a doped layer 105 and a transparent electrode layer 107 are sequentially formed on the substrate 100 and cover the gate DLg and the signal line SL. Then define the patterns of the transparent electrode layer 107 and the doped layer 105 , define a drain D and a source S above the gate, and form a channel 110 between the drain D and the source S. In addition, the first portion TK1 of the transparent electrode layer 107 covers the signal line SL and is connected to the source S, and the doped silicon layer 105 in the source S is in contact with the semiconductor layer 103 through the first opening op1. The second part TK2 of the transparent electrode layer 107 forms a pixel electrode PL and is connected to the drain D, and the doped silicon layer 105 of the drain D is electrically connected to the semiconductor layer 103 through the second opening op2.

Finally, the semiconductor layer 103 and the first insulating layer 102 in the third opening are removed to expose the first conductive layer 101 in the gate pad DLp.

Embodiment five:

9A-9C show the top view of the manufacturing process of the fifth embodiment of the present invention. 10A-10C show cross-sectional views of the manufacturing process of the fifth embodiment of the present invention. In Figures 10A to 10C, Region I is the region where the thin film transistor is located, corresponding to the section along the A-A' direction in Figures 9A to 9C; Region II is the region where the gate pad (gatepad) structure is located, corresponding to Figures 9A to 9C Section along B-B' direction in 9C. The manufacturing method of the present invention will be described below with reference to FIGS. 9A to 9C and FIGS. 10A to 10C.

Referring to FIG. 9A and FIG. 10A , firstly, a first conductive layer 101 , an insulating layer 102 , and a semiconductor layer 103 are sequentially formed on a substrate 100 . Then define the patterns of the semiconductor layer 103 , the insulating layer 102 , and the first conductive layer 101 to form a scan line DL, a gate pad DLp, and a gate DLg. The gate pad DLp is formed at one end of the scan line DL, and the gate DLg extends from one side of the scan line DL. The semiconductor layer 103 on the gate DLg serves as a channel layer of the thin film transistor.

Referring to FIG. 9B and FIG. 10B, a protective layer 104 and a second conductive layer 106 are sequentially formed on the substrate 100, and then the pattern of the second conductive layer 106 and the protective layer 104 is defined so that it covers the scanning line DL and the gate DLg. with the gate pad DLp. The second conductive layer 106 and the passivation layer 104 also form a signal line SL on the substrate 100 , and the signal line SL is perpendicular to the scanning line DL. In addition, part of the second conductive layer 106 and the protective layer 104 are removed, a first opening op1 and a second opening op2 are formed on the gate DLg, and a third opening op3 is formed on the gate pad DLp, so that the semiconductor layer 103 is formed by the first The opening op1, the second opening op2 and the third opening op3 are exposed.

Referring to FIG. 9C and FIG. 10C , a doped silicon layer 305 and a transparent electrode layer 107 are formed on the substrate 100 , and the doped silicon layer 305 is electrically connected to the semiconductor layer 103 through the first opening op1 and the second opening op2 . Then define the pattern of etching the transparent electrode layer 107 and the doped silicon layer 305 to form a source S and a drain D above the gate DLg. A channel 110 is defined between the source S and the drain D. The first part T1 of the transparent electrode layer 107 is located on the signal line SL, the second part T2 of the transparent electrode layer 107 covers the source S, and the third part T3 of the transparent electrode layer 107 forms a pixel electrode PL and covers the drain D . Finally, the semiconductor layer 103 and the first insulating layer 102 in the third opening op3 are removed to expose the first conductive layer 101 of the gate pad DLp.

Through the above-mentioned embodiments 1 to 5, the present invention proposes a novel manufacturing method of a flat-panel thin film transistor display, in which only 4 photomasks are required in the manufacturing process (only 3 photomasks are required in the fifth embodiment). The main manufacturing process includes: (1) forming the first metal layer/gate insulating layer/amorphous silicon layer; (2) forming a passivation layer and an etching stopper layer; (3) forming a source/drain Pole (Source/Drain); (4) Forming the pixel electrode; this can simplify the manufacturing process of the thin film transistor flat panel display.

Although the present invention has been disclosed above in conjunction with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be defined by the claims.

Claims (14)

1. the manufacture method of a film transistor plane indicator comprises:

(a) provide a substrate, on aforesaid substrate, form one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn;

(b) limit the figure of above-mentioned semiconductor layer, first insulating barrier and first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed on an end of above-mentioned scan line;

(c) form a protective layer, be covered on above-mentioned scan line, gate pad, grid and the substrate;

(d) figure of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening on above-mentioned gate pad, and above-mentioned semiconductor layer is exposed in above-mentioned first, second and third opening;

(e) on aforesaid substrate, form a doped silicon layer and one second conductive layer in regular turn;

(f) pattern of above-mentioned second conductive layer of qualification and above-mentioned doped silicon layer, to form a holding wire, an and formation one source pole and a drain electrode above above-mentioned grid, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned source electrode contacts with the semiconductor layer of above-mentioned grid by above-mentioned first and second openings respectively with the doped silicon layer of drain electrode, and above-mentioned holding wire is perpendicular to above-mentioned scan line;

(g) pattern of semiconductor layer and insulating barrier in the above-mentioned gate pad of qualification removes above-mentioned semiconductor layer and insulating barrier in above-mentioned the 3rd opening, and above-mentioned first conductive layer is exposed in above-mentioned the 3rd opening;

(h) form a transparent electrode layer on aforesaid substrate, and cover above-mentioned source electrode, drain electrode and above-mentioned gate pad; And

(i) limit above-mentioned transparent electrode layer, couple a pixel electrode of above-mentioned drain electrode with formation.

2. manufacture method as claimed in claim 1, wherein, in step (i), above-mentioned transparent electrode layer also is formed on the above-mentioned holding wire, and above-mentioned transparent electrode layer contacts with first conductive layer of above-mentioned gate pad via above-mentioned the 3rd opening.

3. manufacture method as claimed in claim 1 wherein, in step (d), also forms one second insulating barrier on above-mentioned semiconductor layer.

4. manufacture method as claimed in claim 3, wherein, in step (d), above-mentioned first, second and the 3rd opening also run through above-mentioned second insulating barrier, make above-mentioned semiconductor layer be exposed to above-mentioned first, second and the 3rd opening.

5. manufacture method as claimed in claim 1, wherein, second conductive layer of above-mentioned source electrode and drain electrode respectively has a sidewall and is exposed in the above-mentioned channel, and above-mentioned transparency conducting layer covers the above-mentioned sidewall of second metal level in the above-mentioned channel.

6. manufacture method as claimed in claim 1, wherein, second conductive layer of above-mentioned source electrode and drain electrode respectively has a sidewall and is exposed in the above-mentioned channel, and above-mentioned transparency conducting layer does not cover the above-mentioned sidewall of second metal level in above-mentioned source electrode and the drain electrode.

7. the manufacture method of a film transistor plane indicator comprises:

(a) provide a substrate, on aforesaid substrate, form one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn;

(b) limit the figure of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line;

(c) form a protective layer, cover on above-mentioned scan line, gate pad, grid and the substrate;

(d) figure of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening above above-mentioned gate pad;

(e) on aforesaid substrate, form a doped silicon layer and one second conductive layer in regular turn;

(f) limit the pattern of above-mentioned second conductive layer and above-mentioned doped silicon layer, above above-mentioned grid, form an island structure, and above-mentioned doped silicon layer is respectively by above-mentioned first and second openings and contact with the semiconductor layer of above-mentioned grid;

(g) pattern of the semiconductor layer and first insulating barrier in the above-mentioned gate pad of qualification is exposed in above-mentioned the 3rd opening above-mentioned first conductive layer;

(i) on aforesaid substrate, form a transparent electrode layer, and cover above-mentioned second conductive layer; And

(j) limit above-mentioned transparent electrode layer, above-mentioned second conductive layer and above-mentioned doped silicon layer, in above-mentioned island structure, form an one source pole and a drain electrode, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned channel is positioned at above-mentioned grid top, above-mentioned transparent electrode layer also forms a pixel electrode, and couples above-mentioned drain electrode.

8. manufacture method as claimed in claim 7; wherein; in step (a), also form one second insulating barrier; in step (b), limit the pattern of above-mentioned second insulating barrier; and when step c) limits above-mentioned protective layer pattern, make above-mentioned second insulating layer exposing in above-mentioned first, second, with the 3rd opening in.

9. manufacture method as claimed in claim 7, wherein, in step (f), above-mentioned second metal level also forms a holding wire, and in step (j), above-mentioned transparent electrode layer also forms a dummy signal lines layer and covers above-mentioned holding wire.

10. the manufacture method of a Thin Film Transistor-LCD comprises:

(a) provide a substrate, on aforesaid substrate, form one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn;

(b) limit the pattern of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line;

(c) form a protective layer, cover on above-mentioned scan line, gate pad, grid and the substrate;

(d) pattern of the above-mentioned protective layer of qualification forms one first opening and one second opening on above-mentioned grid, and forms one the 3rd opening on above-mentioned gate pad;

(e) form one second conductive layer, limit the pattern of above-mentioned second conductive layer, on above-mentioned protective layer, form a holding wire, the vertical above-mentioned scan line of above-mentioned holding wire;

(f) on above-mentioned holding wire and above-mentioned protective layer, form a doped silicon layer and a transparent electrode layer in regular turn, and above-mentioned doped silicon layer is connected with the semiconductor layer of above-mentioned grid via above-mentioned first and second openings;

(g) limit above-mentioned transparent electrode layer and above-mentioned doped silicon layer, above above-mentioned grid, limit and form an one source pole and a drain electrode, be defined as a channel between above-mentioned source electrode and the drain electrode, above-mentioned transparent electrode layer also forms a pixel electrode, above-mentioned pixel electrode is connected with above-mentioned drain electrode, and above-mentioned source electrode is electrically connected with above-mentioned holding wire; And

(h) semiconductor layer and first insulating barrier in the above-mentioned gate pad of qualification etching is exposed in above-mentioned the 3rd opening above-mentioned first conductive layer.

11. manufacture method as claimed in claim 10 is further comprising the steps of:

In step (a), also form one second insulating barrier;

In step (b), limit the pattern of above-mentioned second insulating barrier;

When step (c) limits above-mentioned protective layer pattern, make above-mentioned second insulating layer exposing in above-mentioned first, second and the 3rd opening; And

In step (h), second insulating barrier in the above-mentioned gate pad of etching, semiconductor layer and first insulating barrier are exposed in above-mentioned the 3rd opening above-mentioned first conductive layer.

12. the manufacture method of a film transistor plane indicator comprises:

(a) provide a substrate, on aforesaid substrate, form one first conductive layer, one first insulating barrier and semi-conductor layer in regular turn;

(b) limit the pattern of above-mentioned semiconductor layer, above-mentioned first insulating barrier and above-mentioned first conductive layer, to form one scan line, a gate pad and a grid, above-mentioned gate pad is formed at an end of above-mentioned scan line;

(c) on aforesaid substrate, form a protective layer and one second conductive layer in regular turn, and cover above-mentioned gate pad and grid;

(d) pattern of above-mentioned second conductive layer of qualification and above-mentioned protective layer forms a holding wire on substrate, form one first opening and one second opening on above-mentioned grid, forms one the 3rd opening on above-mentioned gate pad;

(e) form a doped silicon layer and a transparent electrode layer in regular turn on above-mentioned holding wire, above-mentioned grid and aforesaid substrate, and above-mentioned doped silicon layer contacts with above-mentioned semiconductor layer via above-mentioned first opening and above-mentioned second opening; And

(f) limit the pattern of above-mentioned transparent electrode layer, above-mentioned doped layer and above-mentioned second conductive layer; above above-mentioned grid, form a drain electrode and an one source pole; being defined as a channel between above-mentioned drain electrode and the above-mentioned source electrode is exposed in the above-mentioned channel above-mentioned protective layer; above-mentioned transparent electrode layer also forms a pixel electrode, and above-mentioned pixel electrode is connected with above-mentioned drain electrode.

13. manufacture method as claimed in claim 12 comprises that also a step (g) limits the semiconductor layer and first insulating barrier of the above-mentioned gate pad of etching, to expose above-mentioned first conductive layer.

14. the manufacture method described in claim 13 is further comprising the steps of:

In step (a), also form one second insulating barrier;

In step (b), limit the pattern of above-mentioned second insulating barrier;

When step (c) limits above-mentioned protective layer pattern, make above-mentioned second insulating layer exposing in above-mentioned first, second, with the 3rd opening in; And

In step (g), second insulating barrier in the above-mentioned gate pad of etching, semiconductor layer and first insulating barrier are exposed in above-mentioned the 3rd opening above-mentioned first conductive layer.

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